Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477000538.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
..................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-4a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477000538
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 2.1M
-rw-r--r-- 1 mcc users 7.3K Feb 25 16:05 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 16:05 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.1K Feb 25 15:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 25 15:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 8.1K Feb 25 16:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 81K Feb 25 16:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.6K Feb 25 16:32 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 25 16:32 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.7M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-4a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678297792905

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-4a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-4a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA DLCflexbar-PT-4a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678298256059

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 11 (type EXCL) for 6 DLCflexbar-PT-4a-CTLFireability-02
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 1 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 1 0 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 1 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 1/189 1/32 DLCflexbar-PT-4a-CTLFireability-02 19609 m, 3921 m/sec, 831770 t fired, .

Time elapsed: 9 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 6/189 1/32 DLCflexbar-PT-4a-CTLFireability-02 202587 m, 36595 m/sec, 8196510 t fired, .

Time elapsed: 14 secs. Pages in use: 1
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 11/189 2/32 DLCflexbar-PT-4a-CTLFireability-02 383753 m, 36233 m/sec, 15735345 t fired, .

Time elapsed: 19 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 16/189 3/32 DLCflexbar-PT-4a-CTLFireability-02 567407 m, 36730 m/sec, 23267578 t fired, .

Time elapsed: 24 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 21/189 4/32 DLCflexbar-PT-4a-CTLFireability-02 745134 m, 35545 m/sec, 30763560 t fired, .

Time elapsed: 29 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 26/189 5/32 DLCflexbar-PT-4a-CTLFireability-02 924923 m, 35957 m/sec, 38197708 t fired, .

Time elapsed: 34 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 31/189 6/32 DLCflexbar-PT-4a-CTLFireability-02 1107010 m, 36417 m/sec, 45559966 t fired, .

Time elapsed: 39 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 36/189 6/32 DLCflexbar-PT-4a-CTLFireability-02 1273422 m, 33282 m/sec, 52668299 t fired, .

Time elapsed: 44 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 41/189 7/32 DLCflexbar-PT-4a-CTLFireability-02 1438940 m, 33103 m/sec, 59758515 t fired, .

Time elapsed: 49 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 46/189 8/32 DLCflexbar-PT-4a-CTLFireability-02 1607951 m, 33802 m/sec, 66828238 t fired, .

Time elapsed: 54 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 51/189 9/32 DLCflexbar-PT-4a-CTLFireability-02 1775629 m, 33535 m/sec, 73868875 t fired, .

Time elapsed: 59 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 56/189 9/32 DLCflexbar-PT-4a-CTLFireability-02 1941102 m, 33094 m/sec, 80969276 t fired, .

Time elapsed: 64 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 61/189 10/32 DLCflexbar-PT-4a-CTLFireability-02 2112206 m, 34220 m/sec, 87947814 t fired, .

Time elapsed: 69 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 66/189 11/32 DLCflexbar-PT-4a-CTLFireability-02 2279641 m, 33487 m/sec, 94993870 t fired, .

Time elapsed: 74 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 71/189 12/32 DLCflexbar-PT-4a-CTLFireability-02 2444786 m, 33029 m/sec, 101992261 t fired, .

Time elapsed: 79 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 76/189 13/32 DLCflexbar-PT-4a-CTLFireability-02 2606864 m, 32415 m/sec, 108993778 t fired, .

Time elapsed: 84 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 81/189 13/32 DLCflexbar-PT-4a-CTLFireability-02 2767453 m, 32117 m/sec, 115968102 t fired, .

Time elapsed: 89 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 86/189 14/32 DLCflexbar-PT-4a-CTLFireability-02 2928992 m, 32307 m/sec, 122942541 t fired, .

Time elapsed: 94 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 91/189 15/32 DLCflexbar-PT-4a-CTLFireability-02 3088525 m, 31906 m/sec, 129918684 t fired, .

Time elapsed: 99 secs. Pages in use: 15
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 96/189 16/32 DLCflexbar-PT-4a-CTLFireability-02 3250399 m, 32374 m/sec, 136880343 t fired, .

Time elapsed: 104 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 101/189 16/32 DLCflexbar-PT-4a-CTLFireability-02 3414853 m, 32890 m/sec, 143958979 t fired, .

Time elapsed: 109 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 106/189 17/32 DLCflexbar-PT-4a-CTLFireability-02 3574841 m, 31997 m/sec, 150923764 t fired, .

Time elapsed: 114 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 111/189 18/32 DLCflexbar-PT-4a-CTLFireability-02 3740666 m, 33165 m/sec, 157947726 t fired, .

Time elapsed: 119 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 116/189 19/32 DLCflexbar-PT-4a-CTLFireability-02 3904734 m, 32813 m/sec, 164878439 t fired, .

Time elapsed: 124 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 121/189 19/32 DLCflexbar-PT-4a-CTLFireability-02 4064165 m, 31886 m/sec, 171841051 t fired, .

Time elapsed: 129 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 126/189 20/32 DLCflexbar-PT-4a-CTLFireability-02 4226919 m, 32550 m/sec, 178950388 t fired, .

Time elapsed: 134 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 131/189 21/32 DLCflexbar-PT-4a-CTLFireability-02 4391153 m, 32846 m/sec, 186090501 t fired, .

Time elapsed: 139 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 136/189 22/32 DLCflexbar-PT-4a-CTLFireability-02 4553323 m, 32434 m/sec, 193109895 t fired, .

Time elapsed: 144 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 141/189 22/32 DLCflexbar-PT-4a-CTLFireability-02 4712650 m, 31865 m/sec, 200054404 t fired, .

Time elapsed: 149 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 146/189 23/32 DLCflexbar-PT-4a-CTLFireability-02 4872134 m, 31896 m/sec, 207022456 t fired, .

Time elapsed: 154 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 151/189 24/32 DLCflexbar-PT-4a-CTLFireability-02 5028428 m, 31258 m/sec, 213919138 t fired, .

Time elapsed: 159 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 156/189 24/32 DLCflexbar-PT-4a-CTLFireability-02 5191529 m, 32620 m/sec, 221036458 t fired, .

Time elapsed: 164 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 161/189 25/32 DLCflexbar-PT-4a-CTLFireability-02 5349181 m, 31530 m/sec, 227955902 t fired, .

Time elapsed: 169 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 166/189 26/32 DLCflexbar-PT-4a-CTLFireability-02 5505342 m, 31232 m/sec, 234791256 t fired, .

Time elapsed: 174 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 171/189 27/32 DLCflexbar-PT-4a-CTLFireability-02 5660855 m, 31102 m/sec, 241621717 t fired, .

Time elapsed: 179 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 176/189 27/32 DLCflexbar-PT-4a-CTLFireability-02 5822188 m, 32266 m/sec, 248701673 t fired, .

Time elapsed: 184 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 181/189 28/32 DLCflexbar-PT-4a-CTLFireability-02 5994718 m, 34506 m/sec, 255668512 t fired, .

Time elapsed: 189 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 186/189 29/32 DLCflexbar-PT-4a-CTLFireability-02 6154552 m, 31966 m/sec, 262617610 t fired, .

Time elapsed: 194 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 11 (type EXCL) for DLCflexbar-PT-4a-CTLFireability-02 (local timeout)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 1 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 199 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 58 (type EXCL) for 57 DLCflexbar-PT-4a-CTLFireability-15
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 11 (type EXCL) for 6 DLCflexbar-PT-4a-CTLFireability-02
lola: time limit : 3401 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/3401 1/5 DLCflexbar-PT-4a-CTLFireability-02 180313 m, -1194847 m/sec, 7289012 t fired, .
58 CTL EXCL 5/188 1/32 DLCflexbar-PT-4a-CTLFireability-15 147188 m, 29437 m/sec, 4850996 t fired, .

Time elapsed: 204 secs. Pages in use: 30
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 10/3401 2/5 DLCflexbar-PT-4a-CTLFireability-02 354646 m, 34866 m/sec, 14549796 t fired, .
58 CTL EXCL 10/179 2/32 DLCflexbar-PT-4a-CTLFireability-15 308249 m, 32212 m/sec, 9722267 t fired, .

Time elapsed: 209 secs. Pages in use: 30
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 15/3401 3/5 DLCflexbar-PT-4a-CTLFireability-02 529701 m, 35011 m/sec, 21673791 t fired, .
58 CTL EXCL 15/179 3/32 DLCflexbar-PT-4a-CTLFireability-15 467115 m, 31773 m/sec, 14534091 t fired, .

Time elapsed: 214 secs. Pages in use: 30
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 20/3401 4/5 DLCflexbar-PT-4a-CTLFireability-02 701565 m, 34372 m/sec, 28918428 t fired, .
58 CTL EXCL 20/179 4/32 DLCflexbar-PT-4a-CTLFireability-15 619525 m, 30482 m/sec, 19378153 t fired, .

Time elapsed: 219 secs. Pages in use: 30
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 25/3401 5/5 DLCflexbar-PT-4a-CTLFireability-02 876725 m, 35032 m/sec, 36145608 t fired, .
58 CTL EXCL 25/179 5/32 DLCflexbar-PT-4a-CTLFireability-15 784872 m, 33069 m/sec, 24248926 t fired, .

Time elapsed: 224 secs. Pages in use: 30
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 1 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 30/3401 5/5 DLCflexbar-PT-4a-CTLFireability-02 1057693 m, 36193 m/sec, 43440067 t fired, .
58 CTL EXCL 30/179 6/32 DLCflexbar-PT-4a-CTLFireability-15 948106 m, 32646 m/sec, 29198752 t fired, .

Time elapsed: 229 secs. Pages in use: 30
# running tasks: 2 of 4 Visible: 16
lola: CANCELED task # 11 (type EXCL) for DLCflexbar-PT-4a-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 35/179 6/32 DLCflexbar-PT-4a-CTLFireability-15 1110422 m, 32463 m/sec, 34229330 t fired, .

Time elapsed: 234 secs. Pages in use: 30
# running tasks: 2 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 40/188 7/32 DLCflexbar-PT-4a-CTLFireability-15 1278146 m, 33544 m/sec, 39284279 t fired, .

Time elapsed: 239 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 45/188 8/32 DLCflexbar-PT-4a-CTLFireability-15 1447919 m, 33954 m/sec, 44235552 t fired, .

Time elapsed: 244 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 50/188 9/32 DLCflexbar-PT-4a-CTLFireability-15 1624144 m, 35245 m/sec, 49186924 t fired, .

Time elapsed: 249 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 55/188 10/32 DLCflexbar-PT-4a-CTLFireability-15 1789997 m, 33170 m/sec, 54090596 t fired, .

Time elapsed: 254 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 60/188 11/32 DLCflexbar-PT-4a-CTLFireability-15 1960209 m, 34042 m/sec, 58894865 t fired, .

Time elapsed: 259 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 65/188 12/32 DLCflexbar-PT-4a-CTLFireability-15 2127464 m, 33451 m/sec, 63608600 t fired, .

Time elapsed: 264 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 70/188 13/32 DLCflexbar-PT-4a-CTLFireability-15 2285808 m, 31668 m/sec, 68577998 t fired, .

Time elapsed: 269 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 75/188 14/32 DLCflexbar-PT-4a-CTLFireability-15 2448367 m, 32511 m/sec, 73363200 t fired, .

Time elapsed: 274 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 80/188 14/32 DLCflexbar-PT-4a-CTLFireability-15 2609788 m, 32284 m/sec, 78160825 t fired, .

Time elapsed: 279 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 85/188 15/32 DLCflexbar-PT-4a-CTLFireability-15 2774483 m, 32939 m/sec, 82941160 t fired, .

Time elapsed: 284 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 90/188 16/32 DLCflexbar-PT-4a-CTLFireability-15 2945382 m, 34179 m/sec, 87821332 t fired, .

Time elapsed: 289 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 95/188 17/32 DLCflexbar-PT-4a-CTLFireability-15 3128790 m, 36681 m/sec, 92793204 t fired, .

Time elapsed: 294 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 100/188 18/32 DLCflexbar-PT-4a-CTLFireability-15 3284994 m, 31240 m/sec, 97617351 t fired, .

Time elapsed: 299 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 105/188 19/32 DLCflexbar-PT-4a-CTLFireability-15 3445590 m, 32119 m/sec, 102504001 t fired, .

Time elapsed: 304 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 110/188 20/32 DLCflexbar-PT-4a-CTLFireability-15 3606190 m, 32120 m/sec, 107397991 t fired, .

Time elapsed: 309 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 115/188 21/32 DLCflexbar-PT-4a-CTLFireability-15 3773468 m, 33455 m/sec, 112343386 t fired, .

Time elapsed: 314 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 120/188 22/32 DLCflexbar-PT-4a-CTLFireability-15 3929514 m, 31209 m/sec, 117106781 t fired, .

Time elapsed: 319 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 125/188 22/32 DLCflexbar-PT-4a-CTLFireability-15 4079146 m, 29926 m/sec, 121783972 t fired, .

Time elapsed: 324 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 130/188 23/32 DLCflexbar-PT-4a-CTLFireability-15 4234106 m, 30992 m/sec, 126568119 t fired, .

Time elapsed: 329 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 135/188 24/32 DLCflexbar-PT-4a-CTLFireability-15 4380300 m, 29238 m/sec, 131178604 t fired, .

Time elapsed: 334 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 140/188 25/32 DLCflexbar-PT-4a-CTLFireability-15 4533696 m, 30679 m/sec, 135967816 t fired, .

Time elapsed: 339 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 145/188 26/32 DLCflexbar-PT-4a-CTLFireability-15 4689551 m, 31171 m/sec, 140850395 t fired, .

Time elapsed: 344 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 150/188 27/32 DLCflexbar-PT-4a-CTLFireability-15 4860713 m, 34232 m/sec, 145780498 t fired, .

Time elapsed: 349 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 155/188 28/32 DLCflexbar-PT-4a-CTLFireability-15 5040245 m, 35906 m/sec, 150693356 t fired, .

Time elapsed: 354 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 160/188 28/32 DLCflexbar-PT-4a-CTLFireability-15 5196929 m, 31336 m/sec, 155574204 t fired, .

Time elapsed: 359 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 165/188 29/32 DLCflexbar-PT-4a-CTLFireability-15 5374472 m, 35508 m/sec, 160459245 t fired, .

Time elapsed: 364 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 170/188 30/32 DLCflexbar-PT-4a-CTLFireability-15 5538101 m, 32725 m/sec, 165328021 t fired, .

Time elapsed: 369 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 175/188 31/32 DLCflexbar-PT-4a-CTLFireability-15 5708553 m, 34090 m/sec, 170194305 t fired, .

Time elapsed: 374 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
58 CTL EXCL 180/188 32/32 DLCflexbar-PT-4a-CTLFireability-15 5874034 m, 33096 m/sec, 175071059 t fired, .

Time elapsed: 379 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 58 (type EXCL) for DLCflexbar-PT-4a-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 384 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 55 (type EXCL) for 54 DLCflexbar-PT-4a-CTLFireability-14
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for DLCflexbar-PT-4a-CTLFireability-14
lola: result : true
lola: markings : 617
lola: fired transitions : 5468
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 47 DLCflexbar-PT-4a-CTLFireability-13
lola: time limit : 201 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for DLCflexbar-PT-4a-CTLFireability-13
lola: result : true
lola: markings : 2
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 47 DLCflexbar-PT-4a-CTLFireability-13
lola: time limit : 214 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 5/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 1648 m, 329 m/sec, 135091 t fired, .

Time elapsed: 389 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 10/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 3389 m, 348 m/sec, 293222 t fired, .

Time elapsed: 394 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 15/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 5140 m, 350 m/sec, 453150 t fired, .

Time elapsed: 399 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 20/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 6898 m, 351 m/sec, 611896 t fired, .

Time elapsed: 404 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 25/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 8612 m, 342 m/sec, 762715 t fired, .

Time elapsed: 409 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 30/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 10342 m, 346 m/sec, 924823 t fired, .

Time elapsed: 414 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 35/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 11418 m, 215 m/sec, 1029488 t fired, .

Time elapsed: 419 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 42/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 12587 m, 233 m/sec, 1141153 t fired, .

Time elapsed: 426 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 47/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 13505 m, 183 m/sec, 1222504 t fired, .

Time elapsed: 431 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 52/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 14468 m, 192 m/sec, 1315016 t fired, .

Time elapsed: 436 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 57/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 15078 m, 122 m/sec, 1371735 t fired, .

Time elapsed: 441 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 64/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 16241 m, 232 m/sec, 1486235 t fired, .

Time elapsed: 448 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 69/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 17068 m, 165 m/sec, 1566540 t fired, .

Time elapsed: 453 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-4a-CTLFireability-14: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-4a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-02: DISJ 0 1 0 0 2 0 1 0
DLCflexbar-PT-4a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
DLCflexbar-PT-4a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-4a-CTLFireability-13: CONJ 0 0 1 0 3 0 0 0
DLCflexbar-PT-4a-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
50 CTL EXCL 76/214 1/32 DLCflexbar-PT-4a-CTLFireability-13 18291 m, 244 m/sec, 1684612 t fired, .

Time elapsed: 460 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/bin//../lola/bin//../BenchKit_head.sh: line 63: 377 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-4a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-4a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477000538"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-4a.tgz
mv DLCflexbar-PT-4a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;