About the Execution of LoLA for DLCflexbar-PT-2b
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
11521.008 | 246199.00 | 259517.00 | 659.50 | FT?????T?FTTT?FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814477000514.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-2b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814477000514
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 1.9M
-rw-r--r-- 1 mcc users 7.3K Feb 25 15:02 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 25 15:02 CTLCardinality.xml
-rw-r--r-- 1 mcc users 4.9K Feb 25 15:02 CTLFireability.txt
-rw-r--r-- 1 mcc users 42K Feb 25 15:02 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 15:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 129K Feb 25 15:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.7K Feb 25 15:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 25 15:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.5M Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-00
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-01
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-02
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-03
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-04
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-05
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-06
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-07
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-08
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-09
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-10
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-11
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-12
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-13
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-14
FORMULA_NAME DLCflexbar-PT-2b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678295771000
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-2b
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-2b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DLCflexbar-PT-2b-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-2b-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-2b-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-2b-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-2b-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-2b-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-2b-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-2b-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DLCflexbar-PT-2b-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678296017199
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-2b-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-10: EF 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 0 0 0 5 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 15 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 66 (type EXCL) for 36 DLCflexbar-PT-2b-CTLFireability-12
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 64 (type FNDP) for 36 DLCflexbar-PT-2b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 36 DLCflexbar-PT-2b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SRCH) for 36 DLCflexbar-PT-2b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 66 (type EXCL) for DLCflexbar-PT-2b-CTLFireability-12
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 64 (type FNDP) for DLCflexbar-PT-2b-CTLFireability-12 (obsolete)
lola: CANCELED task # 65 (type EQUN) for DLCflexbar-PT-2b-CTLFireability-12 (obsolete)
lola: CANCELED task # 67 (type SRCH) for DLCflexbar-PT-2b-CTLFireability-12 (obsolete)
lola: FINISHED task # 64 (type FNDP) for DLCflexbar-PT-2b-CTLFireability-12
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 67 (type SRCH) for DLCflexbar-PT-2b-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-65.sara.
lola: FINISHED task # 65 (type EQUN) for DLCflexbar-PT-2b-CTLFireability-12
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:738
lola: rewrite Frontend/Parser/formula_rewrite.k:694
lola: LAUNCH task # 39 (type EXCL) for 36 DLCflexbar-PT-2b-CTLFireability-12
lola: time limit : 188 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 69 (type FNDP) for 30 DLCflexbar-PT-2b-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type EQUN) for 30 DLCflexbar-PT-2b-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type SRCH) for 30 DLCflexbar-PT-2b-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:737
lola: rewrite Frontend/Parser/formula_rewrite.k:693
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 72 (type SRCH) for DLCflexbar-PT-2b-CTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 69 (type FNDP) for DLCflexbar-PT-2b-CTLFireability-10
lola: result : true
lola: fired transitions : 3
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 70 (type EQUN) for DLCflexbar-PT-2b-CTLFireability-10 (obsolete)
lola: FINISHED task # 39 (type EXCL) for DLCflexbar-PT-2b-CTLFireability-12
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 73 (type EXCL) for 36 DLCflexbar-PT-2b-CTLFireability-12
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 73 (type EXCL) for DLCflexbar-PT-2b-CTLFireability-12
lola: result : true
lola: markings : 173
lola: fired transitions : 173
lola: time used : 0.000000
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lola: LAUNCH task # 68 (type EXCL) for 18 DLCflexbar-PT-2b-CTLFireability-06
lola: time limit : 223 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/CTLFireability-70.sara.
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lola: FINISHED task # 70 (type EQUN) for DLCflexbar-PT-2b-CTLFireability-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
68 AGEF EXCL 3/223 1/32 DLCflexbar-PT-2b-CTLFireability-06 103801 m, 20760 m/sec, 248125 t fired, .
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 1 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
68 AGEF EXCL 8/223 2/32 DLCflexbar-PT-2b-CTLFireability-06 212652 m, 21770 m/sec, 505653 t fired, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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lola: rewrite Frontend/Parser/formula_rewrite.k:812
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lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-2b-CTLFireability-10: EF true findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DLCflexbar-PT-2b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
68 AGEF EXCL 13/223 4/32 DLCflexbar-PT-2b-CTLFireability-06 743641 m, 106197 m/sec, 1728298 t fired, .
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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68 AGEF EXCL 18/223 7/32 DLCflexbar-PT-2b-CTLFireability-06 1421782 m, 135628 m/sec, 3246588 t fired, .
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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68 AGEF EXCL 23/223 10/32 DLCflexbar-PT-2b-CTLFireability-06 2093422 m, 134328 m/sec, 4763536 t fired, .
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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68 AGEF EXCL 28/223 13/32 DLCflexbar-PT-2b-CTLFireability-06 2766665 m, 134648 m/sec, 6283137 t fired, .
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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68 AGEF EXCL 33/223 17/32 DLCflexbar-PT-2b-CTLFireability-06 3449321 m, 136531 m/sec, 7829460 t fired, .
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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68 AGEF EXCL 38/223 20/32 DLCflexbar-PT-2b-CTLFireability-06 4122091 m, 134554 m/sec, 9369853 t fired, .
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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68 AGEF EXCL 43/223 23/32 DLCflexbar-PT-2b-CTLFireability-06 4784869 m, 132555 m/sec, 10883954 t fired, .
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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68 AGEF EXCL 48/223 26/32 DLCflexbar-PT-2b-CTLFireability-06 5448434 m, 132713 m/sec, 12374061 t fired, .
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DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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68 AGEF EXCL 53/223 29/32 DLCflexbar-PT-2b-CTLFireability-06 6103429 m, 130999 m/sec, 13869980 t fired, .
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DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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lola: markings : 139
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
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DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 2 0 0 11 0 0 0
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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DLCflexbar-PT-2b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
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DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
DLCflexbar-PT-2b-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
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DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
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DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
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DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
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DLCflexbar-PT-2b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-07: EXEF 0 1 0 0 1 0 0 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
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DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
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DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
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DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
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DLCflexbar-PT-2b-CTLFireability-09: CTL false CTL model checker
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DLCflexbar-PT-2b-CTLFireability-11: CTL true CTL model checker
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 30/683 29/32 DLCflexbar-PT-2b-CTLFireability-03 1901044 m, 62730 m/sec, 2149484 t fired, .
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DLCflexbar-PT-2b-CTLFireability-10: EF true findpath
DLCflexbar-PT-2b-CTLFireability-11: CTL true CTL model checker
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DLCflexbar-PT-2b-CTLFireability-10: EF true findpath
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DLCflexbar-PT-2b-CTLFireability-11: CTL true CTL model checker
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DLCflexbar-PT-2b-CTLFireability-09: CTL false CTL model checker
DLCflexbar-PT-2b-CTLFireability-10: EF true findpath
DLCflexbar-PT-2b-CTLFireability-11: CTL true CTL model checker
DLCflexbar-PT-2b-CTLFireability-14: CTL false CTL model checker
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DLCflexbar-PT-2b-CTLFireability-06: EFAG 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DLCflexbar-PT-2b-CTLFireability-12: DISJ 0 1 0 0 12 0 0 0
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lola: LAUNCH task # 4 (type EXCL) for 3 DLCflexbar-PT-2b-CTLFireability-01
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lola: FINISHED task # 4 (type EXCL) for DLCflexbar-PT-2b-CTLFireability-01
lola: result : true
lola: markings : 139
lola: fired transitions : 278
lola: time used : 0.000000
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lola: result : false
lola: time used : 0.000000
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lola: result : false
lola: markings : 29
lola: fired transitions : 87
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DLCflexbar-PT-2b-CTLFireability-00: CTL false CTL model checker
DLCflexbar-PT-2b-CTLFireability-01: CTL true CTL model checker
DLCflexbar-PT-2b-CTLFireability-02: CTL unknown AGGR
DLCflexbar-PT-2b-CTLFireability-03: CTL unknown AGGR
DLCflexbar-PT-2b-CTLFireability-04: CTL unknown AGGR
DLCflexbar-PT-2b-CTLFireability-05: CTL unknown AGGR
DLCflexbar-PT-2b-CTLFireability-06: EFAG unknown AGGR
DLCflexbar-PT-2b-CTLFireability-07: EXEF true state space /EXEF
DLCflexbar-PT-2b-CTLFireability-08: CTL unknown AGGR
DLCflexbar-PT-2b-CTLFireability-09: CTL false CTL model checker
DLCflexbar-PT-2b-CTLFireability-10: EF true findpath
DLCflexbar-PT-2b-CTLFireability-11: CTL true CTL model checker
DLCflexbar-PT-2b-CTLFireability-12: DISJ true DISJ
DLCflexbar-PT-2b-CTLFireability-13: CTL unknown AGGR
DLCflexbar-PT-2b-CTLFireability-14: CTL false CTL model checker
DLCflexbar-PT-2b-CTLFireability-15: CTL true CTL model checker
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-2b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-2b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477000514"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-2b.tgz
mv DLCflexbar-PT-2b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;