MCC'2023- Execution of r102-tall-167814477000506

About the Execution of LoLA for DLCflexbar-PT-2a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
0.000	666073.00	0.00	0.00	T?????T???????TT	normal

Execution Chart

Sorry, for this execution, no execution chart could be reported.

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r
Waiting for the VM to be ready
...................................
=============
Generated by BenchKit 2-5348
Executing tool lola
Input is DLCflexbar-PT-2a,
Time confinement is 3600
Memory confinement is
Number of cores is 4
Run identifier is r102-tall-167
===================================

--------------------
preparation of the directory
/home/mcc/execution
total 948K
-rw-r--r-- 1 mcc users 6.2K
-rw-r--r-- 1 mcc users 68K
-rw-r--r-- 1 mcc users 5.3K
-rw-r--r-- 1 mcc users 48K
-rw-r--r-- 1 mcc users 4.2K
-rw-r--r-- 1 mcc users 6.4K
-rw-r--r-- 1 mcc users 3.7K
-rw-r--r-- 1 mcc users 26K
-rw-r--r-- 1 mcc users 2.2K
-rw-r--r-- 1 mcc users 16K
-rw-r--r-- 1 mcc users 7.9K
-rw-r--r-- 1 mcc users 78K
-rw-r--r-- 1 mcc users 9.1K
-rw-r--r-- 1 mcc users 79K
-rw-r--r-- 1 mcc users 1.6K
-rw-r--r-- 1 mcc users 3.6K
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 3 Mar
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 545K Mar

--------------------
content from stdout:

=== Data for post analysis

The expected result is a vector
BOOL_VECTOR

here is the order used to
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi
FORMULA_NAME DLCflexbar-PT-2a-CTLFi

=== Now, execution of the

BK_START 1678295075813

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DLCflexbar-PT-2a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DLCflexbar-PT-2a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/b
current directory: /home/mcc/execut
CTLFireability

FORMULA DLCflexbar-PT-2a-CTLFireability-00

FORMULA DLCflexbar-PT-2a-CTLFireability-06

FORMULA DLCflexbar-PT-2a-CTLFireability-15

FORMULA DLCflexbar-PT-2a-CTLFireability-14

BK_STOP 1678295741886

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet
lola: reading net from /home/mcc/
lola: reading pnml
lola: PNML file contains
lola: finished parsing
lola: closed net file /home/mcc/e
lola: Reading formula.
lola: Using XML format (--xmlform
lola: reading XML formula
lola: reading formula from
lola: rewrite Frontend/Parser/for
lola: rewrite Frontend/Parser/for
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lola: RELEASE
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lola: RELEASE
lola: Created skeleton in
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lola: Rule S: 0 transitions
lola: Created skeleton in
lola: NOTDEADLOCKFREE
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lola: rewrite Frontend/Parser/for
lola: rewrite Frontend/Parser/for
lola: rewrite Frontend/Parser/for
lola: LAUNCH task # 1 (type
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/for
lola: LAUNCH task # 52 (type
lola: time limit : 32000000
lola: memory limit: 5 pages
lola: FINISHED task # 52
lola: result : true
lola: time used :
lola: memory pages used :
lola: FINISHED task # 1
lola: result : true
lola: markings :
lola: fired transitions :
lola: time used :
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lola: LAUNCH task # 21 (type
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 21
lola: result : true
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: Created skeleton in
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lola: LAUNCH task # 7 (type
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/for
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FINISHED FORMULA: CATEGORY
DLCflexbar-PT-2a-CTLFireability-00:
DLCflexbar-PT-2a-CTLFireability-06:

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======================================================== examination is CTLFireability seconds 16384 MBytes 814477000506 ================================== to be used: Feb 25 15:50 CTLCardinality.txt Feb 25 15:50 CTLCardinality.xml Feb 25 15:23 CTLFireability.txt Feb 25 15:23 CTLFireability.xml Jan 29 11:40 GenericPropertiesDefinition.xml Jan 29 11:40 GenericPropertiesVerdict.xml Feb 25 15:51 LTLCardinality.txt Feb 25 15:51 LTLCardinality.xml Feb 25 15:51 LTLFireability.txt Feb 25 15:51 LTLFireability.xml Feb 25 16:41 ReachabilityCardinality.txt Feb 25 16:41 ReachabilityCardinality.xml Feb 25 16:18 ReachabilityFireability.txt Feb 25 16:18 ReachabilityFireability.xml Feb 25 15:51 UpperBounds.txt Feb 25 15:51 UpperBounds.xml 5 18:22 equiv_col 5 18:22 instance 5 18:22 iscolored 5 18:22 model.pnml generated by BenchKit (invocation template) of booleans build the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 tool begins 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N in//../lola/bin/ ion TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT ) execution/model.pnml place/transition net xecution/model.pnml ula) /home/mcc/execution/CTLFireability.xml mula_rewrite.k:394 mula_rewrite.k:394 mula_rewrite.k:325 mula_rewrite.k:337 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:314 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:337 mula_rewrite.k:296 mula_rewrite.k:296 mula_rewrite.k:322 mula_rewrite.k:328 mula_rewrite.k:296 mula_rewrite.k:250 mula_rewrite.k:317 mula_rewrite.k:322 mula_rewrite.k:340 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:299 mula_rewrite.k:317 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:299 mula_rewrite.k:322 mula_rewrite.k:340 mula_rewrite.k:299 mula_rewrite.k:299 mula_rewrite.k:314 mula_rewrite.k:322 mula_rewrite.k:331 mula_rewrite.k:317 mula_rewrite.k:296 mula_rewrite.k:317 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:322 mula_rewrite.k:337 mula_rewrite.k:314 mula_rewrite.k:296 mula_rewrite.k:314 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:314 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:331 mula_rewrite.k:299 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:322 mula_rewrite.k:337 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:328 mula_rewrite.k:296 mula_rewrite.k:250 mula_rewrite.k:314 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:314 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:322 mula_rewrite.k:337 mula_rewrite.k:296 mula_rewrite.k:296 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:325 mula_rewrite.k:337 mula_rewrite.k:296 mula_rewrite.k:296 mula_rewrite.k:253 mula_rewrite.k:253 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:317 mula_rewrite.k:325 mula_rewrite.k:337 mula_rewrite.k:314 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:331 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:299 mula_rewrite.k:314 mula_rewrite.k:296 mula_rewrite.k:317 mula_rewrite.k:322 mula_rewrite.k:331 mula_rewrite.k:296 mula_rewrite.k:314 mula_rewrite.k:296 mula_rewrite.k:322 mula_rewrite.k:331 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:331 mula_rewrite.k:314 mula_rewrite.k:322 mula_rewrite.k:340 mula_rewrite.k:317 mula_rewrite.k:299 mula_rewrite.k:322 mula_rewrite.k:328 mula_rewrite.k:299 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:317 mula_rewrite.k:299 mula_rewrite.k:314 mula_rewrite.k:325 mula_rewrite.k:328 mula_rewrite.k:299 mula_rewrite.k:317 mula_rewrite.k:299 mula_rewrite.k:325 mula_rewrite.k:328 mula_rewrite.k:299 mula_rewrite.k:325 mula_rewrite.k:331 mula_rewrite.k:322 mula_rewrite.k:328 mula_rewrite.k:296 mula_rewrite.k:463 mula_rewrite.k:475 mula_rewrite.k:448 mula_rewrite.k:472 mula_rewrite.k:253 mula_rewrite.k:250 mula_rewrite.k:472 mula_rewrite.k:250 mula_rewrite.k:250 mula_rewrite.k:454 mula_rewrite.k:544 mula_rewrite.k:317 mula_rewrite.k:314 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:296 mula_rewrite.k:317 mula_rewrite.k:314 mula_rewrite.k:296 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:314 mula_rewrite.k:322 mula_rewrite.k:331 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:337 mula_rewrite.k:296 mula_rewrite.k:296 mula_rewrite.k:250 mula_rewrite.k:250 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:325 mula_rewrite.k:331 mula_rewrite.k:296 mula_rewrite.k:454 mula_rewrite.k:445 mula_rewrite.k:325 mula_rewrite.k:331 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:253 mula_rewrite.k:314 mula_rewrite.k:325 mula_rewrite.k:331 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:337 mula_rewrite.k:296 mula_rewrite.k:296 mula_rewrite.k:322 mula_rewrite.k:331 mula_rewrite.k:317 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:322 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:391 mula_rewrite.k:322 mula_rewrite.k:328 mula_rewrite.k:296 mula_rewrite.k:314 mula_rewrite.k:322 mula_rewrite.k:331 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:296 mula_rewrite.k:314 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:325 mula_rewrite.k:331 mula_rewrite.k:299 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:322 mula_rewrite.k:337 mula_rewrite.k:296 mula_rewrite.k:325 mula_rewrite.k:334 mula_rewrite.k:296 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. removed,0 places removed 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. 0.000000 secs. mula_rewrite.k:814 mula_rewrite.k:806 mula_rewrite.k:730 EXCL) for 0 DLCflexbar-PT-2a-CTLFireability-00 mula_rewrite.k:807 SKEL/SRCH) for 46 DLCflexbar-PT-2a-CTLFireability-14 sec (type SKEL/SRCH) for DLCflexbar-PT-2a-CTLFireability-14 0.000000 1 (type EXCL) for DLCflexbar-PT-2a-CTLFireability-00 3 3 0.000000 1 EXCL) for 18 DLCflexbar-PT-2a-CTLFireability-06 (type EXCL) for DLCflexbar-PT-2a-CTLFireability-06 45 1021 0.000000 1 0.000000 secs. mula_rewrite.k:807 mula_rewrite.k:812 mula_rewrite.k:809 mula_rewrite.k:809 mula_rewrite.k:812 mula_rewrite.k:808 mula_rewrite.k:807 mula_rewrite.k:813 mula_rewrite.k:810 mula_rewrite.k:806 mula_rewrite.k:807 mula_rewrite.k:807 mula_rewrite.k:814 mula_rewrite.k:813 EXCL) for 6 DLCflexbar-PT-2a-CTLFireability-02 mula_rewrite.k:806 mula_rewrite.k:807 mula_rewrite.k:809 mula_rewrite.k:811 mula_rewrite.k:811 mula_rewrite.k:813 mula_rewrite.k:813 mula_rewrite.k:807 mula_rewrite.k:814 mula_rewrite.k:813 mula_rewrite.k:806 mula_rewrite.k:703 mula_rewrite.k:812 mula_rewrite.k:807 mula_rewrite.k:806 mula_rewrite.k:813 mula_rewrite.k:808 mula_rewrite.k:806 mula_rewrite.k:813 mula_rewrite.k:809 mula_rewrite.k:807 mula_rewrite.k:807 mula_rewrite.k:808 mula_rewrite.k:815 mula_rewrite.k:812 mula_rewrite.k:811 mula_rewrite.k:808 mula_rewrite.k:806 mula_rewrite.k:814 mula_rewrite.k:812 mula_rewrite.k:814 mula_rewrite.k:813 mula_rewrite.k:806 mula_rewrite.k:813 mula_rewrite.k:812 mula_rewrite.k:808 mula_rewrite.k:813 mula_rewrite.k:812 mula_rewrite.k:812 mula_rewrite.k:810 mula_rewrite.k:812 mula_rewrite.k:812 mula_rewrite.k:807 mula_rewrite.k:814 mula_rewrite.k:813 mula_rewrite.k:811 mula_rewrite.k:810 mula_rewrite.k:812 mula_rewrite.k:812 mula_rewrite.k:812 mula_rewrite.k:810 mula_rewrite.k:815 mula_rewrite.k:807 mula_rewrite.k:813 mula_rewrite.k:807 mula_rewrite.k:812 mula_rewrite.k:806 mula_rewrite.k:806 mula_rewrite.k:809 mula_rewrite.k:813 mula_rewrite.k:815 mula_rewrite.k:809 mula_rewrite.k:807 mula_rewrite.k:807 mula_rewrite.k:808 mula_rewrite.k:806 mula_rewrite.k:812 mula_rewrite.k:814 mula_rewrite.k:807 mula_rewrite.k:813 mula_rewrite.k:809 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCflexbar-PT-2a-CTLFireability-02 152829 m, 30565 m/sec, 3363806 t fired, . Pages in use: 2 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCflexbar-PT-2a-CTLFireability-02 326136 m, 34661 m/sec, 7182992 t fired, . Pages in use: 2 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCflexbar-PT-2a-CTLFireability-02 493040 m, 33380 m/sec, 10922275 t fired, . Pages in use: 3 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCflexbar-PT-2a-CTLFireability-02 666145 m, 34621 m/sec, 14767157 t fired, . Pages in use: 3 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCflexbar-PT-2a-CTLFireability-02 839633 m, 34697 m/sec, 18613762 t fired, . Pages in use: 4 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCflexbar-PT-2a-CTLFireability-02 1009445 m, 33962 m/sec, 22360711 t fired, . Pages in use: 5 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCflexbar-PT-2a-CTLFireability-02 1179280 m, 33967 m/sec, 26090631 t fired, . Pages in use: 5 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCflexbar-PT-2a-CTLFireability-02 1343320 m, 32808 m/sec, 29751579 t fired, . Pages in use: 6 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCflexbar-PT-2a-CTLFireability-02 1507354 m, 32806 m/sec, 33425447 t fired, . Pages in use: 7 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCflexbar-PT-2a-CTLFireability-02 1675737 m, 33676 m/sec, 37125210 t fired, . Pages in use: 7 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCflexbar-PT-2a-CTLFireability-02 1839439 m, 32740 m/sec, 40764036 t fired, . Pages in use: 8 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCflexbar-PT-2a-CTLFireability-02 2005403 m, 33192 m/sec, 44417309 t fired, . Pages in use: 9 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCflexbar-PT-2a-CTLFireability-02 2165907 m, 32100 m/sec, 47984932 t fired, . Pages in use: 9 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCflexbar-PT-2a-CTLFireability-02 2325805 m, 31979 m/sec, 51559199 t fired, . Pages in use: 10 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCflexbar-PT-2a-CTLFireability-02 2494716 m, 33782 m/sec, 55262778 t fired, . Pages in use: 11 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCflexbar-PT-2a-CTLFireability-02 2662208 m, 33498 m/sec, 58943094 t fired, . Pages in use: 11 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 DLCflexbar-PT-2a-CTLFireability-02 2828400 m, 33238 m/sec, 62622462 t fired, . Pages in use: 12 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCflexbar-PT-2a-CTLFireability-02 2991703 m, 32660 m/sec, 66255263 t fired, . Pages in use: 13 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCflexbar-PT-2a-CTLFireability-02 3155623 m, 32784 m/sec, 69906237 t fired, . Pages in use: 13 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCflexbar-PT-2a-CTLFireability-02 3318633 m, 32602 m/sec, 73542916 t fired, . Pages in use: 14 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 DLCflexbar-PT-2a-CTLFireability-02 3490201 m, 34313 m/sec, 77325077 t fired, . Pages in use: 15 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 DLCflexbar-PT-2a-CTLFireability-02 3658563 m, 33672 m/sec, 81071570 t fired, . Pages in use: 16 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 DLCflexbar-PT-2a-CTLFireability-02 3824563 m, 33200 m/sec, 84770038 t fired, . Pages in use: 16 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 DLCflexbar-PT-2a-CTLFireability-02 3992185 m, 33524 m/sec, 88542339 t fired, . Pages in use: 17 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 DLCflexbar-PT-2a-CTLFireability-02 4160454 m, 33653 m/sec, 92298880 t fired, . Pages in use: 18 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 DLCflexbar-PT-2a-CTLFireability-02 4320864 m, 32082 m/sec, 95905061 t fired, . Pages in use: 18 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 DLCflexbar-PT-2a-CTLFireability-02 4484106 m, 32648 m/sec, 99575129 t fired, . Pages in use: 19 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 DLCflexbar-PT-2a-CTLFireability-02 4642518 m, 31682 m/sec, 103183168 t fired, . Pages in use: 20 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 DLCflexbar-PT-2a-CTLFireability-02 4804738 m, 32444 m/sec, 106823543 t fired, . Pages in use: 20 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 DLCflexbar-PT-2a-CTLFireability-02 4965331 m, 32118 m/sec, 110442902 t fired, . Pages in use: 21 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 DLCflexbar-PT-2a-CTLFireability-02 5122272 m, 31388 m/sec, 113986278 t fired, . Pages in use: 22 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 DLCflexbar-PT-2a-CTLFireability-02 5287908 m, 33127 m/sec, 117697896 t fired, . Pages in use: 22 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 DLCflexbar-PT-2a-CTLFireability-02 5448243 m, 32067 m/sec, 121301679 t fired, . Pages in use: 23 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 DLCflexbar-PT-2a-CTLFireability-02 5606748 m, 31701 m/sec, 124888326 t fired, . Pages in use: 24 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 DLCflexbar-PT-2a-CTLFireability-02 5773291 m, 33308 m/sec, 128601469 t fired, . Pages in use: 24 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 DLCflexbar-PT-2a-CTLFireability-02 5932578 m, 31857 m/sec, 132204505 t fired, . Pages in use: 25 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 DLCflexbar-PT-2a-CTLFireability-02 6097281 m, 32940 m/sec, 135891707 t fired, . Pages in use: 26 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 DLCflexbar-PT-2a-CTLFireability-02 6265800 m, 33703 m/sec, 139607552 t fired, . Pages in use: 26 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 DLCflexbar-PT-2a-CTLFireability-02 6433721 m, 33584 m/sec, 143293434 t fired, . Pages in use: 27 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 DLCflexbar-PT-2a-CTLFireability-02 6600333 m, 33322 m/sec, 146966569 t fired, . Pages in use: 28 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 DLCflexbar-PT-2a-CTLFireability-02 6766792 m, 33291 m/sec, 150664380 t fired, . Pages in use: 28 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 DLCflexbar-PT-2a-CTLFireability-02 6935355 m, 33712 m/sec, 154373086 t fired, . Pages in use: 29 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 DLCflexbar-PT-2a-CTLFireability-02 7098963 m, 32721 m/sec, 158036981 t fired, . Pages in use: 30 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 DLCflexbar-PT-2a-CTLFireability-02 7265659 m, 33339 m/sec, 161720228 t fired, . Pages in use: 30 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 DLCflexbar-PT-2a-CTLFireability-02 7436810 m, 34230 m/sec, 165501794 t fired, . Pages in use: 31 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 DLCflexbar-PT-2a-CTLFireability-02 7605444 m, 33726 m/sec, 169276361 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 DLCflexbar-PT-2a-CTLFireability-02 7761594 m, 31230 m/sec, 172835976 t fired, . Pages in use: 32 (type EXCL) for DLCflexbar-PT-2a-CTLFireability-02 (memory limit exceeded) VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 EXCL) for 49 DLCflexbar-PT-2a-CTLFireability-15 (type EXCL) for DLCflexbar-PT-2a-CTLFireability-15 5 5 0.000000 1 EXCL) for 46 DLCflexbar-PT-2a-CTLFireability-14 (type EXCL) for DLCflexbar-PT-2a-CTLFireability-14 0.000000 1 EXCL) for 43 DLCflexbar-PT-2a-CTLFireability-13 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCflexbar-PT-2a-CTLFireability-13 394085 m, 78817 m/sec, 7374548 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCflexbar-PT-2a-CTLFireability-13 808738 m, 82930 m/sec, 14243079 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCflexbar-PT-2a-CTLFireability-13 1224913 m, 83235 m/sec, 21156352 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCflexbar-PT-2a-CTLFireability-13 1670605 m, 89138 m/sec, 27838481 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCflexbar-PT-2a-CTLFireability-13 2069778 m, 79834 m/sec, 34763538 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCflexbar-PT-2a-CTLFireability-13 2462536 m, 78551 m/sec, 41489537 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 DLCflexbar-PT-2a-CTLFireability-13 2854175 m, 78327 m/sec, 48301022 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCflexbar-PT-2a-CTLFireability-13 3275100 m, 84185 m/sec, 54867711 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 DLCflexbar-PT-2a-CTLFireability-13 3710653 m, 87110 m/sec, 61352032 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 DLCflexbar-PT-2a-CTLFireability-13 4160337 m, 89936 m/sec, 67780648 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 DLCflexbar-PT-2a-CTLFireability-13 4617475 m, 91427 m/sec, 74261038 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 DLCflexbar-PT-2a-CTLFireability-13 4991358 m, 74776 m/sec, 81341082 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 DLCflexbar-PT-2a-CTLFireability-13 5394157 m, 80559 m/sec, 88067540 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 DLCflexbar-PT-2a-CTLFireability-13 5787106 m, 78589 m/sec, 94931056 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 DLCflexbar-PT-2a-CTLFireability-13 6233758 m, 89330 m/sec, 101446356 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 DLCflexbar-PT-2a-CTLFireability-13 6674604 m, 88169 m/sec, 107892406 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 DLCflexbar-PT-2a-CTLFireability-13 7103098 m, 85698 m/sec, 114508760 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 DLCflexbar-PT-2a-CTLFireability-13 7488287 m, 77037 m/sec, 121412107 t fired, . Pages in use: 32 (type EXCL) for DLCflexbar-PT-2a-CTLFireability-13 (memory limit exceeded) VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS Pages in use: 32 EXCL) for 40 DLCflexbar-PT-2a-CTLFireability-12 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCflexbar-PT-2a-CTLFireability-12 57758 m, 11551 m/sec, 1645037 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCflexbar-PT-2a-CTLFireability-12 114457 m, 11339 m/sec, 3264648 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCflexbar-PT-2a-CTLFireability-12 170519 m, 11212 m/sec, 4861856 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 DLCflexbar-PT-2a-CTLFireability-12 226041 m, 11104 m/sec, 6439270 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCflexbar-PT-2a-CTLFireability-12 281191 m, 11030 m/sec, 8022366 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCflexbar-PT-2a-CTLFireability-12 336238 m, 11009 m/sec, 9605726 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCflexbar-PT-2a-CTLFireability-12 391381 m, 11028 m/sec, 11184186 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 DLCflexbar-PT-2a-CTLFireability-12 446085 m, 10940 m/sec, 12772012 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCflexbar-PT-2a-CTLFireability-12 500576 m, 10898 m/sec, 14353478 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCflexbar-PT-2a-CTLFireability-12 554651 m, 10815 m/sec, 15928656 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCflexbar-PT-2a-CTLFireability-12 608931 m, 10856 m/sec, 17514161 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCflexbar-PT-2a-CTLFireability-12 663251 m, 10864 m/sec, 19097933 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 DLCflexbar-PT-2a-CTLFireability-12 717321 m, 10814 m/sec, 20676732 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCflexbar-PT-2a-CTLFireability-12 772411 m, 11018 m/sec, 22258941 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCflexbar-PT-2a-CTLFireability-12 828755 m, 11268 m/sec, 23860659 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCflexbar-PT-2a-CTLFireability-12 884681 m, 11185 m/sec, 25451629 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 DLCflexbar-PT-2a-CTLFireability-12 940430 m, 11149 m/sec, 27038618 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCflexbar-PT-2a-CTLFireability-12 996359 m, 11185 m/sec, 28625822 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCflexbar-PT-2a-CTLFireability-12 1051332 m, 10994 m/sec, 30186713 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCflexbar-PT-2a-CTLFireability-12 1106092 m, 10952 m/sec, 31746606 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 DLCflexbar-PT-2a-CTLFireability-12 1159878 m, 10757 m/sec, 33286380 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCflexbar-PT-2a-CTLFireability-12 1213633 m, 10751 m/sec, 34836927 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCflexbar-PT-2a-CTLFireability-12 1267533 m, 10780 m/sec, 36386738 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCflexbar-PT-2a-CTLFireability-12 1321997 m, 10892 m/sec, 37941856 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCflexbar-PT-2a-CTLFireability-12 1376018 m, 10804 m/sec, 39491409 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 DLCflexbar-PT-2a-CTLFireability-12 1430027 m, 10801 m/sec, 41051905 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCflexbar-PT-2a-CTLFireability-12 1483617 m, 10718 m/sec, 42606575 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCflexbar-PT-2a-CTLFireability-12 1537366 m, 10749 m/sec, 44159707 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCflexbar-PT-2a-CTLFireability-12 1590687 m, 10664 m/sec, 45708652 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 DLCflexbar-PT-2a-CTLFireability-12 1644129 m, 10688 m/sec, 47265745 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCflexbar-PT-2a-CTLFireability-12 1697473 m, 10668 m/sec, 48827705 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCflexbar-PT-2a-CTLFireability-12 1750678 m, 10641 m/sec, 50384380 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCflexbar-PT-2a-CTLFireability-12 1805298 m, 10924 m/sec, 51955640 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCflexbar-PT-2a-CTLFireability-12 1860337 m, 11007 m/sec, 53531064 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 DLCflexbar-PT-2a-CTLFireability-12 1914751 m, 10882 m/sec, 55109710 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCflexbar-PT-2a-CTLFireability-12 1968769 m, 10803 m/sec, 56694726 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCflexbar-PT-2a-CTLFireability-12 2022900 m, 10826 m/sec, 58288599 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCflexbar-PT-2a-CTLFireability-12 2077244 m, 10868 m/sec, 59873323 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 DLCflexbar-PT-2a-CTLFireability-12 2132937 m, 11138 m/sec, 61457616 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCflexbar-PT-2a-CTLFireability-12 2189284 m, 11269 m/sec, 63058698 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCflexbar-PT-2a-CTLFireability-12 2245147 m, 11172 m/sec, 64644958 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCflexbar-PT-2a-CTLFireability-12 2300600 m, 11090 m/sec, 66220887 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 DLCflexbar-PT-2a-CTLFireability-12 2355064 m, 10892 m/sec, 67770180 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCflexbar-PT-2a-CTLFireability-12 2409982 m, 10983 m/sec, 69339461 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCflexbar-PT-2a-CTLFireability-12 2464747 m, 10953 m/sec, 70906131 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCflexbar-PT-2a-CTLFireability-12 2518984 m, 10847 m/sec, 72467812 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCflexbar-PT-2a-CTLFireability-12 2573141 m, 10831 m/sec, 74025723 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 DLCflexbar-PT-2a-CTLFireability-12 2626918 m, 10755 m/sec, 75569406 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 DLCflexbar-PT-2a-CTLFireability-12 2681639 m, 10944 m/sec, 77147511 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 DLCflexbar-PT-2a-CTLFireability-12 2737383 m, 11148 m/sec, 78735249 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 DLCflexbar-PT-2a-CTLFireability-12 2792560 m, 11035 m/sec, 80303962 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 DLCflexbar-PT-2a-CTLFireability-12 2846890 m, 10866 m/sec, 81844605 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCflexbar-PT-2a-CTLFireability-12 2900187 m, 10659 m/sec, 83357965 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCflexbar-PT-2a-CTLFireability-12 2953473 m, 10657 m/sec, 84874095 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCflexbar-PT-2a-CTLFireability-12 3006760 m, 10657 m/sec, 86400539 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCflexbar-PT-2a-CTLFireability-12 3060225 m, 10693 m/sec, 87936063 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 DLCflexbar-PT-2a-CTLFireability-12 3113110 m, 10577 m/sec, 89457385 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCflexbar-PT-2a-CTLFireability-12 3165924 m, 10562 m/sec, 90975415 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCflexbar-PT-2a-CTLFireability-12 3219727 m, 10760 m/sec, 92505895 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCflexbar-PT-2a-CTLFireability-12 3274053 m, 10865 m/sec, 94050590 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 DLCflexbar-PT-2a-CTLFireability-12 3327452 m, 10679 m/sec, 95587039 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 DLCflexbar-PT-2a-CTLFireability-12 3380145 m, 10538 m/sec, 97111316 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 DLCflexbar-PT-2a-CTLFireability-12 3433458 m, 10662 m/sec, 98655750 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 DLCflexbar-PT-2a-CTLFireability-12 3486107 m, 10529 m/sec, 100186712 t fired, . Pages in use: 32 VALUE PRODUCED BY EFEG true state space /EFEG DISJ true CTL model checker CTL true CTL model checker CTL true CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AGEF 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 DLCflexbar-PT-2a-CTLFireability-12 3538274 m, 10433 m/sec, 101710105 t fired, . Pages in use: 32 //../BenchKit_head.sh: line 63: 376 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DLCflexbar-PT-2a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DLCflexbar-PT-2a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814477000506"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DLCflexbar-PT-2a.tgz
mv DLCflexbar-PT-2a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;