About the Execution of LoLA for DES-PT-40b
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
3820.275 | 416070.00 | 1128436.00 | 1091.60 | TF?TFT??TFFFT??T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r102-tall-167814476900466.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DES-PT-40b, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814476900466
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 484K
-rw-r--r-- 1 mcc users 5.8K Feb 26 15:36 CTLCardinality.txt
-rw-r--r-- 1 mcc users 62K Feb 26 15:36 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 15:36 CTLFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 26 15:36 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:51 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:51 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:51 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:51 LTLFireability.xml
-rw-r--r-- 1 mcc users 6.8K Feb 26 15:37 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 26 15:37 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 26 15:37 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 26 15:37 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 15:51 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:51 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 115K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME DES-PT-40b-CTLFireability-00
FORMULA_NAME DES-PT-40b-CTLFireability-01
FORMULA_NAME DES-PT-40b-CTLFireability-02
FORMULA_NAME DES-PT-40b-CTLFireability-03
FORMULA_NAME DES-PT-40b-CTLFireability-04
FORMULA_NAME DES-PT-40b-CTLFireability-05
FORMULA_NAME DES-PT-40b-CTLFireability-06
FORMULA_NAME DES-PT-40b-CTLFireability-07
FORMULA_NAME DES-PT-40b-CTLFireability-08
FORMULA_NAME DES-PT-40b-CTLFireability-09
FORMULA_NAME DES-PT-40b-CTLFireability-10
FORMULA_NAME DES-PT-40b-CTLFireability-11
FORMULA_NAME DES-PT-40b-CTLFireability-12
FORMULA_NAME DES-PT-40b-CTLFireability-13
FORMULA_NAME DES-PT-40b-CTLFireability-14
FORMULA_NAME DES-PT-40b-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678288196000
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DES-PT-40b
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DES-PT-40b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability
FORMULA DES-PT-40b-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA DES-PT-40b-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678288612070
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 10 (type EXCL) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 73 (type FNDP) for 28 DES-PT-40b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type EQUN) for 28 DES-PT-40b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type SRCH) for 28 DES-PT-40b-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 76 (type SRCH) for DES-PT-40b-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
sara: try reading problem file /home/mcc/execution/CTLFireability-74.sara.
lola: FINISHED task # 73 (type FNDP) for DES-PT-40b-CTLFireability-04
lola: result : true
lola: fired transitions : 70
lola: tried executions : 4
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 74 (type EQUN) for DES-PT-40b-CTLFireability-04 (obsolete)
lola: FINISHED task # 74 (type EQUN) for DES-PT-40b-CTLFireability-04
lola: result : unknown
lola: FINISHED task # 10 (type EXCL) for DES-PT-40b-CTLFireability-01
lola: result : true
lola: markings : 24139
lola: fired transitions : 81754
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 6 (type EXCL) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: FINISHED task # 6 (type EXCL) for DES-PT-40b-CTLFireability-01
lola: result : false
lola: markings : 24
lola: fired transitions : 48
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 79 (type EXCL) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 80 (type FNDP) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type EQUN) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SRCH) for 3 DES-PT-40b-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/CTLFireability-81.sara.
lola: FINISHED task # 83 (type SRCH) for DES-PT-40b-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 84 (type FNDP) for 44 DES-PT-40b-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 79 (type EXCL) for DES-PT-40b-CTLFireability-01
lola: result : true
lola: markings : 14
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 80 (type FNDP) for DES-PT-40b-CTLFireability-01 (obsolete)
lola: CANCELED task # 81 (type EQUN) for DES-PT-40b-CTLFireability-01 (obsolete)
lola: LAUNCH task # 51 (type EXCL) for 50 DES-PT-40b-CTLFireability-10
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 85 (type EQUN) for 44 DES-PT-40b-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 87 (type SRCH) for 44 DES-PT-40b-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 80 (type FNDP) for DES-PT-40b-CTLFireability-01
lola: result : true
lola: fired transitions : 4
lola: tried executions : 1
lola: Created skeleton in 0.000000 secs.
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 84 (type FNDP) for DES-PT-40b-CTLFireability-08
lola: result : true
lola: fired transitions : 13
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: CANCELED task # 85 (type EQUN) for DES-PT-40b-CTLFireability-08 (obsolete)
lola: CANCELED task # 87 (type SRCH) for DES-PT-40b-CTLFireability-08 (obsolete)
lola: FINISHED task # 81 (type EQUN) for DES-PT-40b-CTLFireability-01
lola: result : unknown
lola: FINISHED task # 87 (type SRCH) for DES-PT-40b-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 51 (type EXCL) for DES-PT-40b-CTLFireability-10
lola: result : false
lola: markings : 85
lola: fired transitions : 173
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 DES-PT-40b-CTLFireability-09
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 48 (type EXCL) for DES-PT-40b-CTLFireability-09
lola: result : false
lola: markings : 85
lola: fired transitions : 88
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-85.sara.
lola: LAUNCH task # 42 (type EXCL) for 37 DES-PT-40b-CTLFireability-07
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:756
lola: rewrite Frontend/Parser/formula_rewrite.k:691
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 89 (type FNDP) for 60 DES-PT-40b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type EQUN) for 60 DES-PT-40b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 92 (type SRCH) for 60 DES-PT-40b-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 92 (type SRCH) for DES-PT-40b-CTLFireability-12
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 85 (type EQUN) for DES-PT-40b-CTLFireability-08
lola: result : true
sara: try reading problem file /home/mcc/execution/CTLFireability-90.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-08: EF true findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-10: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 4/276 3/32 DES-PT-40b-CTLFireability-07 520704 m, 104140 m/sec, 3338646 t fired, .
89 EF FNDP 4/3599 0/5 DES-PT-40b-CTLFireability-12 6077098 t fired, 243444 attempts, .
90 EF STEQ 4/3599 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 5 secs. Pages in use: 3
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-08: EF true findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-10: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 9/276 5/32 DES-PT-40b-CTLFireability-07 1025436 m, 100946 m/sec, 6951228 t fired, .
89 EF FNDP 9/3599 0/5 DES-PT-40b-CTLFireability-12 12663129 t fired, 510119 attempts, .
90 EF STEQ 9/3599 0/5 DES-PT-40b-CTLFireability-12 sara is running.
Time elapsed: 10 secs. Pages in use: 5
# running tasks: 3 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-40b-CTLFireability-01: DISJ false DISJ
DES-PT-40b-CTLFireability-04: AG false findpath
DES-PT-40b-CTLFireability-08: EF true findpath
DES-PT-40b-CTLFireability-09: CTL false CTL model checker
DES-PT-40b-CTLFireability-10: CTL false CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-40b-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 14/276 7/32 DES-PT-40b-CTLFireability-07 1508516 m, 96616 m/sec, 10569666 t fired, .
89 EF FNDP 14/3599 0/5 DES-PT-40b-CTLFireability-12 19194905 t fired, 775107 attempts, .
90 EF STEQ 14/3599 0/5 DES-PT-40b-CTLFireability-12 sara is running.
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DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 19/276 9/32 DES-PT-40b-CTLFireability-07 1987431 m, 95783 m/sec, 14182830 t fired, .
89 EF FNDP 19/3599 0/5 DES-PT-40b-CTLFireability-12 25754535 t fired, 1041510 attempts, .
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DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 24/276 12/32 DES-PT-40b-CTLFireability-07 2495634 m, 101640 m/sec, 17763953 t fired, .
89 EF FNDP 24/3599 0/5 DES-PT-40b-CTLFireability-12 32274064 t fired, 1306302 attempts, .
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DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 29/276 14/32 DES-PT-40b-CTLFireability-07 2952629 m, 91399 m/sec, 21333938 t fired, .
89 EF FNDP 29/3599 0/5 DES-PT-40b-CTLFireability-12 38843353 t fired, 1573767 attempts, .
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DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 34/276 16/32 DES-PT-40b-CTLFireability-07 3428974 m, 95269 m/sec, 24894872 t fired, .
89 EF FNDP 34/3599 0/5 DES-PT-40b-CTLFireability-12 45392306 t fired, 1840917 attempts, .
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DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 39/276 18/32 DES-PT-40b-CTLFireability-07 3910963 m, 96397 m/sec, 28455568 t fired, .
89 EF FNDP 39/3599 0/5 DES-PT-40b-CTLFireability-12 51933403 t fired, 2107119 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 44/276 20/32 DES-PT-40b-CTLFireability-07 4362878 m, 90383 m/sec, 31992379 t fired, .
89 EF FNDP 44/3599 0/5 DES-PT-40b-CTLFireability-12 58474560 t fired, 2374170 attempts, .
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DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 49/276 22/32 DES-PT-40b-CTLFireability-07 4769660 m, 81356 m/sec, 35525240 t fired, .
89 EF FNDP 49/3599 0/5 DES-PT-40b-CTLFireability-12 65015917 t fired, 2639959 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 54/276 24/32 DES-PT-40b-CTLFireability-07 5285951 m, 103258 m/sec, 39100520 t fired, .
89 EF FNDP 54/3599 0/5 DES-PT-40b-CTLFireability-12 71562145 t fired, 2906265 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 59/276 26/32 DES-PT-40b-CTLFireability-07 5748107 m, 92431 m/sec, 42650994 t fired, .
89 EF FNDP 59/3599 0/5 DES-PT-40b-CTLFireability-12 78107615 t fired, 3172604 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 64/276 29/32 DES-PT-40b-CTLFireability-07 6218117 m, 94002 m/sec, 46187315 t fired, .
89 EF FNDP 64/3599 0/5 DES-PT-40b-CTLFireability-12 84657002 t fired, 3439629 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 1 0 2 0 0 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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42 CTL EXCL 69/276 31/32 DES-PT-40b-CTLFireability-07 6676739 m, 91724 m/sec, 49691797 t fired, .
89 EF FNDP 69/3599 0/5 DES-PT-40b-CTLFireability-12 91207678 t fired, 3706191 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 2 0 0 2 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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89 EF FNDP 74/3599 0/5 DES-PT-40b-CTLFireability-12 97755835 t fired, 3972733 attempts, .
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DES-PT-40b-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
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70 CTL EXCL 5/320 4/32 DES-PT-40b-CTLFireability-15 803059 m, 160611 m/sec, 3599171 t fired, .
89 EF FNDP 79/3599 0/5 DES-PT-40b-CTLFireability-12 104293492 t fired, 4238310 attempts, .
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lola: FINISHED task # 70 (type EXCL) for DES-PT-40b-CTLFireability-15
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DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 1/351 1/32 DES-PT-40b-CTLFireability-14 86575 m, 17315 m/sec, 806406 t fired, .
89 EF FNDP 84/3599 0/5 DES-PT-40b-CTLFireability-12 110846023 t fired, 4505325 attempts, .
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DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 6/351 2/32 DES-PT-40b-CTLFireability-14 419304 m, 66545 m/sec, 4499186 t fired, .
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67 CTL EXCL 11/351 4/32 DES-PT-40b-CTLFireability-14 741200 m, 64379 m/sec, 8161099 t fired, .
89 EF FNDP 94/3599 0/5 DES-PT-40b-CTLFireability-12 123958487 t fired, 5038698 attempts, .
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DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 16/351 5/32 DES-PT-40b-CTLFireability-14 1025190 m, 56798 m/sec, 11844207 t fired, .
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67 CTL EXCL 21/351 6/32 DES-PT-40b-CTLFireability-14 1307917 m, 56545 m/sec, 15553955 t fired, .
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67 CTL EXCL 26/351 8/32 DES-PT-40b-CTLFireability-14 1595173 m, 57451 m/sec, 19247292 t fired, .
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67 CTL EXCL 31/351 9/32 DES-PT-40b-CTLFireability-14 1878821 m, 56729 m/sec, 22960141 t fired, .
89 EF FNDP 114/3599 0/5 DES-PT-40b-CTLFireability-12 150429942 t fired, 6117067 attempts, .
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67 CTL EXCL 36/351 10/32 DES-PT-40b-CTLFireability-14 2170739 m, 58383 m/sec, 26677003 t fired, .
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67 CTL EXCL 41/351 12/32 DES-PT-40b-CTLFireability-14 2482214 m, 62295 m/sec, 30371174 t fired, .
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67 CTL EXCL 46/351 13/32 DES-PT-40b-CTLFireability-14 2753991 m, 54355 m/sec, 34073231 t fired, .
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67 CTL EXCL 51/351 14/32 DES-PT-40b-CTLFireability-14 3024707 m, 54143 m/sec, 37752309 t fired, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
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67 CTL EXCL 66/351 18/32 DES-PT-40b-CTLFireability-14 3888049 m, 54926 m/sec, 48772443 t fired, .
89 EF FNDP 149/3599 0/5 DES-PT-40b-CTLFireability-12 197295165 t fired, 8024391 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 71/351 19/32 DES-PT-40b-CTLFireability-14 4157075 m, 53805 m/sec, 52428482 t fired, .
89 EF FNDP 154/3599 0/5 DES-PT-40b-CTLFireability-12 204009323 t fired, 8297796 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
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67 CTL EXCL 76/351 20/32 DES-PT-40b-CTLFireability-14 4418229 m, 52230 m/sec, 56055555 t fired, .
89 EF FNDP 159/3599 0/5 DES-PT-40b-CTLFireability-12 210698762 t fired, 8570168 attempts, .
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DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 81/351 21/32 DES-PT-40b-CTLFireability-14 4636558 m, 43665 m/sec, 59649556 t fired, .
89 EF FNDP 164/3599 0/5 DES-PT-40b-CTLFireability-12 217380282 t fired, 8842676 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 91/351 24/32 DES-PT-40b-CTLFireability-14 5243178 m, 62588 m/sec, 67050375 t fired, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 96/351 25/32 DES-PT-40b-CTLFireability-14 5516298 m, 54624 m/sec, 70724894 t fired, .
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DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-11: DISJ 0 1 0 0 3 0 0 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 101/351 27/32 DES-PT-40b-CTLFireability-14 5789909 m, 54722 m/sec, 74362477 t fired, .
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DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 106/351 28/32 DES-PT-40b-CTLFireability-14 6058572 m, 53732 m/sec, 78007725 t fired, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 111/351 29/32 DES-PT-40b-CTLFireability-14 6359498 m, 60185 m/sec, 81647116 t fired, .
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DES-PT-40b-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
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DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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67 CTL EXCL 116/351 30/32 DES-PT-40b-CTLFireability-14 6617311 m, 51562 m/sec, 85247038 t fired, .
89 EF FNDP 199/3599 0/5 DES-PT-40b-CTLFireability-12 264268320 t fired, 10751221 attempts, .
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DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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67 CTL EXCL 121/351 32/32 DES-PT-40b-CTLFireability-14 6874915 m, 51520 m/sec, 88818658 t fired, .
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DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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89 EF FNDP 209/3599 0/5 DES-PT-40b-CTLFireability-12 277701108 t fired, 11299061 attempts, .
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35 CTL EXCL 5/423 3/32 DES-PT-40b-CTLFireability-06 492304 m, 98460 m/sec, 3487949 t fired, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 75/423 29/32 DES-PT-40b-CTLFireability-06 6304010 m, 83271 m/sec, 51208354 t fired, .
89 EF FNDP 284/3599 0/5 DES-PT-40b-CTLFireability-12 378155906 t fired, 15391238 attempts, .
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DES-PT-40b-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 80/423 31/32 DES-PT-40b-CTLFireability-06 6696912 m, 78580 m/sec, 54550793 t fired, .
89 EF FNDP 289/3599 0/5 DES-PT-40b-CTLFireability-12 384850276 t fired, 15663481 attempts, .
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DES-PT-40b-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
89 EF FNDP 294/3599 0/5 DES-PT-40b-CTLFireability-12 391558561 t fired, 15937038 attempts, .
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DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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23 CTL EXCL 4/660 5/32 DES-PT-40b-CTLFireability-02 842936 m, 168587 m/sec, 3009462 t fired, .
89 EF FNDP 299/3599 0/5 DES-PT-40b-CTLFireability-12 398310034 t fired, 16211745 attempts, .
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DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-40b-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
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23 CTL EXCL 9/660 9/32 DES-PT-40b-CTLFireability-02 1765056 m, 184424 m/sec, 6753865 t fired, .
89 EF FNDP 304/3599 0/5 DES-PT-40b-CTLFireability-12 404996427 t fired, 16484293 attempts, .
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DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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23 CTL EXCL 14/660 14/32 DES-PT-40b-CTLFireability-02 2737885 m, 194565 m/sec, 10505708 t fired, .
89 EF FNDP 309/3599 0/5 DES-PT-40b-CTLFireability-12 411684584 t fired, 16757116 attempts, .
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DES-PT-40b-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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23 CTL EXCL 19/660 18/32 DES-PT-40b-CTLFireability-02 3630024 m, 178427 m/sec, 14195720 t fired, .
89 EF FNDP 314/3599 0/5 DES-PT-40b-CTLFireability-12 418377901 t fired, 17030485 attempts, .
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DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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23 CTL EXCL 24/660 23/32 DES-PT-40b-CTLFireability-02 4606259 m, 195247 m/sec, 17928909 t fired, .
89 EF FNDP 319/3599 0/5 DES-PT-40b-CTLFireability-12 425066542 t fired, 17303226 attempts, .
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DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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89 EF FNDP 324/3599 0/5 DES-PT-40b-CTLFireability-12 431752050 t fired, 17574750 attempts, .
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DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
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DES-PT-40b-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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23 CTL EXCL 34/660 31/32 DES-PT-40b-CTLFireability-02 6228712 m, 151237 m/sec, 25216925 t fired, .
89 EF FNDP 329/3599 0/5 DES-PT-40b-CTLFireability-12 438444700 t fired, 17847849 attempts, .
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DES-PT-40b-CTLFireability-07: CONJ 0 1 0 0 2 0 1 0
DES-PT-40b-CTLFireability-12: EF 0 1 2 0 2 0 0 0
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89 EF FNDP 334/3599 0/5 DES-PT-40b-CTLFireability-12 445317132 t fired, 18127318 attempts, .
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1 CTL EXCL 5/816 3/32 DES-PT-40b-CTLFireability-00 524029 m, 104805 m/sec, 3778743 t fired, .
89 EF FNDP 339/3599 0/5 DES-PT-40b-CTLFireability-12 452000998 t fired, 18399812 attempts, .
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1 CTL EXCL 15/816 8/32 DES-PT-40b-CTLFireability-00 1532261 m, 100513 m/sec, 11422125 t fired, .
89 EF FNDP 349/3599 0/5 DES-PT-40b-CTLFireability-12 465360986 t fired, 18943652 attempts, .
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89 EF FNDP 354/3599 0/5 DES-PT-40b-CTLFireability-12 472050427 t fired, 19216676 attempts, .
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lola: FINISHED task # 1 (type EXCL) for DES-PT-40b-CTLFireability-00
lola: result : true
lola: markings : 2286110
lola: fired transitions : 17000047
lola: time used : 23.000000
lola: memory pages used : 12
lola: LAUNCH task # 91 (type EXCL) for 60 DES-PT-40b-CTLFireability-12
lola: time limit : 1080 sec
lola: memory limit: 32 pages
lola: FINISHED task # 91 (type EXCL) for DES-PT-40b-CTLFireability-12
lola: result : true
lola: markings : 14501
lola: fired transitions : 18197
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 89 (type FNDP) for DES-PT-40b-CTLFireability-12 (obsolete)
lola: CANCELED task # 90 (type EQUN) for DES-PT-40b-CTLFireability-12 (obsolete)
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lola: FINISHED task # 89 (type FNDP) for DES-PT-40b-CTLFireability-12
lola: result : unknown
lola: fired transitions : 475216064
lola: tried executions : 19345939
lola: time used : 357.000000
lola: memory pages used : 0
lola: FINISHED task # 90 (type EQUN) for DES-PT-40b-CTLFireability-12
lola: result : unknown
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lola: result : true
lola: markings : 23
lola: fired transitions : 45
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 64 (type EXCL) for 63 DES-PT-40b-CTLFireability-13
lola: time limit : 3242 sec
lola: memory limit: 32 pages
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FINAL RESULTS
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DES-PT-40b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DES-PT-40b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814476900466"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/DES-PT-40b.tgz
mv DES-PT-40b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;