Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r102-tall-167814476800410.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is DES-PT-10a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r102-tall-167814476800410
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 7.8K Feb 26 15:47 CTLCardinality.txt
-rw-r--r-- 1 mcc users 91K Feb 26 15:47 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.8K Feb 26 15:46 CTLFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 15:46 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Feb 25 15:50 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:50 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K Feb 25 15:50 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:50 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 15:50 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 117K Feb 26 15:50 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.8K Feb 26 15:49 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 92K Feb 26 15:49 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.5K Feb 25 15:50 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:50 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 43K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME DES-PT-10a-CTLFireability-00
FORMULA_NAME DES-PT-10a-CTLFireability-01
FORMULA_NAME DES-PT-10a-CTLFireability-02
FORMULA_NAME DES-PT-10a-CTLFireability-03
FORMULA_NAME DES-PT-10a-CTLFireability-04
FORMULA_NAME DES-PT-10a-CTLFireability-05
FORMULA_NAME DES-PT-10a-CTLFireability-06
FORMULA_NAME DES-PT-10a-CTLFireability-07
FORMULA_NAME DES-PT-10a-CTLFireability-08
FORMULA_NAME DES-PT-10a-CTLFireability-09
FORMULA_NAME DES-PT-10a-CTLFireability-10
FORMULA_NAME DES-PT-10a-CTLFireability-11
FORMULA_NAME DES-PT-10a-CTLFireability-12
FORMULA_NAME DES-PT-10a-CTLFireability-13
FORMULA_NAME DES-PT-10a-CTLFireability-14
FORMULA_NAME DES-PT-10a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678280672936

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=DES-PT-10a
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT DES-PT-10a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA DES-PT-10a-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA DES-PT-10a-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678280885132

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 8 (type EXCL) for 7 DES-PT-10a-CTLFireability-01
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
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DES-PT-10a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 5/199 5/32 DES-PT-10a-CTLFireability-01 1074119 m, 214823 m/sec, 8525363 t fired, .

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DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DES-PT-10a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 10/199 10/32 DES-PT-10a-CTLFireability-01 2137906 m, 212757 m/sec, 17032572 t fired, .

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DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DES-PT-10a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 15/199 14/32 DES-PT-10a-CTLFireability-01 3114490 m, 195316 m/sec, 25262710 t fired, .

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DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DES-PT-10a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 20/199 18/32 DES-PT-10a-CTLFireability-01 3996799 m, 176461 m/sec, 33326449 t fired, .

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DES-PT-10a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 25/199 22/32 DES-PT-10a-CTLFireability-01 4887537 m, 178147 m/sec, 41121619 t fired, .

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DES-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 30/199 26/32 DES-PT-10a-CTLFireability-01 5812799 m, 185052 m/sec, 49099764 t fired, .

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DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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DES-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-15: DISJ 0 2 0 0 2 0 0 0

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8 CTL EXCL 35/199 30/32 DES-PT-10a-CTLFireability-01 6813585 m, 200157 m/sec, 57178427 t fired, .

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DES-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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DES-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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DES-PT-10a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 5/222 6/32 DES-PT-10a-CTLFireability-15 1320285 m, 264057 m/sec, 8591304 t fired, .

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DES-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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41 CTL EXCL 4/253 3/32 DES-PT-10a-CTLFireability-12 620760 m, 124152 m/sec, 2650880 t fired, .

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DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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DES-PT-10a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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41 CTL EXCL 9/253 7/32 DES-PT-10a-CTLFireability-12 1407112 m, 157270 m/sec, 6478049 t fired, .

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DES-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
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41 CTL EXCL 14/253 10/32 DES-PT-10a-CTLFireability-12 2261980 m, 170973 m/sec, 12709535 t fired, .

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41 CTL EXCL 19/253 14/32 DES-PT-10a-CTLFireability-12 3121920 m, 171988 m/sec, 17212709 t fired, .

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41 CTL EXCL 24/253 18/32 DES-PT-10a-CTLFireability-12 3944076 m, 164431 m/sec, 21655171 t fired, .

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20 CTL EXCL 5/433 5/32 DES-PT-10a-CTLFireability-05 1125301 m, 225060 m/sec, 8944927 t fired, .

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20 CTL EXCL 10/433 10/32 DES-PT-10a-CTLFireability-05 2153607 m, 205661 m/sec, 17718561 t fired, .

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20 CTL EXCL 15/433 14/32 DES-PT-10a-CTLFireability-05 3110573 m, 191393 m/sec, 26156005 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
DES-PT-10a-CTLFireability-00: DISJ 0 2 0 0 2 0 0 0
DES-PT-10a-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
DES-PT-10a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
DES-PT-10a-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
DES-PT-10a-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
DES-PT-10a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
DES-PT-10a-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
DES-PT-10a-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
DES-PT-10a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/566 9/32 DES-PT-10a-CTLFireability-03 1854362 m, 166239 m/sec, 18089893 t fired, .

Time elapsed: 211 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 14 (type EXCL) for DES-PT-10a-CTLFireability-03
lola: result : true
lola: markings : 2455674
lola: fired transitions : 20906090
lola: time used : 11.000000
lola: memory pages used : 11
lola: LAUNCH task # 11 (type EXCL) for 10 DES-PT-10a-CTLFireability-02
lola: time limit : 677 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for DES-PT-10a-CTLFireability-02
lola: result : false
lola: markings : 8801
lola: fired transitions : 39051
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 5 (type EXCL) for 0 DES-PT-10a-CTLFireability-00
lola: time limit : 847 sec
lola: memory limit: 32 pages
lola: FINISHED task # 5 (type EXCL) for DES-PT-10a-CTLFireability-00
lola: result : true
lola: markings : 660
lola: fired transitions : 5331
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 DES-PT-10a-CTLFireability-13
lola: time limit : 1693 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for DES-PT-10a-CTLFireability-13
lola: result : true
lola: markings : 46
lola: fired transitions : 45
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 DES-PT-10a-CTLFireability-06
lola: time limit : 3387 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for DES-PT-10a-CTLFireability-06
lola: result : false
lola: markings : 46
lola: fired transitions : 138
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
DES-PT-10a-CTLFireability-00: DISJ true CTL model checker
DES-PT-10a-CTLFireability-01: CTL unknown AGGR
DES-PT-10a-CTLFireability-02: CTL false CTL model checker
DES-PT-10a-CTLFireability-03: CTL true CTL model checker
DES-PT-10a-CTLFireability-04: CTL unknown AGGR
DES-PT-10a-CTLFireability-05: CTL unknown AGGR
DES-PT-10a-CTLFireability-06: CTL false CTL model checker
DES-PT-10a-CTLFireability-07: CTL false CTL model checker
DES-PT-10a-CTLFireability-08: CTL unknown AGGR
DES-PT-10a-CTLFireability-09: CTL false CTL model checker
DES-PT-10a-CTLFireability-10: CTL true CTL model checker
DES-PT-10a-CTLFireability-11: CTL false CTL model checker
DES-PT-10a-CTLFireability-12: CTL unknown AGGR
DES-PT-10a-CTLFireability-13: CTL true CTL model checker
DES-PT-10a-CTLFireability-14: CTL true CTL model checker
DES-PT-10a-CTLFireability-15: DISJ false DISJ


Time elapsed: 213 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="DES-PT-10a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is DES-PT-10a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r102-tall-167814476800410"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/DES-PT-10a.tgz
mv DES-PT-10a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;