Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r073-smll-167814399100098.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool ltsminxred
Input is CircadianClock-PT-000001, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r073-smll-167814399100098
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 448K
-rw-r--r-- 1 mcc users 7.3K Feb 26 10:31 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K Feb 26 10:31 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K Feb 26 10:31 CTLFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 26 10:31 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 15:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 15:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 15:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 15:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 9.5K Feb 26 10:31 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 100K Feb 26 10:31 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.6K Feb 26 10:31 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 67K Feb 26 10:31 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 12K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-00
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-01
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-02
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-03
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-04
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-05
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-06
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-07
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-08
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-09
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-10
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-11
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-12
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-13
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-14
FORMULA_NAME CircadianClock-PT-000001-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678278027198

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=ltsminxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CircadianClock-PT-000001
Applying reductions before tool ltsmin
Invoking reducer
Running Version 202303021504
[2023-03-08 12:20:29] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 12:20:29] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 12:20:30] [INFO ] Load time of PNML (sax parser for PT used): 40 ms
[2023-03-08 12:20:30] [INFO ] Transformed 14 places.
[2023-03-08 12:20:30] [INFO ] Transformed 16 transitions.
[2023-03-08 12:20:30] [INFO ] Found NUPN structural information;
[2023-03-08 12:20:30] [INFO ] Parsed PT model containing 14 places and 16 transitions and 58 arcs in 387 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 17 ms.
Initial state reduction rules removed 2 formulas.
FORMULA CircadianClock-PT-000001-CTLFireability-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA CircadianClock-PT-000001-CTLFireability-14 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 14 out of 14 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 14 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
[2023-03-08 12:20:30] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
// Phase 1: matrix 14 rows 14 cols
[2023-03-08 12:20:30] [INFO ] Computed 7 place invariants in 4 ms
[2023-03-08 12:20:30] [INFO ] Implicit Places using invariants in 191 ms returned []
[2023-03-08 12:20:30] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 12:20:30] [INFO ] Invariant cache hit.
[2023-03-08 12:20:30] [INFO ] State equation strengthened by 2 read => feed constraints.
[2023-03-08 12:20:30] [INFO ] Implicit Places using invariants and state equation in 69 ms returned []
Implicit Place search using SMT with State Equation took 311 ms to find 0 implicit places.
[2023-03-08 12:20:30] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 12:20:30] [INFO ] Invariant cache hit.
[2023-03-08 12:20:30] [INFO ] Dead Transitions using invariants and state equation in 54 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 381 ms. Remains : 14/14 places, 16/16 transitions.
Support contains 14 out of 14 places after structural reductions.
[2023-03-08 12:20:30] [INFO ] Flatten gal took : 21 ms
[2023-03-08 12:20:30] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:20:30] [INFO ] Input system was already deterministic with 16 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 170 ms. (steps per millisecond=58 ) properties (out of 37) seen :36
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 39 ms. (steps per millisecond=256 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-08 12:20:31] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 12:20:31] [INFO ] Invariant cache hit.
[2023-03-08 12:20:31] [INFO ] [Real]Absence check using 7 positive place invariants in 5 ms returned sat
[2023-03-08 12:20:31] [INFO ] After 70ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 1 atomic propositions for a total of 14 simplifications.
FORMULA CircadianClock-PT-000001-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 5 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 3 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 3 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 3 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 3 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 3 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 7 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 8 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 2 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 1 ms
[2023-03-08 12:20:31] [INFO ] Input system was already deterministic with 16 transitions.
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 3 ms
[2023-03-08 12:20:31] [INFO ] Flatten gal took : 3 ms
[2023-03-08 12:20:31] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-08 12:20:31] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 14 places, 16 transitions and 58 arcs took 1 ms.
Total runtime 1976 ms.
There are residual formulas that ITS could not solve within timeout
pnml2lts-sym model.pnml --lace-workers=4 --vset=lddmc --saturation=sat -rbs,w2W,ru,hf --sylvan-sizes=20,28,20,28 --ctl=/tmp/462/ctl_0_ --ctl=/tmp/462/ctl_1_ --ctl=/tmp/462/ctl_2_ --ctl=/tmp/462/ctl_3_ --ctl=/tmp/462/ctl_4_ --ctl=/tmp/462/ctl_5_ --ctl=/tmp/462/ctl_6_ --ctl=/tmp/462/ctl_7_ --ctl=/tmp/462/ctl_8_ --ctl=/tmp/462/ctl_9_ --ctl=/tmp/462/ctl_10_ --ctl=/tmp/462/ctl_11_ --ctl=/tmp/462/ctl_12_ --mu-par --mu-opt
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-00
FORMULA CircadianClock-PT-000001-CTLFireability-01 FALSE TECHNIQUES DECISION_DIAGRAMS PARALLEL_PROCESSING USE_NUPN
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-02
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-03
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-04
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-05
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-07
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-09
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-10
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-11
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-12
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-13
Could not compute solution for formula : CircadianClock-PT-000001-CTLFireability-15

BK_STOP 1678278033043

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
mcc2023
ctl formula name CircadianClock-PT-000001-CTLFireability-00
ctl formula formula --ctl=/tmp/462/ctl_0_
ctl formula name CircadianClock-PT-000001-CTLFireability-01
ctl formula formula --ctl=/tmp/462/ctl_1_
ctl formula name CircadianClock-PT-000001-CTLFireability-02
ctl formula formula --ctl=/tmp/462/ctl_2_
ctl formula name CircadianClock-PT-000001-CTLFireability-03
ctl formula formula --ctl=/tmp/462/ctl_3_
ctl formula name CircadianClock-PT-000001-CTLFireability-04
ctl formula formula --ctl=/tmp/462/ctl_4_
ctl formula name CircadianClock-PT-000001-CTLFireability-05
ctl formula formula --ctl=/tmp/462/ctl_5_
ctl formula name CircadianClock-PT-000001-CTLFireability-07
ctl formula formula --ctl=/tmp/462/ctl_6_
ctl formula name CircadianClock-PT-000001-CTLFireability-09
ctl formula formula --ctl=/tmp/462/ctl_7_
ctl formula name CircadianClock-PT-000001-CTLFireability-10
ctl formula formula --ctl=/tmp/462/ctl_8_
ctl formula name CircadianClock-PT-000001-CTLFireability-11
ctl formula formula --ctl=/tmp/462/ctl_9_
ctl formula name CircadianClock-PT-000001-CTLFireability-12
ctl formula formula --ctl=/tmp/462/ctl_10_
ctl formula name CircadianClock-PT-000001-CTLFireability-13
ctl formula formula --ctl=/tmp/462/ctl_11_
ctl formula name CircadianClock-PT-000001-CTLFireability-15
ctl formula formula --ctl=/tmp/462/ctl_12_
pnml2lts-sym: Exploration order is bfs-prev
pnml2lts-sym: Saturation strategy is sat
pnml2lts-sym: Guided search strategy is unguided
pnml2lts-sym: Attractor strategy is default
pnml2lts-sym: opening model.pnml
pnml2lts-sym: Edge label is id
Warning: program compiled against libxml 210 using older 209
pnml2lts-sym: Petri net has 14 places, 16 transitions and 58 arcs
pnml2lts-sym: Petri net Petri analyzed
pnml2lts-sym: There are no safe places
pnml2lts-sym: Loading Petri net took 0.010 real 0.000 user 0.000 sys
pnml2lts-sym: Initializing regrouping layer
pnml2lts-sym: Regroup specification: bs,w2W,ru,hf
pnml2lts-sym: Regroup Boost's Sloan
pnml2lts-sym: Regroup over-approximate must-write to may-write
pnml2lts-sym: Regroup Row sUbsume
pnml2lts-sym: Reqroup Horizontal Flip
pnml2lts-sym: Regrouping: 16->9 groups
pnml2lts-sym: Regrouping took 0.000 real 0.000 user 0.000 sys
pnml2lts-sym: state vector length is 14; there are 9 groups
pnml2lts-sym: Creating a multi-core ListDD domain.
pnml2lts-sym: Sylvan allocates 15.000 GB virtual memory for nodes table and operation cache.
pnml2lts-sym: Initial nodes table and operation cache requires 60.00 MB.
pnml2lts-sym: Using GBgetTransitionsShortR2W as next-state function
pnml2lts-sym: got initial state
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: parsing CTL formula
pnml2lts-sym: converting CTL to mu-calculus...
pnml2lts-sym: Exploration took 61 group checks and 0 next state calls
pnml2lts-sym: reachability took 0.020 real 0.070 user 0.030 sys
pnml2lts-sym: counting visited states...
pnml2lts-sym: counting took 0.000 real 0.000 user 0.000 sys
pnml2lts-sym: state space has 128 states, 28 nodes
pnml2lts-sym: Formula /tmp/462/ctl_1_ does not hold for the initial state
*** segmentation fault ***

Please send information on how to reproduce this problem to:
ltsmin-support@lists.utwente.nl
along with all output preceding this message.
In addition, include the following information:
Package: ltsmin 3.1.0
Stack trace:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CircadianClock-PT-000001"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="ltsminxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool ltsminxred"
echo " Input is CircadianClock-PT-000001, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r073-smll-167814399100098"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CircadianClock-PT-000001.tgz
mv CircadianClock-PT-000001 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;