MCC'2023- Execution of r071-smll-167814398000442

About the Execution of LoLa+red for CloudDeployment-PT-7a

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
3370.199	3600000.00	970900.00	11936.00	TFTFF?TTT?TFT?F?	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r071-s
Waiting for the VM to be ready
........................................
==================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is CloudDeployment-PT-7a,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-smll-16781439
========================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 792K
-rw-r--r-- 1 mcc users 6.4K Feb
-rw-r--r-- 1 mcc users 61K Feb
-rw-r--r-- 1 mcc users 6.4K Feb
-rw-r--r-- 1 mcc users 64K Feb
-rw-r--r-- 1 mcc users 4.2K Jan
-rw-r--r-- 1 mcc users 6.8K Jan
-rw-r--r-- 1 mcc users 3.4K Feb
-rw-r--r-- 1 mcc users 21K Feb
-rw-r--r-- 1 mcc users 2.2K Feb
-rw-r--r-- 1 mcc users 17K Feb
-rw-r--r-- 1 mcc users 7.2K Feb
-rw-r--r-- 1 mcc users 67K Feb
-rw-r--r-- 1 mcc users 7.0K Feb
-rw-r--r-- 1 mcc users 56K Feb
-rw-r--r-- 1 mcc users 1.7K Feb
-rw-r--r-- 1 mcc users 3.7K Feb
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 3 Mar
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 420K Mar

--------------------
content from stdout:

=== Data for post analysis generated

The expected result is a vector
BOOL_VECTOR

here is the order used to build
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi
FORMULA_NAME CloudDeployment-PT-7a-CTLFi

=== Now, execution of the tool begins

BK_START 1678288097959

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CloudDeployment-PT-7a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 15:08:21] [INFO ]
[2023-03-08 15:08:21] [INFO ]
[2023-03-08 15:08:21] [INFO ]
[2023-03-08 15:08:21] [INFO ]
[2023-03-08 15:08:21] [INFO ]
[2023-03-08 15:08:21] [INFO ]
[2023-03-08 15:08:21] [INFO ]
Parsed 16 properties from file
Ensure Unique test removed 154
Reduce redundant transitions removed
Support contains 105 out of 264
Starting structural reductions
Ensure Unique test removed 14 places
Iterating post reduction 0 with
Discarding 5 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 4 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 3 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 2 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Drop transitions removed 98 transitions
Redundant transition composition
Iterating global reduction 1 with
Applied a total of 140 rules in
[2023-03-08 15:08:21] [INFO ]
// Phase 1: matrix 461 rows 236 cols
[2023-03-08 15:08:21] [INFO ]
[2023-03-08 15:08:22] [INFO ]
[2023-03-08 15:08:22] [INFO ]
[2023-03-08 15:08:22] [INFO ]
[2023-03-08 15:08:22] [INFO ]
[2023-03-08 15:08:23] [INFO ]
Implicit Place search using SMT
[2023-03-08 15:08:23] [INFO ]
[2023-03-08 15:08:23] [INFO ]
[2023-03-08 15:08:24] [INFO ]
Starting structural reductions
Finished structural reductions
Support contains 105 out of 236
[2023-03-08 15:08:24] [INFO ]
[2023-03-08 15:08:24] [INFO ]
[2023-03-08 15:08:25] [INFO ]
Support contains 104 out of 236
Incomplete random walk after 10000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Running SMT prover for 33 properties.
[2023-03-08 15:08:26] [INFO ]
[2023-03-08 15:08:26] [INFO ]
[2023-03-08 15:08:26] [INFO ]
[2023-03-08 15:08:27] [INFO ]
[2023-03-08 15:08:28] [INFO ]
[2023-03-08 15:08:30] [INFO ]
[2023-03-08 15:08:30] [INFO ]
[2023-03-08 15:08:31] [INFO ]
[2023-03-08 15:08:34] [INFO ]
Attempting to minimize the solution
Minimization took 1344 ms.
[2023-03-08 15:08:35] [INFO ]
Fused 33 Parikh solutions to 29
Parikh walk visited 0 properties
Support contains 52 out of 236
Starting structural reductions
Graph (trivial) has 174 edges and
Free SCC test removed 27 places
Drop transitions removed 111 transitions
Ensure Unique test removed 13 transition
Reduce isomorphic transitions removed
Graph (complete) has 1480 edges
Discarding 1 places :
Also discarding 0 output transitions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Performed 3 Post agglomeration
Deduced a syphon composed of 3
Reduce places removed 3 places
Iterating global reduction 0 with
Performed 18 Post agglomeration
Deduced a syphon composed of 18
Reduce places removed 18 places
Iterating global reduction 0 with
Drop transitions removed 118 transitions
Redundant transition composition
Iterating global reduction 0 with
Performed 3 Post agglomeration
Deduced a syphon composed of 3
Reduce places removed 3 places
Iterating global reduction 0 with
Free-agglomeration rule applied
Iterating global reduction 0 with
Reduce places removed 1 places
Iterating post reduction 0 with
Free-agglomeration rule (complex)
Iterating global reduction 1 with
Reduce places removed 2 places
Iterating post reduction 1 with
Partial Free-agglomeration rule
Drop transitions removed 2 transitions
Iterating global reduction 2 with
Applied a total of 178 rules in
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Running SMT prover for 23 properties.
[2023-03-08 15:08:37] [INFO ]
// Phase 1: matrix 323 rows 180 cols
[2023-03-08 15:08:37] [INFO ]
[2023-03-08 15:08:37] [INFO ]
[2023-03-08 15:08:37] [INFO ]
[2023-03-08 15:08:38] [INFO ]
[2023-03-08 15:08:38] [INFO ]
[2023-03-08 15:08:38] [INFO ]
[2023-03-08 15:08:40] [INFO ]
[2023-03-08 15:08:40] [INFO ]
[2023-03-08 15:08:41] [INFO ]
[2023-03-08 15:08:43] [INFO ]
Attempting to minimize the solution
Minimization took 1275 ms.
[2023-03-08 15:08:44] [INFO ]
Fused 23 Parikh solutions to 22
Parikh walk visited 0 properties
Support contains 45 out of 180
Starting structural reductions
Graph (trivial) has 58 edges and
Free SCC test removed 3 places
Drop transitions removed 6 transitions
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded
Performed 1 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 1 places
Iterating post reduction 1 with
Discarding 1 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Partial Free-agglomeration rule
Drop transitions removed 1 transitions
Iterating global reduction 2 with
Applied a total of 6 rules in 109
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Running SMT prover for 17 properties.
[2023-03-08 15:08:45] [INFO ]
// Phase 1: matrix 308 rows 175 cols
[2023-03-08 15:08:45] [INFO ]
[2023-03-08 15:08:45] [INFO ]
[2023-03-08 15:08:45] [INFO ]
[2023-03-08 15:08:46] [INFO ]
[2023-03-08 15:08:46] [INFO ]
[2023-03-08 15:08:46] [INFO ]
[2023-03-08 15:08:47] [INFO ]
[2023-03-08 15:08:47] [INFO ]
[2023-03-08 15:08:48] [INFO ]
[2023-03-08 15:08:49] [INFO ]
Attempting to minimize the solution
Minimization took 831 ms.
[2023-03-08 15:08:50] [INFO ]
Fused 17 Parikh solutions to 16
Parikh walk visited 0 properties
Support contains 37 out of 175
Starting structural reductions
Graph (trivial) has 68 edges and
Free SCC test removed 3 places
Drop transitions removed 6 transitions
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Performed 1 Post agglomeration
Deduced a syphon composed of 1
Reduce places removed 1 places
Iterating global reduction 0 with
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Free-agglomeration rule applied
Iterating global reduction 1 with
Reduce places removed 1 places
Iterating post reduction 1 with
Partial Free-agglomeration rule
Drop transitions removed 1 transitions
Iterating global reduction 2 with
Applied a total of 15 rules in
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Interrupted probabilistic random walk after 222688
Probabilistic random walk after 222688
Running SMT prover for 16 properties.
[2023-03-08 15:08:54] [INFO ]
// Phase 1: matrix 292 rows 169 cols
[2023-03-08 15:08:54] [INFO ]
[2023-03-08 15:08:54] [INFO ]
[2023-03-08 15:08:54] [INFO ]
[2023-03-08 15:08:55] [INFO ]
[2023-03-08 15:08:55] [INFO ]
[2023-03-08 15:08:55] [INFO ]
[2023-03-08 15:08:56] [INFO ]
[2023-03-08 15:08:56] [INFO ]
[2023-03-08 15:08:57] [INFO ]
[2023-03-08 15:08:58] [INFO ]
Attempting to minimize the solution
Minimization took 736 ms.
[2023-03-08 15:08:59] [INFO ]
Fused 16 Parikh solutions to 15
Parikh walk visited 0 properties
Support contains 35 out of 169
Starting structural reductions
Applied a total of 0 rules in 28
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Interrupted probabilistic random walk after 222031
Probabilistic random walk after 222031
Running SMT prover for 15 properties.
[2023-03-08 15:09:02] [INFO ]
[2023-03-08 15:09:02] [INFO ]
[2023-03-08 15:09:03] [INFO ]
[2023-03-08 15:09:03] [INFO ]
[2023-03-08 15:09:03] [INFO ]
[2023-03-08 15:09:03] [INFO ]
[2023-03-08 15:09:03] [INFO ]
[2023-03-08 15:09:04] [INFO ]
[2023-03-08 15:09:04] [INFO ]
[2023-03-08 15:09:05] [INFO ]
[2023-03-08 15:09:06] [INFO ]
Attempting to minimize the solution
Minimization took 697 ms.
[2023-03-08 15:09:06] [INFO ]
Fused 15 Parikh solutions to 14
Parikh walk visited 0 properties
Support contains 34 out of 169
Starting structural reductions
Graph (trivial) has 64 edges and
Free SCC test removed 2 places
Drop transitions removed 4 transitions
Ensure Unique test removed 7 transitions
Reduce isomorphic transitions removed
Applied a total of 1 rules in 30
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Interrupted probabilistic random walk after 220650
Probabilistic random walk after 220650
Running SMT prover for 15 properties.
[2023-03-08 15:09:10] [INFO ]
// Phase 1: matrix 281 rows 167 cols
[2023-03-08 15:09:10] [INFO ]
[2023-03-08 15:09:10] [INFO ]
[2023-03-08 15:09:10] [INFO ]
[2023-03-08 15:09:11] [INFO ]
[2023-03-08 15:09:11] [INFO ]
[2023-03-08 15:09:11] [INFO ]
[2023-03-08 15:09:12] [INFO ]
[2023-03-08 15:09:12] [INFO ]
[2023-03-08 15:09:13] [INFO ]
[2023-03-08 15:09:14] [INFO ]
Attempting to minimize the solution
Minimization took 671 ms.
[2023-03-08 15:09:14] [INFO ]
Fused 15 Parikh solutions to 14
Parikh walk visited 0 properties
Support contains 34 out of 167
Starting structural reductions
Applied a total of 0 rules in 26
Finished structural reductions
Starting structural reductions
Applied a total of 0 rules in 26
[2023-03-08 15:09:15] [INFO ]
[2023-03-08 15:09:15] [INFO ]
[2023-03-08 15:09:15] [INFO ]
[2023-03-08 15:09:15] [INFO ]
[2023-03-08 15:09:15] [INFO ]
[2023-03-08 15:09:15] [INFO ]
[2023-03-08 15:09:15] [INFO ]
Implicit Place search using SMT
[2023-03-08 15:09:16] [INFO ]
[2023-03-08 15:09:16] [INFO ]
[2023-03-08 15:09:16] [INFO ]
[2023-03-08 15:09:16] [INFO ]
Finished structural reductions
Graph (trivial) has 109 edges and
Free SCC test removed 26 places
Drop transitions removed 36 transitions
Ensure Unique test removed 378
Reduce isomorphic transitions removed
Ensure Unique test removed 2 places
Drop transitions removed 31 transitions
Trivial Post-agglo rules discarded
Performed 31 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 31 places
Performed 3 Post agglomeration
Iterating post reduction 1 with
Reduce places removed 3 places
Iterating post reduction 2 with
Performed 11 Pre agglomeration
Pre-agglomeration after 3 with
Deduced a syphon composed of 11
Reduce places removed 11 places
Iterating global reduction 3 with
Discarding 6 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Discarding 4 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 12 transition
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 2 Post agglomeration
Deduced a syphon composed of 2
Reduce places removed 2 places
Iterating global reduction 4 with
Performed 3 Post agglomeration
Deduced a syphon composed of 3
Reduce places removed 3 places
Iterating global reduction 4 with
Drop transitions removed 39 transitions
Redundant transition composition
Iterating global reduction 4 with
Performed 1 Post agglomeration
Iterating post reduction 4 with
Reduce places removed 1 places
Iterating post reduction 5 with
Performed 2 Post agglomeration
Deduced a syphon composed of 2
Reduce places removed 2 places
Iterating global reduction 6 with
Free-agglomeration rule applied
Iterating global reduction 6 with
Reduce places removed 3 places
Iterating post reduction 6 with
Drop transitions removed 1 transitions
Redundant transition composition
Iterating global reduction 7 with
Performed 1 Post agglomeration
Deduced a syphon composed of 1
Reduce places removed 1 places
Iterating global reduction 7 with
Partial Free-agglomeration rule
Drop transitions removed 1 transitions
Iterating global reduction 7 with
Partial Post-agglomeration rule
Drop transitions removed 1 transitions
Iterating global reduction 7 with
Applied a total of 191 rules in
Running SMT prover for 15 properties.
[2023-03-08 15:09:16] [INFO ]
// Phase 1: matrix 139 rows 72 cols
[2023-03-08 15:09:16] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:17] [INFO ]
[2023-03-08 15:09:18] [INFO ]
Attempting to minimize the solution
Minimization took 197 ms.
[2023-03-08 15:09:18] [INFO ]
Successfully simplified 3 atomic
Initial state reduction rules removed
FORMULA CloudDeployment-PT-7a-CTLFireability-00
[2023-03-08 15:09:18] [INFO
[2023-03-08 15:09:18] [INFO ]
[2023-03-08 15:09:18] [INFO ]
Computed a total of 117 stabilizing
Graph (complete) has 2489 edges
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 13
Finished structural reductions
[2023-03-08 15:09:18] [INFO ]
[2023-03-08 15:09:18] [INFO ]
[2023-03-08 15:09:19] [INFO ]
Starting structural reductions
Graph (trivial) has 275 edges and
Free SCC test removed 49 places
Ensure Unique test removed 147
Reduce isomorphic transitions removed
Discarding 8 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Drop transitions removed 28 transitions
Redundant transition composition
Iterating global reduction 0 with
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded
Performed 7 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 7 places
Iterating post reduction 1 with
Performed 7 Post agglomeration
Deduced a syphon composed of 7
Reduce places removed 7 places
Iterating global reduction 2 with
Applied a total of 73 rules in
Finished structural reductions
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 9
Finished structural reductions
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 8
Finished structural reductions
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 8
Finished structural reductions
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
Starting structural reductions
Graph (trivial) has 268 edges and
Free SCC test removed 49 places
Ensure Unique test removed 147
Reduce isomorphic transitions removed
Discarding 8 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Drop transitions removed 25 transitions
Redundant transition composition
Iterating global reduction 0 with
Drop transitions removed 5 transitions
Trivial Post-agglo rules discarded
Performed 5 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 5 places
Iterating post reduction 1 with
Performed 7 Post agglomeration
Deduced a syphon composed of 7
Reduce places removed 7 places
Iterating global reduction 2 with
Partial Post-agglomeration rule
Drop transitions removed 1 transitions
Iterating global reduction 2 with
Applied a total of 67 rules in
Finished structural reductions
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:19] [INFO ]
[2023-03-08 15:09:20] [INFO ]
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 9
Finished structural reductions
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 8
Finished structural reductions
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
Starting structural reductions
Applied a total of 0 rules in 5
Finished structural reductions
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 8
Finished structural reductions
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
Starting structural reductions
Graph (trivial) has 260 edges and
Free SCC test removed 49 places
Ensure Unique test removed 147
Reduce isomorphic transitions removed
Discarding 8 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Drop transitions removed 28 transitions
Redundant transition composition
Iterating global reduction 0 with
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded
Performed 7 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 7 places
Iterating post reduction 1 with
Performed 7 Post agglomeration
Deduced a syphon composed of 7
Reduce places removed 7 places
Iterating global reduction 2 with
Applied a total of 73 rules in
Finished structural reductions
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 10
Finished structural reductions
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:20] [INFO ]
[2023-03-08 15:09:21] [INFO ]
Starting structural reductions
Discarding 1 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Applied a total of 2 rules in 6
Finished structural reductions
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
Starting structural reductions
Graph (trivial) has 258 edges and
Free SCC test removed 44 places
Ensure Unique test removed 129
Reduce isomorphic transitions removed
Discarding 7 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Drop transitions removed 29 transitions
Redundant transition composition
Iterating global reduction 0 with
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded
Performed 6 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 6 places
Iterating post reduction 1 with
Performed 9 Post agglomeration
Deduced a syphon composed of 9
Reduce places removed 9 places
Iterating global reduction 2 with
Applied a total of 74 rules in
Finished structural reductions
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
Starting structural reductions
Graph (trivial) has 257 edges and
Free SCC test removed 46 places
Ensure Unique test removed 140
Reduce isomorphic transitions removed
Discarding 8 places :
Symmetric choice reduction at 0
Iterating global reduction 0 with
Drop transitions removed 26 transitions
Redundant transition composition
Iterating global reduction 0 with
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded
Performed 6 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 6 places
Iterating post reduction 1 with
Performed 7 Post agglomeration
Deduced a syphon composed of 7
Reduce places removed 7 places
Iterating global reduction 2 with
Applied a total of 69 rules in
Finished structural reductions
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
[2023-03-08 15:09:21] [INFO ]
Total runtime 60618 ms.
There are residual formulas that
starting LoLA
BK_INPUT CloudDeployment-PT-7a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//.
current directory: /home/mcc/execution/3
CTLFireability

FORMULA CloudDeployment-PT-7a-CTLFireability-10

FORMULA CloudDeployment-PT-7a-CTLFireability-02

FORMULA CloudDeployment-PT-7a-CTLFireability-14

FORMULA CloudDeployment-PT-7a-CTLFireability-12

FORMULA CloudDeployment-PT-7a-CTLFireability-08

FORMULA CloudDeployment-PT-7a-CTLFireability-07

FORMULA CloudDeployment-PT-7a-CTLFireability-04

FORMULA CloudDeployment-PT-7a-CTLFireability-03

FORMULA CloudDeployment-PT-7a-CTLFireability-01

FORMULA CloudDeployment-PT-7a-CTLFireability-06

FORMULA CloudDeployment-PT-7a-CTLFireability-11
TIME LIMIT: Killed by timeout
MemTotal: 16393216 kB
MemFree: 12781856 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16103620 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/i
+ PYTHONPATH=/home/mcc/BenchKit/itstools
+ export LD_LIBRARY_PATH=/home/mcc/Bench
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/its
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execu
lola: reading pnml
lola: PNML file contains place/transition
lola: finished parsing
lola: closed net file /home/mcc/execut
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/e
lola: rewrite Frontend/Parser/formula_
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lola: rewrite Frontend/Parser/formula_
lola: RELEASE
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lola: RELEASE
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lola: RELEASE
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lola: RELEASE
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Rule S: 0 transitions removed,0
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: Created skeleton in 0.000000
lola: LAUNCH INITIAL
lola: LAUNCH task # 32 (type
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 32 (type
lola: result : true
lola: Created skeleton in 0.000000
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lola: rewrite Frontend/Parser/formula_
lola: rewrite Frontend/Parser/formula_
lola: LAUNCH task # 4 (type EXCL)
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type
lola: result : true
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: Created skeleton in 0.000000
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lola: rewrite Frontend/Parser/formula_
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lola: LAUNCH task # 44 (type
lola: time limit : 256 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_
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lola: FINISHED task # 44 (type
lola: result : false
lola: markings :
lola: fired transitions :
lola: time used :
lola: memory pages used :
lola: LAUNCH task # 29 (type
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_
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=================================================== examination is CTLFireability 8000442 ============================= 25 15:43 CTLCardinality.txt 25 15:43 CTLCardinality.xml 25 15:22 CTLFireability.txt 25 15:22 CTLFireability.xml 29 11:40 GenericPropertiesDefinition.xml 29 11:40 GenericPropertiesVerdict.xml 25 15:45 LTLCardinality.txt 25 15:45 LTLCardinality.xml 25 15:45 LTLFireability.txt 25 15:45 LTLFireability.xml 25 16:21 ReachabilityCardinality.txt 25 16:21 ReachabilityCardinality.xml 25 16:08 ReachabilityFireability.txt 25 16:08 ReachabilityFireability.xml 25 15:45 UpperBounds.txt 25 15:45 UpperBounds.xml 5 18:22 equiv_col 5 18:22 instance 5 18:22 iscolored 5 18:22 model.pnml by BenchKit (invocation template) of booleans the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML] Parsing pnml file : /home/mcc/execution/model.pnml Load time of PNML (sax parser for PT used): 289 ms Transformed 264 places. Transformed 1174 transitions. Found NUPN structural information; Parsed PT model containing 264 places and 1174 transitions and 7331 arcs in 463 ms. /home/mcc/execution/CTLFireability.xml in 25 ms. transitions 154 transitions. places. Attempting structural reductions. in LTL mode, iteration 0 : 264/264 places, 1020/1020 transitions. 14 rules applied. Total rules applied 14 place count 250 transition count 1020 with 5 rule applications. Total rules 19 place count 245 transition count 1015 5 rules applied. Total rules applied 24 place count 245 transition count 1015 with 4 rule applications. Total rules 28 place count 241 transition count 1011 4 rules applied. Total rules applied 32 place count 241 transition count 1011 with 3 rule applications. Total rules 35 place count 238 transition count 1008 3 rules applied. Total rules applied 38 place count 238 transition count 1008 with 2 rule applications. Total rules 40 place count 236 transition count 1006 2 rules applied. Total rules applied 42 place count 236 transition count 1006 rules discarded 98 transitions 98 rules applied. Total rules applied 140 place count 236 transition count 908 167 ms. Remains 236 /264 variables (removed 28) and now considering 908/1020 (removed 112) transitions. Flow matrix only has 461 transitions (discarded 447 similar events) Computed 28 place invariants in 27 ms Implicit Places using invariants in 375 ms returned [] Flow matrix only has 461 transitions (discarded 447 similar events) Invariant cache hit. State equation strengthened by 226 read => feed constraints. Implicit Places using invariants and state equation in 897 ms returned [] with State Equation took 1313 ms to find 0 implicit places. Flow matrix only has 461 transitions (discarded 447 similar events) Invariant cache hit. Dead Transitions using invariants and state equation in 836 ms found 0 transitions. in LTL mode, iteration 1 : 236/264 places, 908/1020 transitions. in LTL mode , in 1 iterations and 2319 ms. Remains : 236/264 places, 908/1020 transitions. places after structural reductions. Flatten gal took : 237 ms Flatten gal took : 149 ms Input system was already deterministic with 908 transitions. places (down from 105) after GAL structural reductions. steps, including 95 resets, run finished after 730 ms. (steps per millisecond=13 ) properties (out of 105) seen :70 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 35) seen :1 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 34) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 34) seen :1 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=91 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 33) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 33) seen :0 Flow matrix only has 461 transitions (discarded 447 similar events) Invariant cache hit. [Real]Absence check using 0 positive and 28 generalized place invariants in 12 ms returned sat After 1342ms SMT Verify possible using all constraints in real domain returned unsat :2 sat :0 real:31 [Nat]Absence check using 0 positive and 28 generalized place invariants in 27 ms returned sat After 1538ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :30 State equation strengthened by 226 read => feed constraints. After 1879ms SMT Verify possible using 226 Read/Feed constraints in natural domain returned unsat :3 sat :30 After 4317ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :30 found. After 7967ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :30 different solutions. in 725 ms. places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 236/236 places, 908/908 transitions. 236 vertex of which 39 / 236 are part of one of the 12 SCC in 5 ms s 124 transitions. and 209 vertex of which 208 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.8 ms with 1 rule applications. Total rules 3 place count 207 transition count 783 1 rules applied. Total rules applied 4 place count 207 transition count 783 using F-continuation condition.Transition count delta: 3 places in 1 ms and 0 transitions. 6 rules applied. Total rules applied 10 place count 204 transition count 780 using F-continuation condition.Transition count delta: -66 places in 1 ms and 0 transitions. 36 rules applied. Total rules applied 46 place count 186 transition count 846 rules discarded 118 transitions 118 rules applied. Total rules applied 164 place count 186 transition count 728 using F-continuation condition.Transition count delta: 3 places in 1 ms and 0 transitions. 6 rules applied. Total rules applied 170 place count 183 transition count 725 1 times. 1 rules applied. Total rules applied 171 place count 183 transition count 724 and 0 transitions. 1 rules applied. Total rules applied 172 place count 182 transition count 724 applied 2 times. 2 rules applied. Total rules applied 174 place count 182 transition count 722 and 0 transitions. 2 rules applied. Total rules applied 176 place count 180 transition count 722 applied 2 times. 2 rules applied. Total rules applied 178 place count 180 transition count 722 322 ms. Remains 180 /236 variables (removed 56) and now considering 722/908 (removed 186) transitions. in REACHABILITY mode , in 1 iterations and 323 ms. Remains : 180/236 places, 722/908 transitions. steps, including 129 resets, run finished after 464 ms. (steps per millisecond=21 ) properties (out of 30) seen :2 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 28) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 28) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 28) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 28) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 28) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 28) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 28) seen :1 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 27) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 27) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 27) seen :2 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 25) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 25) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 25) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 25) seen :1 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 24) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 24) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 24) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 24) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 24) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 24) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 24) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 24) seen :1 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 23) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 23) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 23) seen :0 Flow matrix only has 323 transitions (discarded 399 similar events) Computed 28 place invariants in 3 ms [Real]Absence check using 7 positive place invariants in 4 ms returned sat [Real]Absence check using 7 positive and 21 generalized place invariants in 7 ms returned sat After 1060ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:23 [Nat]Absence check using 7 positive place invariants in 5 ms returned sat [Nat]Absence check using 7 positive and 21 generalized place invariants in 14 ms returned sat After 1259ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :23 State equation strengthened by 204 read => feed constraints. After 1245ms SMT Verify possible using 204 Read/Feed constraints in natural domain returned unsat :0 sat :23 After 2844ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :23 found. After 5805ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :23 different solutions. in 381 ms. places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 180/180 places, 722/722 transitions. 180 vertex of which 5 / 180 are part of one of the 2 SCC in 1 ms 13 transitions. 1 transitions Transition count delta: 1 1 rules applied. Total rules applied 2 place count 177 transition count 708 and 0 transitions. 1 rules applied. Total rules applied 3 place count 176 transition count 708 with 1 rule applications. Total rules 4 place count 175 transition count 700 1 rules applied. Total rules applied 5 place count 175 transition count 700 applied 1 times. 1 rules applied. Total rules applied 6 place count 175 transition count 700 ms. Remains 175 /180 variables (removed 5) and now considering 700/722 (removed 22) transitions. in REACHABILITY mode , in 1 iterations and 109 ms. Remains : 175/180 places, 700/722 transitions. steps, including 135 resets, run finished after 513 ms. (steps per millisecond=19 ) properties (out of 23) seen :2 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 3 ms. (steps per millisecond=333 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 21) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 21) seen :1 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 20) seen :1 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 19) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 19) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 19) seen :2 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0 Flow matrix only has 308 transitions (discarded 392 similar events) Computed 28 place invariants in 4 ms [Real]Absence check using 7 positive place invariants in 4 ms returned sat [Real]Absence check using 7 positive and 21 generalized place invariants in 9 ms returned sat After 1014ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:17 [Nat]Absence check using 7 positive place invariants in 6 ms returned sat [Nat]Absence check using 7 positive and 21 generalized place invariants in 9 ms returned sat After 886ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :17 State equation strengthened by 197 read => feed constraints. After 826ms SMT Verify possible using 197 Read/Feed constraints in natural domain returned unsat :0 sat :17 After 1853ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :17 found. After 3904ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :17 different solutions. in 298 ms. places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 175/175 places, 700/700 transitions. 175 vertex of which 6 / 175 are part of one of the 3 SCC in 0 ms 13 transitions. with 1 rule applications. Total rules 2 place count 171 transition count 679 1 rules applied. Total rules applied 3 place count 171 transition count 679 using F-continuation condition.Transition count delta: 1 places in 1 ms and 0 transitions. 2 rules applied. Total rules applied 5 place count 170 transition count 678 7 transitions. 7 rules applied. Total rules applied 12 place count 170 transition count 671 1 times. 1 rules applied. Total rules applied 13 place count 170 transition count 670 and 0 transitions. 1 rules applied. Total rules applied 14 place count 169 transition count 670 applied 1 times. 1 rules applied. Total rules applied 15 place count 169 transition count 670 117 ms. Remains 169 /175 variables (removed 6) and now considering 670/700 (removed 30) transitions. in REACHABILITY mode , in 1 iterations and 118 ms. Remains : 169/175 places, 670/700 transitions. steps, including 134 resets, run finished after 460 ms. (steps per millisecond=21 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 17) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=74 ) properties seen :{7=1} steps, saw 45018 distinct states, run finished after 3004 ms. (steps per millisecond=74 ) properties seen :1 Flow matrix only has 292 transitions (discarded 378 similar events) Computed 28 place invariants in 4 ms [Real]Absence check using 7 positive place invariants in 4 ms returned sat [Real]Absence check using 7 positive and 21 generalized place invariants in 9 ms returned sat After 873ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:16 [Nat]Absence check using 7 positive place invariants in 5 ms returned sat [Nat]Absence check using 7 positive and 21 generalized place invariants in 12 ms returned sat After 808ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :16 State equation strengthened by 190 read => feed constraints. After 830ms SMT Verify possible using 190 Read/Feed constraints in natural domain returned unsat :0 sat :16 After 1795ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :16 found. After 3657ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :16 different solutions. in 194 ms. places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 169/169 places, 670/670 transitions. ms. Remains 169 /169 variables (removed 0) and now considering 670/670 (removed 0) transitions. in REACHABILITY mode , in 1 iterations and 30 ms. Remains : 169/169 places, 670/670 transitions. steps, including 143 resets, run finished after 512 ms. (steps per millisecond=19 ) properties (out of 16) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 16) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 16) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 16) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 16) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 16) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 16) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 16) seen :1 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 15) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=73 ) properties seen :{} steps, saw 44864 distinct states, run finished after 3001 ms. (steps per millisecond=73 ) properties seen :0 Flow matrix only has 292 transitions (discarded 378 similar events) Invariant cache hit. [Real]Absence check using 7 positive place invariants in 3 ms returned sat [Real]Absence check using 7 positive and 21 generalized place invariants in 8 ms returned sat After 668ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:15 [Nat]Absence check using 7 positive place invariants in 5 ms returned sat [Nat]Absence check using 7 positive and 21 generalized place invariants in 10 ms returned sat After 619ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15 State equation strengthened by 190 read => feed constraints. After 789ms SMT Verify possible using 190 Read/Feed constraints in natural domain returned unsat :0 sat :15 After 1695ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :15 found. After 3249ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :15 different solutions. in 202 ms. places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 169/169 places, 670/670 transitions. 169 vertex of which 3 / 169 are part of one of the 1 SCC in 2 ms 11 transitions. ms. Remains 167 /169 variables (removed 2) and now considering 659/670 (removed 11) transitions. in REACHABILITY mode , in 1 iterations and 30 ms. Remains : 167/169 places, 659/670 transitions. steps, including 142 resets, run finished after 431 ms. (steps per millisecond=23 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 5 ms. (steps per millisecond=200 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 15) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=73 ) properties seen :{} steps, saw 44669 distinct states, run finished after 3001 ms. (steps per millisecond=73 ) properties seen :0 Flow matrix only has 281 transitions (discarded 378 similar events) Computed 28 place invariants in 3 ms [Real]Absence check using 7 positive place invariants in 4 ms returned sat [Real]Absence check using 7 positive and 21 generalized place invariants in 12 ms returned sat After 1003ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:15 [Nat]Absence check using 7 positive place invariants in 5 ms returned sat [Nat]Absence check using 7 positive and 21 generalized place invariants in 13 ms returned sat After 720ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15 State equation strengthened by 183 read => feed constraints. After 764ms SMT Verify possible using 183 Read/Feed constraints in natural domain returned unsat :0 sat :15 After 1669ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :15 found. After 3350ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :15 different solutions. in 169 ms. places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 167/167 places, 659/659 transitions. ms. Remains 167 /167 variables (removed 0) and now considering 659/659 (removed 0) transitions. in REACHABILITY mode , in 1 iterations and 26 ms. Remains : 167/167 places, 659/659 transitions. in REACHABILITY mode, iteration 0 : 167/167 places, 659/659 transitions. ms. Remains 167 /167 variables (removed 0) and now considering 659/659 (removed 0) transitions. Flow matrix only has 281 transitions (discarded 378 similar events) Invariant cache hit. Implicit Places using invariants in 172 ms returned [] Flow matrix only has 281 transitions (discarded 378 similar events) Invariant cache hit. State equation strengthened by 183 read => feed constraints. Implicit Places using invariants and state equation in 605 ms returned [] with State Equation took 781 ms to find 0 implicit places. Redundant transitions in 109 ms returned [] Flow matrix only has 281 transitions (discarded 378 similar events) Invariant cache hit. Dead Transitions using invariants and state equation in 825 ms found 0 transitions. in REACHABILITY mode , in 1 iterations and 1752 ms. Remains : 167/167 places, 659/659 transitions. 167 vertex of which 33 / 167 are part of one of the 7 SCC in 1 ms transitions 414 transitions. 31 transitions Transition count delta: 31 33 rules applied. Total rules applied 34 place count 139 transition count 214 and 0 transitions. using F-continuation condition.Transition count delta: 3 34 rules applied. Total rules applied 68 place count 108 transition count 211 and 0 transitions. 3 rules applied. Total rules applied 71 place count 105 transition count 211 using Quasi-Persistent + Divergent Free condition.. 11 Pre rules applied. Total rules applied 71 place count 105 transition count 200 places in 0 ms and 0 transitions. 22 rules applied. Total rules applied 93 place count 94 transition count 200 with 6 rule applications. Total rules 99 place count 88 transition count 194 6 rules applied. Total rules applied 105 place count 88 transition count 194 with 4 rule applications. Total rules 109 place count 84 transition count 166 4 rules applied. Total rules applied 113 place count 84 transition count 166 s 12 transitions. 12 rules applied. Total rules applied 125 place count 84 transition count 154 using F-continuation condition.Transition count delta: 2 places in 0 ms and 0 transitions. 4 rules applied. Total rules applied 129 place count 82 transition count 152 using F-continuation condition.Transition count delta: -24 places in 0 ms and 0 transitions. 6 rules applied. Total rules applied 135 place count 79 transition count 176 rules discarded 39 transitions 39 rules applied. Total rules applied 174 place count 79 transition count 137 using F-continuation condition.Transition count delta: 1 1 rules applied. Total rules applied 175 place count 79 transition count 136 and 0 transitions. 1 rules applied. Total rules applied 176 place count 78 transition count 136 using F-continuation condition.Transition count delta: -18 places in 0 ms and 0 transitions. 4 rules applied. Total rules applied 180 place count 76 transition count 154 3 times. 3 rules applied. Total rules applied 183 place count 76 transition count 151 and 0 transitions. 3 rules applied. Total rules applied 186 place count 73 transition count 151 rules discarded 1 transitions 1 rules applied. Total rules applied 187 place count 73 transition count 150 using F-continuation condition.Transition count delta: 1 places in 0 ms and 0 transitions. 2 rules applied. Total rules applied 189 place count 72 transition count 149 applied 1 times. 1 rules applied. Total rules applied 190 place count 72 transition count 149 applied 1 times. 1 rules applied. Total rules applied 191 place count 72 transition count 149 39 ms. Remains 72 /167 variables (removed 95) and now considering 149/659 (removed 510) transitions. Flow matrix only has 139 transitions (discarded 10 similar events) Computed 26 place invariants in 1 ms [Real]Absence check using 7 positive place invariants in 2 ms returned sat [Real]Absence check using 7 positive and 19 generalized place invariants in 5 ms returned sat After 153ms SMT Verify possible using state equation in real domain returned unsat :0 sat :3 real:12 State equation strengthened by 10 read => feed constraints. After 27ms SMT Verify possible using 10 Read/Feed constraints in real domain returned unsat :0 sat :0 real:15 After 288ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:15 [Nat]Absence check using 7 positive place invariants in 3 ms returned sat [Nat]Absence check using 7 positive and 19 generalized place invariants in 6 ms returned sat After 255ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :15 After 201ms SMT Verify possible using 10 Read/Feed constraints in natural domain returned unsat :0 sat :15 After 474ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :15 found. After 1040ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :15 propositions for a total of 16 simplifications. 1 formulas. TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE ] Flatten gal took : 95 ms Flatten gal took : 93 ms Input system was already deterministic with 908 transitions. places and 670 stable transitions and 236 vertex of which 235 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.15 ms in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 15 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 73 ms Flatten gal took : 60 ms Input system was already deterministic with 907 transitions. in SI_CTL mode, iteration 0 : 236/236 places, 908/908 transitions. 236 vertex of which 70 / 236 are part of one of the 21 SCC in 1 ms transitions 147 transitions. with 8 rule applications. Total rules 9 place count 179 transition count 697 8 rules applied. Total rules applied 17 place count 179 transition count 697 rules discarded 28 transitions 28 rules applied. Total rules applied 45 place count 179 transition count 669 7 transitions Transition count delta: 7 7 rules applied. Total rules applied 52 place count 179 transition count 662 and 0 transitions. 7 rules applied. Total rules applied 59 place count 172 transition count 662 using F-continuation condition.Transition count delta: 7 places in 0 ms and 0 transitions. 14 rules applied. Total rules applied 73 place count 165 transition count 655 98 ms. Remains 165 /236 variables (removed 71) and now considering 655/908 (removed 253) transitions. in SI_CTL mode , in 1 iterations and 99 ms. Remains : 165/236 places, 655/908 transitions. Flatten gal took : 27 ms Flatten gal took : 30 ms Input system was already deterministic with 655 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 9 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 37 ms Flatten gal took : 40 ms Input system was already deterministic with 907 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 9 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 37 ms Flatten gal took : 42 ms Input system was already deterministic with 907 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 9 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 36 ms Flatten gal took : 39 ms Input system was already deterministic with 907 transitions. in SI_CTL mode, iteration 0 : 236/236 places, 908/908 transitions. 236 vertex of which 70 / 236 are part of one of the 21 SCC in 1 ms transitions 147 transitions. with 8 rule applications. Total rules 9 place count 179 transition count 697 8 rules applied. Total rules applied 17 place count 179 transition count 697 rules discarded 25 transitions 25 rules applied. Total rules applied 42 place count 179 transition count 672 5 transitions Transition count delta: 5 5 rules applied. Total rules applied 47 place count 179 transition count 667 and 0 transitions. 5 rules applied. Total rules applied 52 place count 174 transition count 667 using F-continuation condition.Transition count delta: 7 places in 1 ms and 0 transitions. 14 rules applied. Total rules applied 66 place count 167 transition count 660 applied 1 times. 1 rules applied. Total rules applied 67 place count 167 transition count 660 106 ms. Remains 167 /236 variables (removed 69) and now considering 660/908 (removed 248) transitions. in SI_CTL mode , in 1 iterations and 107 ms. Remains : 167/236 places, 660/908 transitions. Flatten gal took : 27 ms Flatten gal took : 29 ms Input system was already deterministic with 660 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 10 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 34 ms Flatten gal took : 40 ms Input system was already deterministic with 907 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 9 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 35 ms Flatten gal took : 38 ms Input system was already deterministic with 907 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. ms. Remains 236 /236 variables (removed 0) and now considering 908/908 (removed 0) transitions. in LTL mode , in 1 iterations and 6 ms. Remains : 236/236 places, 908/908 transitions. Flatten gal took : 36 ms Flatten gal took : 40 ms Input system was already deterministic with 908 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 9 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 36 ms Flatten gal took : 39 ms Input system was already deterministic with 907 transitions. in SI_CTL mode, iteration 0 : 236/236 places, 908/908 transitions. 236 vertex of which 70 / 236 are part of one of the 21 SCC in 1 ms transitions 147 transitions. with 8 rule applications. Total rules 9 place count 179 transition count 697 8 rules applied. Total rules applied 17 place count 179 transition count 697 rules discarded 28 transitions 28 rules applied. Total rules applied 45 place count 179 transition count 669 7 transitions Transition count delta: 7 7 rules applied. Total rules applied 52 place count 179 transition count 662 and 0 transitions. 7 rules applied. Total rules applied 59 place count 172 transition count 662 using F-continuation condition.Transition count delta: 7 places in 0 ms and 0 transitions. 14 rules applied. Total rules applied 73 place count 165 transition count 655 63 ms. Remains 165 /236 variables (removed 71) and now considering 655/908 (removed 253) transitions. in SI_CTL mode , in 1 iterations and 64 ms. Remains : 165/236 places, 655/908 transitions. Flatten gal took : 26 ms Flatten gal took : 28 ms Input system was already deterministic with 655 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 10 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 34 ms Flatten gal took : 38 ms Input system was already deterministic with 907 transitions. in LTL mode, iteration 0 : 236/236 places, 908/908 transitions. with 1 rule applications. Total rules 1 place count 235 transition count 907 1 rules applied. Total rules applied 2 place count 235 transition count 907 ms. Remains 235 /236 variables (removed 1) and now considering 907/908 (removed 1) transitions. in LTL mode , in 1 iterations and 7 ms. Remains : 235/236 places, 907/908 transitions. Flatten gal took : 35 ms Flatten gal took : 38 ms Input system was already deterministic with 907 transitions. in SI_CTL mode, iteration 0 : 236/236 places, 908/908 transitions. 236 vertex of which 64 / 236 are part of one of the 20 SCC in 1 ms transitions 129 transitions. with 7 rule applications. Total rules 8 place count 185 transition count 724 7 rules applied. Total rules applied 15 place count 185 transition count 724 rules discarded 29 transitions 29 rules applied. Total rules applied 44 place count 185 transition count 695 6 transitions Transition count delta: 6 6 rules applied. Total rules applied 50 place count 185 transition count 689 and 0 transitions. 6 rules applied. Total rules applied 56 place count 179 transition count 689 using F-continuation condition.Transition count delta: 9 places in 0 ms and 0 transitions. 18 rules applied. Total rules applied 74 place count 170 transition count 680 76 ms. Remains 170 /236 variables (removed 66) and now considering 680/908 (removed 228) transitions. in SI_CTL mode , in 1 iterations and 77 ms. Remains : 170/236 places, 680/908 transitions. Flatten gal took : 26 ms Flatten gal took : 32 ms Input system was already deterministic with 680 transitions. in SI_CTL mode, iteration 0 : 236/236 places, 908/908 transitions. 236 vertex of which 67 / 236 are part of one of the 21 SCC in 1 ms transitions 140 transitions. with 8 rule applications. Total rules 9 place count 182 transition count 704 8 rules applied. Total rules applied 17 place count 182 transition count 704 rules discarded 26 transitions 26 rules applied. Total rules applied 43 place count 182 transition count 678 6 transitions Transition count delta: 6 6 rules applied. Total rules applied 49 place count 182 transition count 672 and 0 transitions. 6 rules applied. Total rules applied 55 place count 176 transition count 672 using F-continuation condition.Transition count delta: 7 places in 0 ms and 0 transitions. 14 rules applied. Total rules applied 69 place count 169 transition count 665 61 ms. Remains 169 /236 variables (removed 67) and now considering 665/908 (removed 243) transitions. in SI_CTL mode , in 1 iterations and 62 ms. Remains : 169/236 places, 665/908 transitions. Flatten gal took : 24 ms Flatten gal took : 28 ms Input system was already deterministic with 665 transitions. Flatten gal took : 39 ms Flatten gal took : 37 ms Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 7 ms. Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 236 places, 908 transitions and 6295 arcs took 8 ms. ITS could not solve within timeout ./reducer/bin//../../lola/bin/ 74 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT after 3600 seconds tstools/pylibs /pylibs Kit/itstools/pylibs: tools/pylibs: /bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar //../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML tion/374/model.pnml net ion/374/model.pnml xecution/374/CTLFireability.xml rewrite.k:550 rewrite.k:478 rewrite.k:250 rewrite.k:250 rewrite.k:322 rewrite.k:331 rewrite.k:296 rewrite.k:322 rewrite.k:337 rewrite.k:317 rewrite.k:322 rewrite.k:331 rewrite.k:296 rewrite.k:296 rewrite.k:296 rewrite.k:322 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:325 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:469 rewrite.k:322 rewrite.k:331 rewrite.k:296 rewrite.k:250 rewrite.k:253 rewrite.k:472 rewrite.k:314 rewrite.k:322 rewrite.k:331 rewrite.k:296 rewrite.k:322 rewrite.k:331 rewrite.k:296 rewrite.k:451 rewrite.k:325 rewrite.k:331 rewrite.k:296 rewrite.k:478 rewrite.k:314 rewrite.k:317 rewrite.k:325 rewrite.k:334 rewrite.k:296 rewrite.k:325 rewrite.k:331 rewrite.k:296 rewrite.k:322 rewrite.k:331 rewrite.k:296 rewrite.k:322 rewrite.k:337 rewrite.k:296 rewrite.k:317 rewrite.k:314 rewrite.k:322 rewrite.k:334 rewrite.k:299 rewrite.k:322 rewrite.k:328 rewrite.k:299 rewrite.k:325 rewrite.k:328 rewrite.k:299 rewrite.k:322 rewrite.k:337 rewrite.k:317 rewrite.k:325 rewrite.k:337 rewrite.k:296 rewrite.k:322 rewrite.k:328 rewrite.k:296 rewrite.k:322 rewrite.k:328 rewrite.k:317 rewrite.k:322 rewrite.k:334 rewrite.k:296 rewrite.k:296 rewrite.k:314 rewrite.k:296 rewrite.k:325 rewrite.k:331 rewrite.k:296 rewrite.k:325 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:314 rewrite.k:322 rewrite.k:331 rewrite.k:296 rewrite.k:325 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:322 rewrite.k:337 rewrite.k:317 rewrite.k:325 rewrite.k:328 rewrite.k:299 rewrite.k:322 rewrite.k:340 rewrite.k:299 rewrite.k:299 rewrite.k:296 rewrite.k:98 rewrite.k:129 rewrite.k:322 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:253 rewrite.k:325 rewrite.k:334 rewrite.k:296 rewrite.k:250 rewrite.k:325 rewrite.k:331 rewrite.k:296 rewrite.k:322 rewrite.k:337 rewrite.k:325 rewrite.k:328 rewrite.k:296 rewrite.k:322 rewrite.k:328 rewrite.k:296 secs. secs. secs. secs. places removed secs. secs. secs. secs. CNST) for 31 CloudDeployment-PT-7a-CTLFireability-10 CNST) for CloudDeployment-PT-7a-CTLFireability-10 secs. secs. secs. secs. secs. rewrite.k:814 rewrite.k:808 for 3 CloudDeployment-PT-7a-CTLFireability-02 EXCL) for CloudDeployment-PT-7a-CTLFireability-02 2 5 0.000000 1 secs. secs. rewrite.k:811 rewrite.k:811 rewrite.k:811 rewrite.k:813 rewrite.k:811 rewrite.k:809 rewrite.k:808 rewrite.k:808 rewrite.k:813 rewrite.k:806 rewrite.k:815 rewrite.k:807 rewrite.k:811 rewrite.k:809 rewrite.k:814 rewrite.k:814 rewrite.k:811 rewrite.k:809 rewrite.k:810 EXCL) for 43 CloudDeployment-PT-7a-CTLFireability-14 rewrite.k:730 rewrite.k:813 rewrite.k:811 rewrite.k:808 rewrite.k:806 rewrite.k:808 rewrite.k:813 rewrite.k:813 rewrite.k:809 EXCL) for CloudDeployment-PT-7a-CTLFireability-14 2 8 0.000000 1 EXCL) for 28 CloudDeployment-PT-7a-CTLFireability-09 rewrite.k:806 rewrite.k:815 rewrite.k:807 rewrite.k:806 rewrite.k:813 rewrite.k:810 rewrite.k:813 rewrite.k:810 rewrite.k:807 rewrite.k:808 rewrite.k:811 rewrite.k:808 rewrite.k:810 rewrite.k:811 rewrite.k:810 rewrite.k:811 rewrite.k:813 rewrite.k:809 rewrite.k:812 rewrite.k:813 rewrite.k:808 rewrite.k:811 rewrite.k:807 rewrite.k:807 rewrite.k:807 rewrite.k:806 rewrite.k:807 rewrite.k:809 rewrite.k:813 rewrite.k:811 rewrite.k:811 rewrite.k:812 rewrite.k:806 rewrite.k:814 rewrite.k:814 rewrite.k:814 rewrite.k:814 rewrite.k:809 rewrite.k:808 rewrite.k:812 rewrite.k:806 rewrite.k:812 rewrite.k:811 rewrite.k:807 rewrite.k:806 rewrite.k:811 rewrite.k:810 rewrite.k:809 rewrite.k:813 rewrite.k:809 rewrite.k:811 rewrite.k:806 rewrite.k:810 rewrite.k:814 rewrite.k:809 rewrite.k:806 rewrite.k:812 rewrite.k:813 rewrite.k:811 rewrite.k:811 rewrite.k:808 rewrite.k:814 rewrite.k:811 rewrite.k:812 rewrite.k:812 rewrite.k:808 rewrite.k:814 rewrite.k:809 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 CloudDeployment-PT-7a-CTLFireability-09 149017 m, 29803 m/sec, 2368276 t fired, . in use: 1 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 CloudDeployment-PT-7a-CTLFireability-09 318163 m, 33829 m/sec, 5177004 t fired, . in use: 2 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 CloudDeployment-PT-7a-CTLFireability-09 477844 m, 31936 m/sec, 7915657 t fired, . in use: 3 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 CloudDeployment-PT-7a-CTLFireability-09 635749 m, 31581 m/sec, 10782378 t fired, . in use: 3 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 CloudDeployment-PT-7a-CTLFireability-09 790277 m, 30905 m/sec, 13585733 t fired, . in use: 4 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 CloudDeployment-PT-7a-CTLFireability-09 948196 m, 31583 m/sec, 16371184 t fired, . in use: 5 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 CloudDeployment-PT-7a-CTLFireability-09 1110746 m, 32510 m/sec, 19177950 t fired, . in use: 6 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 CloudDeployment-PT-7a-CTLFireability-09 1266103 m, 31071 m/sec, 22044362 t fired, . in use: 7 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 CloudDeployment-PT-7a-CTLFireability-09 1418239 m, 30427 m/sec, 24799800 t fired, . in use: 7 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 CloudDeployment-PT-7a-CTLFireability-09 1576217 m, 31595 m/sec, 27506564 t fired, . in use: 8 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-7a-CTLFireability-09 1712771 m, 27310 m/sec, 30062754 t fired, . in use: 9 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 CloudDeployment-PT-7a-CTLFireability-09 1863676 m, 30181 m/sec, 32770679 t fired, . in use: 10 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 CloudDeployment-PT-7a-CTLFireability-09 2016992 m, 30663 m/sec, 35529675 t fired, . in use: 10 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 CloudDeployment-PT-7a-CTLFireability-09 2171429 m, 30887 m/sec, 38309715 t fired, . in use: 11 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-7a-CTLFireability-09 2325776 m, 30869 m/sec, 41099512 t fired, . in use: 12 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 CloudDeployment-PT-7a-CTLFireability-09 2472816 m, 29408 m/sec, 43743406 t fired, . in use: 13 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 CloudDeployment-PT-7a-CTLFireability-09 2622871 m, 30011 m/sec, 46449886 t fired, . in use: 13 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 CloudDeployment-PT-7a-CTLFireability-09 2781910 m, 31807 m/sec, 49179083 t fired, . in use: 14 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-7a-CTLFireability-09 2931881 m, 29994 m/sec, 51866360 t fired, . in use: 15 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 CloudDeployment-PT-7a-CTLFireability-09 3086623 m, 30948 m/sec, 54651058 t fired, . in use: 16 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 CloudDeployment-PT-7a-CTLFireability-09 3231266 m, 28928 m/sec, 57383847 t fired, . in use: 16 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-7a-CTLFireability-09 3385504 m, 30847 m/sec, 60159284 t fired, . in use: 17 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 CloudDeployment-PT-7a-CTLFireability-09 3536247 m, 30148 m/sec, 62844707 t fired, . in use: 18 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-7a-CTLFireability-09 3694894 m, 31729 m/sec, 65521257 t fired, . in use: 19 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-7a-CTLFireability-09 3847697 m, 30560 m/sec, 68348313 t fired, . in use: 19 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-7a-CTLFireability-09 4001477 m, 30756 m/sec, 71103156 t fired, . in use: 20 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-7a-CTLFireability-09 4153911 m, 30486 m/sec, 73753734 t fired, . in use: 20 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 CloudDeployment-PT-7a-CTLFireability-09 4297992 m, 28816 m/sec, 76424937 t fired, . in use: 21 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 CloudDeployment-PT-7a-CTLFireability-09 4446855 m, 29772 m/sec, 79097794 t fired, . in use: 22 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 CloudDeployment-PT-7a-CTLFireability-09 4598890 m, 30407 m/sec, 81827124 t fired, . in use: 22 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-7a-CTLFireability-09 4747095 m, 29641 m/sec, 84495836 t fired, . in use: 23 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-7a-CTLFireability-09 4890992 m, 28779 m/sec, 87115673 t fired, . in use: 24 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-7a-CTLFireability-09 5036048 m, 29011 m/sec, 89680909 t fired, . in use: 24 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 CloudDeployment-PT-7a-CTLFireability-09 5185595 m, 29909 m/sec, 92338994 t fired, . in use: 25 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-7a-CTLFireability-09 5333364 m, 29553 m/sec, 95089529 t fired, . in use: 26 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-7a-CTLFireability-09 5497036 m, 32734 m/sec, 97854041 t fired, . in use: 26 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 CloudDeployment-PT-7a-CTLFireability-09 5657702 m, 32133 m/sec, 100560046 t fired, . in use: 27 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 CloudDeployment-PT-7a-CTLFireability-09 5802512 m, 28962 m/sec, 103276245 t fired, . in use: 28 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 CloudDeployment-PT-7a-CTLFireability-09 5948674 m, 29232 m/sec, 105905480 t fired, . in use: 29 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 CloudDeployment-PT-7a-CTLFireability-09 6100539 m, 30373 m/sec, 108647677 t fired, . in use: 29 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 CloudDeployment-PT-7a-CTLFireability-09 6248895 m, 29671 m/sec, 111330479 t fired, . in use: 30 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 CloudDeployment-PT-7a-CTLFireability-09 6398818 m, 29984 m/sec, 113985963 t fired, . in use: 31 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-7a-CTLFireability-09 6542817 m, 28799 m/sec, 116616560 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-7a-CTLFireability-09 6690301 m, 29496 m/sec, 119237959 t fired, . in use: 32 EXCL) for CloudDeployment-PT-7a-CTLFireability-09 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 EXCL) for 40 CloudDeployment-PT-7a-CTLFireability-13 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 CloudDeployment-PT-7a-CTLFireability-13 167363 m, 33472 m/sec, 2170512 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 CloudDeployment-PT-7a-CTLFireability-13 332319 m, 32991 m/sec, 4433938 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 CloudDeployment-PT-7a-CTLFireability-13 493336 m, 32203 m/sec, 6669658 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 CloudDeployment-PT-7a-CTLFireability-13 646970 m, 30726 m/sec, 9012029 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 CloudDeployment-PT-7a-CTLFireability-13 797588 m, 30123 m/sec, 11339133 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 CloudDeployment-PT-7a-CTLFireability-13 948067 m, 30095 m/sec, 13594645 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 CloudDeployment-PT-7a-CTLFireability-13 1104170 m, 31220 m/sec, 15874113 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 CloudDeployment-PT-7a-CTLFireability-13 1257955 m, 30757 m/sec, 18206090 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 CloudDeployment-PT-7a-CTLFireability-13 1406867 m, 29782 m/sec, 20442993 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 CloudDeployment-PT-7a-CTLFireability-13 1560349 m, 30696 m/sec, 22699008 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-7a-CTLFireability-13 1697332 m, 27396 m/sec, 24761031 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-7a-CTLFireability-13 1843338 m, 29201 m/sec, 26943621 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 CloudDeployment-PT-7a-CTLFireability-13 1991825 m, 29697 m/sec, 29190867 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 CloudDeployment-PT-7a-CTLFireability-13 2143365 m, 30308 m/sec, 31475685 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-7a-CTLFireability-13 2295638 m, 30454 m/sec, 33753247 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-7a-CTLFireability-13 2437964 m, 28465 m/sec, 35898379 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 CloudDeployment-PT-7a-CTLFireability-13 2586776 m, 29762 m/sec, 38138064 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 CloudDeployment-PT-7a-CTLFireability-13 2741261 m, 30897 m/sec, 40369127 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-7a-CTLFireability-13 2891421 m, 30032 m/sec, 42575550 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-7a-CTLFireability-13 3041455 m, 30006 m/sec, 44828380 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 CloudDeployment-PT-7a-CTLFireability-13 3182346 m, 28178 m/sec, 47049024 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-7a-CTLFireability-13 3329594 m, 29449 m/sec, 49297693 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 CloudDeployment-PT-7a-CTLFireability-13 3475406 m, 29162 m/sec, 51483816 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 CloudDeployment-PT-7a-CTLFireability-13 3635539 m, 32026 m/sec, 53676845 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-7a-CTLFireability-13 3782166 m, 29325 m/sec, 55940499 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-7a-CTLFireability-13 3929056 m, 29378 m/sec, 58177191 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-7a-CTLFireability-13 4081975 m, 30583 m/sec, 60390730 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 CloudDeployment-PT-7a-CTLFireability-13 4225795 m, 28764 m/sec, 62565638 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 CloudDeployment-PT-7a-CTLFireability-13 4366165 m, 28074 m/sec, 64702891 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 CloudDeployment-PT-7a-CTLFireability-13 4517680 m, 30303 m/sec, 66965488 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-7a-CTLFireability-13 4672122 m, 30888 m/sec, 69296619 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-7a-CTLFireability-13 4822968 m, 30169 m/sec, 71566060 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-7a-CTLFireability-13 4969578 m, 29322 m/sec, 73774290 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 CloudDeployment-PT-7a-CTLFireability-13 5118672 m, 29818 m/sec, 75925471 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 CloudDeployment-PT-7a-CTLFireability-13 5264839 m, 29233 m/sec, 78139502 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-7a-CTLFireability-13 5408402 m, 28712 m/sec, 80366675 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 CloudDeployment-PT-7a-CTLFireability-13 5559223 m, 30164 m/sec, 82584861 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 CloudDeployment-PT-7a-CTLFireability-13 5710941 m, 30343 m/sec, 84831241 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 CloudDeployment-PT-7a-CTLFireability-13 5852524 m, 28316 m/sec, 86954695 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 CloudDeployment-PT-7a-CTLFireability-13 6001753 m, 29845 m/sec, 89178011 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 CloudDeployment-PT-7a-CTLFireability-13 6148299 m, 29309 m/sec, 91396997 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 CloudDeployment-PT-7a-CTLFireability-13 6296472 m, 29634 m/sec, 93594285 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 CloudDeployment-PT-7a-CTLFireability-13 6438533 m, 28412 m/sec, 95758171 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-7a-CTLFireability-13 6585482 m, 29389 m/sec, 97922392 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-7a-CTLFireability-13 6726160 m, 28135 m/sec, 100059087 t fired, . in use: 32 EXCL) for CloudDeployment-PT-7a-CTLFireability-13 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker true preprocessing CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 EXCL) for 37 CloudDeployment-PT-7a-CTLFireability-12 EXCL) for CloudDeployment-PT-7a-CTLFireability-12 717 7013 0.000000 1 EXCL) for 25 CloudDeployment-PT-7a-CTLFireability-08 EXCL) for CloudDeployment-PT-7a-CTLFireability-08 2561 31031 0.000000 1 EXCL) for 22 CloudDeployment-PT-7a-CTLFireability-07 EXCL) for CloudDeployment-PT-7a-CTLFireability-07 1371 18385 0.000000 1 EXCL) for 12 CloudDeployment-PT-7a-CTLFireability-05 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 CloudDeployment-PT-7a-CTLFireability-05 208106 m, 41621 m/sec, 2700290 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 CloudDeployment-PT-7a-CTLFireability-05 420096 m, 42398 m/sec, 5582676 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 CloudDeployment-PT-7a-CTLFireability-05 604283 m, 36837 m/sec, 8442309 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 CloudDeployment-PT-7a-CTLFireability-05 795246 m, 38192 m/sec, 11299437 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 CloudDeployment-PT-7a-CTLFireability-05 986165 m, 38183 m/sec, 14159147 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 CloudDeployment-PT-7a-CTLFireability-05 1192308 m, 41228 m/sec, 17103517 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 CloudDeployment-PT-7a-CTLFireability-05 1376115 m, 36761 m/sec, 19963514 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 CloudDeployment-PT-7a-CTLFireability-05 1567198 m, 38216 m/sec, 22752371 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-7a-CTLFireability-05 1733854 m, 33331 m/sec, 25324526 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 CloudDeployment-PT-7a-CTLFireability-05 1925194 m, 38268 m/sec, 28179503 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 CloudDeployment-PT-7a-CTLFireability-05 2111633 m, 37287 m/sec, 30985786 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-7a-CTLFireability-05 2303092 m, 38291 m/sec, 33866499 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 CloudDeployment-PT-7a-CTLFireability-05 2484840 m, 36349 m/sec, 36596851 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 CloudDeployment-PT-7a-CTLFireability-05 2668910 m, 36814 m/sec, 39353527 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-7a-CTLFireability-05 2862385 m, 38695 m/sec, 42137834 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-7a-CTLFireability-05 3049742 m, 37471 m/sec, 44953149 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 CloudDeployment-PT-7a-CTLFireability-05 3223711 m, 34793 m/sec, 47711854 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-7a-CTLFireability-05 3409187 m, 37095 m/sec, 50496098 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 CloudDeployment-PT-7a-CTLFireability-05 3599439 m, 38050 m/sec, 53264635 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-7a-CTLFireability-05 3791935 m, 38499 m/sec, 56102684 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-7a-CTLFireability-05 3981702 m, 37953 m/sec, 58946813 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 CloudDeployment-PT-7a-CTLFireability-05 4168014 m, 37262 m/sec, 61688381 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 CloudDeployment-PT-7a-CTLFireability-05 4345470 m, 35491 m/sec, 64395062 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 CloudDeployment-PT-7a-CTLFireability-05 4535392 m, 37984 m/sec, 67229949 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-7a-CTLFireability-05 4716729 m, 36267 m/sec, 69972800 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-7a-CTLFireability-05 4894997 m, 35653 m/sec, 72644417 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-7a-CTLFireability-05 5074844 m, 35969 m/sec, 75269315 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 CloudDeployment-PT-7a-CTLFireability-05 5257722 m, 36575 m/sec, 78019341 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-7a-CTLFireability-05 5439220 m, 36299 m/sec, 80829663 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 CloudDeployment-PT-7a-CTLFireability-05 5630372 m, 38230 m/sec, 83627616 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 CloudDeployment-PT-7a-CTLFireability-05 5815391 m, 37003 m/sec, 86393248 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 CloudDeployment-PT-7a-CTLFireability-05 5999036 m, 36729 m/sec, 89138904 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 CloudDeployment-PT-7a-CTLFireability-05 6183234 m, 36839 m/sec, 91917888 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 CloudDeployment-PT-7a-CTLFireability-05 6368003 m, 36953 m/sec, 94653337 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-7a-CTLFireability-05 6542803 m, 34960 m/sec, 97324075 t fired, . in use: 32 VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-7a-CTLFireability-05 6724238 m, 36287 m/sec, 100021982 t fired, . in use: 32 EXCL) for CloudDeployment-PT-7a-CTLFireability-05 (memory limit exceeded) VALUE PRODUCED BY CTL true CTL model checker CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 DISJ 0 2 0 0 2 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 EXCL) for 9 CloudDeployment-PT-7a-CTLFireability-04 EXCL) for CloudDeployment-PT-7a-CTLFireability-04 2 4 0.000000 1 for 6 CloudDeployment-PT-7a-CTLFireability-03 EXCL) for CloudDeployment-PT-7a-CTLFireability-03 115 679 0.000000 1 for 0 CloudDeployment-PT-7a-CTLFireability-01 EXCL) for CloudDeployment-PT-7a-CTLFireability-01 2 6 0.000000 1 EXCL) for 15 CloudDeployment-PT-7a-CTLFireability-06 EXCL) for CloudDeployment-PT-7a-CTLFireability-06 2 2 0.000000 1 EXCL) for 46 CloudDeployment-PT-7a-CTLFireability-15 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 CloudDeployment-PT-7a-CTLFireability-15 187321 m, 37464 m/sec, 3338936 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 CloudDeployment-PT-7a-CTLFireability-15 372036 m, 36943 m/sec, 6884827 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 CloudDeployment-PT-7a-CTLFireability-15 550466 m, 35686 m/sec, 10301499 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 CloudDeployment-PT-7a-CTLFireability-15 734467 m, 36800 m/sec, 13761648 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 CloudDeployment-PT-7a-CTLFireability-15 911109 m, 35328 m/sec, 17188294 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 CloudDeployment-PT-7a-CTLFireability-15 1091850 m, 36148 m/sec, 20604915 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 CloudDeployment-PT-7a-CTLFireability-15 1270810 m, 35792 m/sec, 24004212 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 CloudDeployment-PT-7a-CTLFireability-15 1449124 m, 35662 m/sec, 27431988 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 CloudDeployment-PT-7a-CTLFireability-15 1626227 m, 35420 m/sec, 30799907 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-7a-CTLFireability-15 1796206 m, 33995 m/sec, 34063087 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-7a-CTLFireability-15 1956438 m, 32046 m/sec, 37303500 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 CloudDeployment-PT-7a-CTLFireability-15 2125242 m, 33760 m/sec, 40700360 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 CloudDeployment-PT-7a-CTLFireability-15 2295399 m, 34031 m/sec, 44086085 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-7a-CTLFireability-15 2465330 m, 33986 m/sec, 47514416 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-7a-CTLFireability-15 2631487 m, 33231 m/sec, 50842780 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 CloudDeployment-PT-7a-CTLFireability-15 2786388 m, 30980 m/sec, 53953232 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 CloudDeployment-PT-7a-CTLFireability-15 2947869 m, 32296 m/sec, 57248366 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-7a-CTLFireability-15 3121939 m, 34814 m/sec, 60574238 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-7a-CTLFireability-15 3272683 m, 30148 m/sec, 63946595 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 CloudDeployment-PT-7a-CTLFireability-15 3438562 m, 33175 m/sec, 67454128 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-7a-CTLFireability-15 3600201 m, 32327 m/sec, 70832363 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-7a-CTLFireability-15 3756312 m, 31222 m/sec, 74177137 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 CloudDeployment-PT-7a-CTLFireability-15 3911528 m, 31043 m/sec, 77423289 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 CloudDeployment-PT-7a-CTLFireability-15 4067160 m, 31126 m/sec, 80737476 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-7a-CTLFireability-15 4219865 m, 30541 m/sec, 83939321 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-7a-CTLFireability-15 4376811 m, 31389 m/sec, 87217551 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-7a-CTLFireability-15 4542686 m, 33175 m/sec, 90724463 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 CloudDeployment-PT-7a-CTLFireability-15 4705470 m, 32556 m/sec, 94193142 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 CloudDeployment-PT-7a-CTLFireability-15 4860385 m, 30983 m/sec, 97460571 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-7a-CTLFireability-15 5018893 m, 31701 m/sec, 100802508 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-7a-CTLFireability-15 5179507 m, 32122 m/sec, 104099944 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-7a-CTLFireability-15 5343281 m, 32754 m/sec, 107395637 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 CloudDeployment-PT-7a-CTLFireability-15 5498082 m, 30960 m/sec, 110674958 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 CloudDeployment-PT-7a-CTLFireability-15 5659496 m, 32282 m/sec, 114075877 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-7a-CTLFireability-15 5815653 m, 31231 m/sec, 117391922 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 CloudDeployment-PT-7a-CTLFireability-15 5962991 m, 29467 m/sec, 120651759 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 CloudDeployment-PT-7a-CTLFireability-15 6125698 m, 32541 m/sec, 124104853 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 CloudDeployment-PT-7a-CTLFireability-15 6284425 m, 31745 m/sec, 127467119 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 CloudDeployment-PT-7a-CTLFireability-15 6439351 m, 30985 m/sec, 130736815 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 CloudDeployment-PT-7a-CTLFireability-15 6604925 m, 33114 m/sec, 134094080 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 CloudDeployment-PT-7a-CTLFireability-15 6772189 m, 33452 m/sec, 137456379 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 CloudDeployment-PT-7a-CTLFireability-15 6920664 m, 29695 m/sec, 140775837 t fired, . in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 1 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-7a-CTLFireability-15 7066964 m, 29260 m/sec, 143850689 t fired, . in use: 32 EXCL) for CloudDeployment-PT-7a-CTLFireability-15 (memory limit exceeded) VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 EXCL) for 34 CloudDeployment-PT-7a-CTLFireability-11 EXCL) for CloudDeployment-PT-7a-CTLFireability-11 2 10 0.000000 1 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker CTL false CTL model checker DISJ true state space /EFEG CTL true CTL model checker CTL true CTL model checker true preprocessing CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 truncated ====== if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CloudDeployment-PT-7a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is CloudDeployment-PT-7a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-smll-167814398000442"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CloudDeployment-PT-7a.tgz
mv CloudDeployment-PT-7a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;