MCC'2023- Execution of r071-smll-167814398000434

About the Execution of LoLa+red for CloudDeployment-PT-6b

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
3339.907	3600000.00	599748.00	9748.50	FTFFT?FTF?TTFFFT	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r071-s
Waiting for the VM to be ready
........................................
==================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is CloudDeployment-PT-6b,
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-smll-16781439
========================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 5.2M
-rw-r--r-- 1 mcc users 8.0K Feb
-rw-r--r-- 1 mcc users 85K Feb
-rw-r--r-- 1 mcc users 5.3K Feb
-rw-r--r-- 1 mcc users 46K Feb
-rw-r--r-- 1 mcc users 4.2K Jan
-rw-r--r-- 1 mcc users 6.8K Jan
-rw-r--r-- 1 mcc users 3.8K Feb
-rw-r--r-- 1 mcc users 27K Feb
-rw-r--r-- 1 mcc users 2.3K Feb
-rw-r--r-- 1 mcc users 18K Feb
-rw-r--r-- 1 mcc users 5.8K Feb
-rw-r--r-- 1 mcc users 47K Feb
-rw-r--r-- 1 mcc users 11K Feb
-rw-r--r-- 1 mcc users 90K Feb
-rw-r--r-- 1 mcc users 1.7K Feb
-rw-r--r-- 1 mcc users 3.7K Feb
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 3 Mar
-rw-r--r-- 1 mcc users 6 Mar
-rw-r--r-- 1 mcc users 4.8M Mar

--------------------
content from stdout:

=== Data for post analysis generated

The expected result is a vector
BOOL_VECTOR

here is the order used to build
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi
FORMULA_NAME CloudDeployment-PT-6b-CTLFi

=== Now, execution of the tool begins

BK_START 1678286238316

bash -c /home/mcc/BenchKit/BenchKit_head.sh
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CloudDeployment-PT-6b
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 14:37:20] [INFO ]
[2023-03-08 14:37:21] [INFO ]
[2023-03-08 14:37:21] [INFO ]
[2023-03-08 14:37:21] [INFO ]
[2023-03-08 14:37:22] [INFO ]
[2023-03-08 14:37:22] [INFO ]
[2023-03-08 14:37:22] [INFO ]
Parsed 16 properties from file
Support contains 99 out of 1888
Starting structural reductions
Reduce places removed 6 places
Iterating post reduction 0 with
Discarding 511 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Discarding 196 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 29 transition
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 17 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 2 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 1 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Applied a total of 1489 rules in
// Phase 1: matrix 6048 rows 1155 cols
[2023-03-08 14:37:23] [INFO ]
[2023-03-08 14:37:24] [INFO ]
[2023-03-08 14:37:24] [INFO ]
[2023-03-08 14:37:25] [INFO ]
Implicit Place search using SMT
[2023-03-08 14:37:25] [INFO ]
[2023-03-08 14:37:31] [INFO ]
Starting structural reductions
Finished structural reductions
Support contains 99 out of 1155
[2023-03-08 14:37:33] [INFO ]
[2023-03-08 14:37:34] [INFO ]
[2023-03-08 14:37:36] [INFO ]
Incomplete random walk after 10000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1000
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Incomplete Best-First random walk after 1001
Running SMT prover for 63 properties.
[2023-03-08 14:37:38] [INFO ]
[2023-03-08 14:37:42] [INFO ]
[2023-03-08 14:37:42] [INFO ]
[2023-03-08 14:37:43] [INFO ]
[2023-03-08 14:37:57] [INFO ]
[2023-03-08 14:38:05] [INFO ]
Attempting to minimize the solution
Minimization took 2148 ms.
[2023-03-08 14:38:07] [INFO ]
Fused 63 Parikh solutions to 21
Parikh walk visited 16 properties
Support contains 9 out of 1155
Starting structural reductions
Graph (trivial) has 1173 edges
Free SCC test removed 364 places
Drop transitions removed 4557 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Graph (complete) has 3179 edges
Discarding 33 places :
Also discarding 0 output transitions
Drop transitions removed 22 transitions
Reduce isomorphic transitions removed
Drop transitions removed 317 transitions
Trivial Post-agglo rules discarded
Performed 317 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 317 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Performed 2 Post agglomeration
Iterating post reduction 1 with
Reduce places removed 2 places
Iterating post reduction 2 with
Performed 67 Pre agglomeration
Pre-agglomeration after 3 with
Deduced a syphon composed of 67
Reduce places removed 67 places
Iterating global reduction 3 with
Discarding 13 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 9 Pre agglomeration using
Pre-agglomeration after 4 with
Deduced a syphon composed of 9
Reduce places removed 9 places
Iterating global reduction 4 with
Performed 98 Post agglomeration
Deduced a syphon composed of 98
Reduce places removed 98 places
Iterating global reduction 4 with
Performed 38 Post agglomeration
Deduced a syphon composed of 38
Reduce places removed 38 places
Iterating global reduction 4 with
Drop transitions removed 11 transitions
Ensure Unique test removed 37 transition
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Performed 6 Post agglomeration
Deduced a syphon composed of 6
Reduce places removed 6 places
Iterating global reduction 5 with
Drop transitions removed 150 transitions
Redundant transition composition
Iterating global reduction 5 with
Free-agglomeration rule applied
Iterating global reduction 5 with
Reduce places removed 55 places
Drop transitions removed 94 transitions
Ensure Unique test removed 76 transition
Reduce isomorphic transitions removed
Iterating post reduction 5 with
Discarding 7 places :
Symmetric choice reduction at 6
Iterating global reduction 6 with
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Iterating post reduction 6 with
Drop transitions removed 91 transitions
Redundant transition composition
Iterating global reduction 7 with
Partial Free-agglomeration rule
Drop transitions removed 1 transitions
Iterating global reduction 7 with
Applied a total of 1712 rules in
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Running SMT prover for 3 properties.
[2023-03-08 14:38:09] [INFO ]
// Phase 1: matrix 381 rows 146 cols
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:09] [INFO ]
[2023-03-08 14:38:10] [INFO ]
[2023-03-08 14:38:10] [INFO ]
[2023-03-08 14:38:10] [INFO ]
[2023-03-08 14:38:10] [INFO ]
[2023-03-08 14:38:10] [INFO ]
[2023-03-08 14:38:10] [INFO ]
Attempting to minimize the solution
Minimization took 74 ms.
[2023-03-08 14:38:10] [INFO ]
Parikh walk visited 0 properties
Support contains 7 out of 146 places.
Starting structural reductions
Graph (trivial) has 48 edges and
Free SCC test removed 1 places
Drop transitions removed 2 transitions
Reduce isomorphic transitions removed
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded
Performed 1 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 1 places
Iterating post reduction 1 with
Discarding 1 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Performed 1 Post agglomeration
Deduced a syphon composed of 1
Reduce places removed 1 places
Iterating global reduction 2 with
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Drop transitions removed 33 transitions
Redundant transition composition
Iterating global reduction 3 with
Applied a total of 44 rules in
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Running SMT prover for 2 properties.
[2023-03-08 14:38:11] [INFO ]
// Phase 1: matrix 342 rows 142 cols
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:11] [INFO ]
[2023-03-08 14:38:12] [INFO ]
[2023-03-08 14:38:12] [INFO ]
[2023-03-08 14:38:12] [INFO ]
[2023-03-08 14:38:12] [INFO ]
[2023-03-08 14:38:12] [INFO ]
Attempting to minimize the solution
Minimization took 100 ms.
[2023-03-08 14:38:12] [INFO ]
Parikh walk visited 0 properties
Support contains 6 out of 142 places.
Starting structural reductions
Performed 1 Post agglomeration
Deduced a syphon composed of 1
Reduce places removed 1 places
Iterating global reduction 0 with
Applied a total of 2 rules in 29
Finished structural reductions
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Incomplete Best-First random walk after 10001
Interrupted probabilistic random walk after 532859
Probabilistic random walk after 532859
Running SMT prover for 2 properties.
[2023-03-08 14:38:15] [INFO ]
// Phase 1: matrix 341 rows 141 cols
[2023-03-08 14:38:15] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
Attempting to minimize the solution
Minimization took 52 ms.
[2023-03-08 14:38:16] [INFO ]
Parikh walk visited 0 properties
Support contains 6 out of 141 places.
Starting structural reductions
Applied a total of 0 rules in 15
Finished structural reductions
Starting structural reductions
Applied a total of 0 rules in 14
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:16] [INFO ]
[2023-03-08 14:38:17] [INFO ]
[2023-03-08 14:38:17] [INFO ]
Implicit Place search using SMT
[2023-03-08 14:38:17] [INFO ]
[2023-03-08 14:38:17] [INFO ]
[2023-03-08 14:38:17] [INFO ]
[2023-03-08 14:38:18] [INFO ]
Finished structural reductions
Graph (trivial) has 126 edges and
Free SCC test removed 34 places
Drop transitions removed 53 transitions
Ensure Unique test removed 295
Reduce isomorphic transitions removed
Ensure Unique test removed 9 places
Drop transitions removed 11 transitions
Trivial Post-agglo rules discarded
Performed 11 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 11 places
Performed 1 Post agglomeration
Iterating post reduction 1 with
Reduce places removed 1 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Performed 10 Pre agglomeration
Pre-agglomeration after 3 with
Deduced a syphon composed of 10
Reduce places removed 10 places
Iterating global reduction 3 with
Discarding 4 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Discarding 4 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Discarding 4 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 68 transition
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 7 Post agglomeration
Deduced a syphon composed of 7
Reduce places removed 7 places
Iterating global reduction 4 with
Ensure Unique test removed 10 transition
Reduce isomorphic transitions removed
Iterating post reduction 4 with
Performed 5 Post agglomeration
Deduced a syphon composed of 5
Reduce places removed 5 places
Iterating global reduction 5 with
Drop transitions removed 54 transitions
Redundant transition composition
Iterating global reduction 5 with
Discarding 1 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Performed 4 Post agglomeration
Deduced a syphon composed of 4
Reduce places removed 4 places
Iterating global reduction 5 with
Discarding 3 places :
Symmetric choice reduction at 5
Iterating global reduction 5 with
Performed 1 Post agglomeration
Deduced a syphon composed of 1
Reduce places removed 1 places
Iterating global reduction 5 with
Applied a total of 253 rules in
Running SMT prover for 2 properties.
// Phase 1: matrix 98 rows 43 cols
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
[2023-03-08 14:38:18] [INFO ]
Attempting to minimize the solution
Minimization took 14 ms.
[2023-03-08 14:38:18] [INFO ]
Successfully simplified 42 atomic
FORMULA CloudDeployment-PT-6b-CTLFireability-04
[2023-03-08 14:38:19] [INFO
[2023-03-08 14:38:19] [INFO ]
FORMULA CloudDeployment-PT-6b-CTLFireability-15
[2023-03-08 14:38:20] [INFO
[2023-03-08 14:38:21] [INFO ]
Support contains 55 out of 1155
Computed a total of 184 stabilizing
Graph (complete) has 3784 edges
Starting structural reductions
Ensure Unique test removed 1 places
Iterating post reduction 0 with
Discarding 28 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 8 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 2 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Applied a total of 78 rules in
Finished structural reductions
[2023-03-08 14:38:22] [INFO ]
[2023-03-08 14:38:22] [INFO ]
[2023-03-08 14:38:22] [INFO ]
Starting structural reductions
Ensure Unique test removed 1 places
Iterating post reduction 0 with
Discarding 27 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 7 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 2 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Applied a total of 74 rules in
Finished structural reductions
[2023-03-08 14:38:23] [INFO ]
[2023-03-08 14:38:23] [INFO ]
[2023-03-08 14:38:23] [INFO ]
Starting structural reductions
Graph (trivial) has 1165 edges
Free SCC test removed 367 places
Ensure Unique test removed 419
Reduce isomorphic transitions removed
Graph (complete) has 3311 edges
Discarding 1 places :
Also discarding 1 output transitions
Drop transitions removed 1 transitions
Drop transitions removed 311 transitions
Trivial Post-agglo rules discarded
Performed 311 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 311 places
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed
Performed 3 Post agglomeration
Iterating post reduction 1 with
Reduce places removed 3 places
Iterating post reduction 2 with
Performed 62 Pre agglomeration
Pre-agglomeration after 3 with
Deduced a syphon composed of 62
Reduce places removed 62 places
Iterating global reduction 3 with
Discarding 8 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 1 Pre agglomeration using
Pre-agglomeration after 4 with
Deduced a syphon composed of 1
Reduce places removed 1 places
Iterating global reduction 4 with
Performed 105 Post agglomeration
Deduced a syphon composed of 105
Reduce places removed 105 places
Iterating global reduction 4 with
Drop transitions removed 24 transitions
Redundant transition composition
Iterating global reduction 4 with
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded
Performed 12 trivial Post agglomeration.
Iterating post reduction 4 with
Reduce places removed 12 places
Iterating post reduction 5 with
Performed 6 Post agglomeration
Deduced a syphon composed of 6
Reduce places removed 6 places
Iterating global reduction 6 with
Applied a total of 1045 rules in
Finished structural reductions
[2023-03-08 14:38:25] [INFO ]
[2023-03-08 14:38:26] [INFO ]
[2023-03-08 14:38:27] [INFO ]
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Interrupted probabilistic random walk after 132913
Probabilistic random walk after 132913
Running SMT prover for 1 properties.
[2023-03-08 14:38:30] [INFO ]
// Phase 1: matrix 4911 rows 279 cols
[2023-03-08 14:38:30] [INFO ]
[2023-03-08 14:38:30] [INFO ]
[2023-03-08 14:38:31] [INFO ]
[2023-03-08 14:38:33] [INFO ]
[2023-03-08 14:38:33] [INFO ]
[2023-03-08 14:38:33] [INFO ]
[2023-03-08 14:38:34] [INFO ]
Attempting to minimize the solution
Minimization took 328 ms.
[2023-03-08 14:38:34] [INFO ]
Parikh walk visited 0 properties
Support contains 27 out of 279
Starting structural reductions
Drop transitions removed 51 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Performed 14 Post agglomeration
Deduced a syphon composed of 14
Reduce places removed 14 places
Iterating global reduction 1 with
Performed 18 Post agglomeration
Deduced a syphon composed of 18
Reduce places removed 18 places
Iterating global reduction 1 with
Drop transitions removed 12 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Drop transitions removed 134 transitions
Redundant transition composition
Iterating global reduction 2 with
Free-agglomeration rule applied
Iterating global reduction 2 with
Reduce places removed 62 places
Drop transitions removed 73 transitions
Ensure Unique test removed 80 transition
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Discarding 6 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Drop transitions removed 2 transitions
Redundant transition composition
Iterating global reduction 3 with
Partial Free-agglomeration rule
Drop transitions removed 1 transitions
Iterating global reduction 3 with
Applied a total of 553 rules in
Finished structural reductions
Finished random walk after 19937
FORMULA CloudDeployment-PT-6b-CTLFireability-02
Starting structural reductions
Graph (trivial) has 1186 edges
Free SCC test removed 386 places
Ensure Unique test removed 440
Reduce isomorphic transitions removed
Graph (complete) has 3281 edges
Discarding 33 places :
Also discarding 4097 output transitions
Drop transitions removed 4097 transitions
Reduce places removed 1 places
Drop transitions removed 302 transitions
Trivial Post-agglo rules discarded
Performed 302 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 302 places
Performed 1 Post agglomeration
Iterating post reduction 1 with
Reduce places removed 1 places
Iterating post reduction 2 with
Performed 61 Pre agglomeration
Pre-agglomeration after 3 with
Deduced a syphon composed of 61
Reduce places removed 61 places
Iterating global reduction 3 with
Discarding 7 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 102 Post agglomeration
Deduced a syphon composed of 102
Reduce places removed 102 places
Iterating global reduction 4 with
Drop transitions removed 24 transitions
Redundant transition composition
Iterating global reduction 4 with
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded
Performed 12 trivial Post agglomeration.
Iterating post reduction 4 with
Reduce places removed 12 places
Iterating post reduction 5 with
Performed 6 Post agglomeration
Deduced a syphon composed of 6
Reduce places removed 6 places
Iterating global reduction 6 with
Reduce places removed 1 places
Iterating global reduction 6 with
Applied a total of 1010 rules in
Finished structural reductions
[2023-03-08 14:38:35] [INFO ]
[2023-03-08 14:38:36] [INFO ]
[2023-03-08 14:38:36] [INFO ]
Finished random walk after 152
FORMULA CloudDeployment-PT-6b-CTLFireability-03
Starting structural reductions
Graph (trivial) has 1180 edges
Free SCC test removed 370 places
Ensure Unique test removed 421
Reduce isomorphic transitions removed
Graph (complete) has 3301 edges
Discarding 33 places :
Also discarding 4097 output transitions
Drop transitions removed 4097 transitions
Drop transitions removed 311 transitions
Trivial Post-agglo rules discarded
Performed 311 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 311 places
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Performed 2 Post agglomeration
Iterating post reduction 1 with
Reduce places removed 2 places
Iterating post reduction 2 with
Performed 61 Pre agglomeration
Pre-agglomeration after 3 with
Deduced a syphon composed of 61
Reduce places removed 61 places
Iterating global reduction 3 with
Discarding 8 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 2 Pre agglomeration using
Pre-agglomeration after 4 with
Deduced a syphon composed of 2
Reduce places removed 2 places
Iterating global reduction 4 with
Performed 104 Post agglomeration
Deduced a syphon composed of 104
Reduce places removed 104 places
Iterating global reduction 4 with
Drop transitions removed 25 transitions
Redundant transition composition
Iterating global reduction 4 with
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded
Performed 12 trivial Post agglomeration.
Iterating post reduction 4 with
Reduce places removed 12 places
Iterating post reduction 5 with
Performed 7 Post agglomeration
Deduced a syphon composed of 7
Reduce places removed 7 places
Iterating global reduction 6 with
Applied a total of 1043 rules in
Finished structural reductions
[2023-03-08 14:38:36] [INFO ]
[2023-03-08 14:38:36] [INFO ]
[2023-03-08 14:38:36] [INFO ]
Starting structural reductions
Ensure Unique test removed 1 places
Iterating post reduction 0 with
Discarding 28 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 8 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 2 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Applied a total of 78 rules in
Finished structural reductions
[2023-03-08 14:38:36] [INFO ]
[2023-03-08 14:38:36] [INFO ]
[2023-03-08 14:38:37] [INFO ]
Starting structural reductions
Graph (trivial) has 1187 edges
Free SCC test removed 386 places
Ensure Unique test removed 440
Reduce isomorphic transitions removed
Graph (complete) has 3281 edges
Discarding 33 places :
Also discarding 4097 output transitions
Drop transitions removed 4097 transitions
Reduce places removed 1 places
Drop transitions removed 304 transitions
Trivial Post-agglo rules discarded
Performed 304 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 304 places
Iterating post reduction 1 with
Performed 60 Pre agglomeration
Pre-agglomeration after 2 with
Deduced a syphon composed of 60
Reduce places removed 60 places
Iterating global reduction 2 with
Discarding 7 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Performed 103 Post agglomeration
Deduced a syphon composed of 103
Reduce places removed 103 places
Iterating global reduction 3 with
Drop transitions removed 24 transitions
Redundant transition composition
Iterating global reduction 3 with
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded
Performed 12 trivial Post agglomeration.
Iterating post reduction 3 with
Reduce places removed 12 places
Iterating post reduction 4 with
Performed 6 Post agglomeration
Deduced a syphon composed of 6
Reduce places removed 6 places
Iterating global reduction 5 with
Reduce places removed 1 places
Iterating global reduction 5 with
Applied a total of 1012 rules in
Finished structural reductions
[2023-03-08 14:38:37] [INFO ]
[2023-03-08 14:38:37] [INFO ]
[2023-03-08 14:38:37] [INFO ]
Starting structural reductions
Ensure Unique test removed 1 places
Iterating post reduction 0 with
Discarding 28 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 8 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 2 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Applied a total of 78 rules in
Finished structural reductions
[2023-03-08 14:38:37] [INFO ]
[2023-03-08 14:38:37] [INFO ]
[2023-03-08 14:38:38] [INFO ]
Starting structural reductions
Graph (trivial) has 1182 edges
Free SCC test removed 386 places
Ensure Unique test removed 440
Reduce isomorphic transitions removed
Graph (complete) has 3281 edges
Discarding 33 places :
Also discarding 4097 output transitions
Drop transitions removed 4097 transitions
Reduce places removed 1 places
Drop transitions removed 303 transitions
Trivial Post-agglo rules discarded
Performed 303 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 303 places
Performed 2 Post agglomeration
Iterating post reduction 1 with
Reduce places removed 2 places
Iterating post reduction 2 with
Performed 61 Pre agglomeration
Pre-agglomeration after 3 with
Deduced a syphon composed of 61
Reduce places removed 61 places
Iterating global reduction 3 with
Discarding 6 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 103 Post agglomeration
Deduced a syphon composed of 103
Reduce places removed 103 places
Iterating global reduction 4 with
Drop transitions removed 24 transitions
Redundant transition composition
Iterating global reduction 4 with
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded
Performed 12 trivial Post agglomeration.
Iterating post reduction 4 with
Reduce places removed 12 places
Iterating post reduction 5 with
Performed 6 Post agglomeration
Deduced a syphon composed of 6
Reduce places removed 6 places
Iterating global reduction 6 with
Reduce places removed 1 places
Iterating global reduction 6 with
Applied a total of 1014 rules in
Finished structural reductions
[2023-03-08 14:38:38] [INFO ]
[2023-03-08 14:38:38] [INFO ]
[2023-03-08 14:38:38] [INFO ]
Starting structural reductions
Graph (trivial) has 1189 edges
Free SCC test removed 386 places
Ensure Unique test removed 440
Reduce isomorphic transitions removed
Graph (complete) has 3281 edges
Discarding 33 places :
Also discarding 4097 output transitions
Drop transitions removed 4097 transitions
Reduce places removed 1 places
Drop transitions removed 306 transitions
Trivial Post-agglo rules discarded
Performed 306 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 306 places
Iterating post reduction 1 with
Performed 61 Pre agglomeration
Pre-agglomeration after 2 with
Deduced a syphon composed of 61
Reduce places removed 61 places
Iterating global reduction 2 with
Discarding 6 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 2 with
Performed 103 Post agglomeration
Deduced a syphon composed of 103
Reduce places removed 103 places
Iterating global reduction 3 with
Drop transitions removed 24 transitions
Redundant transition composition
Iterating global reduction 3 with
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded
Performed 12 trivial Post agglomeration.
Iterating post reduction 3 with
Reduce places removed 12 places
Iterating post reduction 4 with
Performed 6 Post agglomeration
Deduced a syphon composed of 6
Reduce places removed 6 places
Iterating global reduction 5 with
Reduce places removed 1 places
Iterating global reduction 5 with
Applied a total of 1016 rules in
Finished structural reductions
[2023-03-08 14:38:38] [INFO ]
[2023-03-08 14:38:38] [INFO ]
[2023-03-08 14:38:38] [INFO ]
Incomplete random walk after 10000
Incomplete Best-First random walk after 10001
Interrupted probabilistic random walk after 696928
Probabilistic random walk after 696928
Running SMT prover for 1 properties.
[2023-03-08 14:38:41] [INFO ]
// Phase 1: matrix 799 rows 240 cols
[2023-03-08 14:38:41] [INFO ]
[2023-03-08 14:38:41] [INFO ]
[2023-03-08 14:38:42] [INFO ]
[2023-03-08 14:38:42] [INFO ]
[2023-03-08 14:38:42] [INFO ]
[2023-03-08 14:38:42] [INFO ]
[2023-03-08 14:38:42] [INFO ]
[2023-03-08 14:38:42] [INFO ]
Attempting to minimize the solution
Minimization took 25 ms.
[2023-03-08 14:38:42] [INFO ]
Parikh walk visited 0 properties
Support contains 1 out of 240 places.
Starting structural reductions
Drop transitions removed 72 transitions
Reduce isomorphic transitions removed
Iterating post reduction 0 with
Performed 18 Post agglomeration
Deduced a syphon composed of 18
Reduce places removed 18 places
Iterating global reduction 1 with
Performed 18 Post agglomeration
Deduced a syphon composed of 18
Reduce places removed 18 places
Iterating global reduction 1 with
Drop transitions removed 18 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Drop transitions removed 191 transitions
Redundant transition composition
Iterating global reduction 2 with
Free-agglomeration rule applied
Iterating global reduction 2 with
Reduce places removed 66 places
Drop transitions removed 138 transitions
Ensure Unique test removed 72 transition
Reduce isomorphic transitions removed
Graph (complete) has 1082 edges
Discarding 1 places :
Also discarding 0 output transitions
Iterating post reduction 2 with
Drop transitions removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Discarding 6 places :
Symmetric choice reduction at 4
Iterating global reduction 4 with
Applied a total of 709 rules in
Finished structural reductions
Finished random walk after 332
FORMULA CloudDeployment-PT-6b-CTLFireability-10
Starting structural reductions
Ensure Unique test removed 1 places
Iterating post reduction 0 with
Discarding 27 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 7 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 2 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Applied a total of 74 rules in
Finished structural reductions
[2023-03-08 14:38:43] [INFO ]
[2023-03-08 14:38:43] [INFO ]
[2023-03-08 14:38:43] [INFO ]
Starting structural reductions
Ensure Unique test removed 1 places
Iterating post reduction 0 with
Discarding 26 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 7 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 1 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Applied a total of 70 rules in
Finished structural reductions
[2023-03-08 14:38:43] [INFO ]
[2023-03-08 14:38:43] [INFO ]
[2023-03-08 14:38:43] [INFO ]
Starting structural reductions
Graph (trivial) has 1188 edges
Free SCC test removed 386 places
Ensure Unique test removed 440
Reduce isomorphic transitions removed
Graph (complete) has 3281 edges
Discarding 33 places :
Also discarding 4097 output transitions
Drop transitions removed 4097 transitions
Reduce places removed 1 places
Drop transitions removed 303 transitions
Trivial Post-agglo rules discarded
Performed 303 trivial Post agglomeration.
Iterating post reduction 0 with
Reduce places removed 303 places
Performed 1 Post agglomeration
Iterating post reduction 1 with
Reduce places removed 1 places
Iterating post reduction 2 with
Performed 61 Pre agglomeration
Pre-agglomeration after 3 with
Deduced a syphon composed of 61
Reduce places removed 61 places
Iterating global reduction 3 with
Discarding 7 places :
Symmetric choice reduction at 3
Iterating global reduction 3 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 3 with
Performed 103 Post agglomeration
Deduced a syphon composed of 103
Reduce places removed 103 places
Iterating global reduction 4 with
Drop transitions removed 24 transitions
Redundant transition composition
Iterating global reduction 4 with
Drop transitions removed 12 transitions
Trivial Post-agglo rules discarded
Performed 12 trivial Post agglomeration.
Iterating post reduction 4 with
Reduce places removed 12 places
Iterating post reduction 5 with
Performed 6 Post agglomeration
Deduced a syphon composed of 6
Reduce places removed 6 places
Iterating global reduction 6 with
Reduce places removed 1 places
Iterating global reduction 6 with
Applied a total of 1014 rules in
Finished structural reductions
[2023-03-08 14:38:44] [INFO ]
[2023-03-08 14:38:44] [INFO ]
[2023-03-08 14:38:44] [INFO ]
Starting structural reductions
Ensure Unique test removed 1 places
Iterating post reduction 0 with
Discarding 28 places :
Symmetric choice reduction at 1
Iterating global reduction 1 with
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed
Iterating post reduction 1 with
Discarding 8 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Discarding 2 places :
Symmetric choice reduction at 2
Iterating global reduction 2 with
Applied a total of 78 rules in
Finished structural reductions
[2023-03-08 14:38:44] [INFO ]
[2023-03-08 14:38:44] [INFO ]
[2023-03-08 14:38:44] [INFO ]
[2023-03-08 14:38:45] [INFO ]
[2023-03-08 14:38:46] [INFO ]
[2023-03-08 14:38:46] [INFO ]
[2023-03-08 14:38:46] [INFO ]
Total runtime 86029 ms.
There are residual formulas that
starting LoLA
BK_INPUT CloudDeployment-PT-6b
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//.
current directory: /home/mcc/execution/3
CTLFireability

FORMULA CloudDeployment-PT-6b-CTLFireability-00

FORMULA CloudDeployment-PT-6b-CTLFireability-12

FORMULA CloudDeployment-PT-6b-CTLFireability-11

FORMULA CloudDeployment-PT-6b-CTLFireability-06

FORMULA CloudDeployment-PT-6b-CTLFireability-01

FORMULA CloudDeployment-PT-6b-CTLFireability-14

FORMULA CloudDeployment-PT-6b-CTLFireability-13

FORMULA CloudDeployment-PT-6b-CTLFireability-08

FORMULA CloudDeployment-PT-6b-CTLFireability-07
TIME LIMIT: Killed by timeout
MemTotal: 16393216 kB
MemFree: 13851208 kB
After kill :
MemTotal: 16393216 kB
MemFree: 16091800 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/i
+ PYTHONPATH=/home/mcc/BenchKit/itstools
+ export LD_LIBRARY_PATH=/home/mcc/Bench
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/its
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execu
lola: reading pnml
lola: PNML file contains place/transition
lola: finished parsing
lola: closed net file /home/mcc/execut
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/e
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=================================================== examination is CTLFireability 8000434 ============================= 25 14:49 CTLCardinality.txt 25 14:49 CTLCardinality.xml 25 14:48 CTLFireability.txt 25 14:48 CTLFireability.xml 29 11:40 GenericPropertiesDefinition.xml 29 11:40 GenericPropertiesVerdict.xml 25 15:45 LTLCardinality.txt 25 15:45 LTLCardinality.xml 25 15:45 LTLFireability.txt 25 15:45 LTLFireability.xml 25 14:50 ReachabilityCardinality.txt 25 14:50 ReachabilityCardinality.xml 25 14:49 ReachabilityFireability.txt 25 14:49 ReachabilityFireability.xml 25 15:45 UpperBounds.txt 25 15:45 UpperBounds.xml 5 18:22 equiv_col 5 18:22 instance 5 18:22 iscolored 5 18:22 model.pnml by BenchKit (invocation template) of booleans the result vector(from text file) reability-00 reability-01 reability-02 reability-03 reability-04 reability-05 reability-06 reability-07 reability-08 reability-09 reability-10 reability-11 reability-12 reability-13 reability-14 reability-15 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML] Parsing pnml file : /home/mcc/execution/model.pnml Load time of PNML (sax parser for PT used): 726 ms Transformed 1888 places. Transformed 6804 transitions. Found NUPN structural information; Parsed PT model containing 1888 places and 6804 transitions and 91831 arcs in 917 ms. /home/mcc/execution/CTLFireability.xml in 17 ms. places. Attempting structural reductions. in LTL mode, iteration 0 : 1888/1888 places, 6804/6804 transitions. and 0 transitions. 6 rules applied. Total rules applied 6 place count 1882 transition count 6804 with 511 rule applications. Total rules 517 place count 1371 transition count 6293 511 rules applied. Total rules applied 1028 place count 1371 transition count 6293 with 196 rule applications. Total rules 1224 place count 1175 transition count 6097 196 rules applied. Total rules applied 1420 place count 1175 transition count 6097 s 29 transitions. 29 rules applied. Total rules applied 1449 place count 1175 transition count 6068 with 17 rule applications. Total rules 1466 place count 1158 transition count 6051 17 rules applied. Total rules applied 1483 place count 1158 transition count 6051 with 2 rule applications. Total rules 1485 place count 1156 transition count 6049 2 rules applied. Total rules applied 1487 place count 1156 transition count 6049 with 1 rule applications. Total rules 1488 place count 1155 transition count 6048 1 rules applied. Total rules applied 1489 place count 1155 transition count 6048 963 ms. Remains 1155 /1888 variables (removed 733) and now considering 6048/6804 (removed 756) transitions. Computed 19 place invariants in 189 ms Implicit Places using invariants in 869 ms returned [] Invariant cache hit. Implicit Places using invariants and state equation in 1409 ms returned [] with State Equation took 2329 ms to find 0 implicit places. Invariant cache hit. Dead Transitions using invariants and state equation in 5749 ms found 0 transitions. in LTL mode, iteration 1 : 1155/1888 places, 6048/6804 transitions. in LTL mode , in 1 iterations and 9051 ms. Remains : 1155/1888 places, 6048/6804 transitions. places after structural reductions. Flatten gal took : 1471 ms Flatten gal took : 1098 ms Input system was already deterministic with 6048 transitions. steps, including 52 resets, run finished after 1030 ms. (steps per millisecond=9 ) properties (out of 75) seen :12 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 32 ms. (steps per millisecond=31 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 12 ms. (steps per millisecond=83 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=52 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 10 ms. (steps per millisecond=100 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=142 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 8 ms. (steps per millisecond=125 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 63) seen :0 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 63) seen :0 Invariant cache hit. [Real]Absence check using 0 positive and 19 generalized place invariants in 25 ms returned sat After 1924ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:63 [Nat]Absence check using 0 positive and 19 generalized place invariants in 11 ms returned sat After 11920ms SMT Verify possible using state equation in natural domain returned unsat :42 sat :21 After 20060ms SMT Verify possible using trap constraints in natural domain returned unsat :42 sat :21 found. After 25021ms SMT Verify possible using all constraints in natural domain returned unsat :42 sat :20 different solutions. in 1043 ms. places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. and 1155 vertex of which 410 / 1155 are part of one of the 46 SCC in 9 ms 4558 transitions. and 791 vertex of which 758 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.9 ms 22 transitions. 317 transitions Transition count delta: 317 339 rules applied. Total rules applied 341 place count 758 transition count 1151 and 0 transitions. 1 transitions. using F-continuation condition.Transition count delta: 2 320 rules applied. Total rules applied 661 place count 441 transition count 1148 and 0 transitions. 2 rules applied. Total rules applied 663 place count 439 transition count 1148 using Quasi-Persistent + Divergent Free condition.. 67 Pre rules applied. Total rules applied 663 place count 439 transition count 1081 places in 1 ms and 0 transitions. 134 rules applied. Total rules applied 797 place count 372 transition count 1081 with 13 rule applications. Total rules 810 place count 359 transition count 1068 13 rules applied. Total rules applied 823 place count 359 transition count 1068 1 transitions. 1 rules applied. Total rules applied 824 place count 359 transition count 1067 Quasi-Persistent + Divergent Free condition.. 9 Pre rules applied. Total rules applied 824 place count 359 transition count 1058 places in 4 ms and 0 transitions. 18 rules applied. Total rules applied 842 place count 350 transition count 1058 using F-continuation condition.Transition count delta: 98 places in 2 ms and 0 transitions. 196 rules applied. Total rules applied 1038 place count 252 transition count 960 using F-continuation condition.Transition count delta: -257 places in 2 ms and 0 transitions. 76 rules applied. Total rules applied 1114 place count 214 transition count 1217 s 48 transitions. 48 rules applied. Total rules applied 1162 place count 214 transition count 1169 using F-continuation condition.Transition count delta: -60 places in 1 ms and 0 transitions. 12 rules applied. Total rules applied 1174 place count 208 transition count 1229 rules discarded 150 transitions 150 rules applied. Total rules applied 1324 place count 208 transition count 1079 55 times with reduction of 20 identical transitions. 55 rules applied. Total rules applied 1379 place count 208 transition count 1004 and 0 transitions. s 170 transitions. 225 rules applied. Total rules applied 1604 place count 153 transition count 834 with 7 rule applications. Total rules 1611 place count 146 transition count 778 7 rules applied. Total rules applied 1618 place count 146 transition count 778 2 transitions. 2 rules applied. Total rules applied 1620 place count 146 transition count 776 rules discarded 91 transitions 91 rules applied. Total rules applied 1711 place count 146 transition count 685 applied 1 times. 1 rules applied. Total rules applied 1712 place count 146 transition count 685 481 ms. Remains 146 /1155 variables (removed 1009) and now considering 685/6048 (removed 5363) transitions. in REACHABILITY mode , in 1 iterations and 482 ms. Remains : 146/1155 places, 685/6048 transitions. steps, including 130 resets, run finished after 224 ms. (steps per millisecond=44 ) properties (out of 5) seen :2 steps, including 15 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 3) seen :0 steps, including 6 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 3) seen :0 steps, including 15 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 3) seen :0 Flow matrix only has 381 transitions (discarded 304 similar events) Computed 22 place invariants in 5 ms [Real]Absence check using 6 positive place invariants in 3 ms returned sat [Real]Absence check using 6 positive and 16 generalized place invariants in 5 ms returned sat After 254ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:2 State equation strengthened by 228 read => feed constraints. After 79ms SMT Verify possible using 228 Read/Feed constraints in real domain returned unsat :0 sat :0 real:3 After 444ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:3 [Nat]Absence check using 6 positive place invariants in 11 ms returned sat [Nat]Absence check using 6 positive and 16 generalized place invariants in 7 ms returned sat After 241ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :3 After 158ms SMT Verify possible using 228 Read/Feed constraints in natural domain returned unsat :0 sat :3 Deduced a trap composed of 4 places in 197 ms of which 2 ms to minimize. Deduced a trap composed of 46 places in 154 ms of which 1 ms to minimize. Trap strengthening (SAT) tested/added 3/2 trap constraints in 402 ms After 689ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :3 found. After 1118ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :3 in 21 ms. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 146/146 places, 685/685 transitions. 146 vertex of which 2 / 146 are part of one of the 1 SCC in 0 ms 2 transitions. 1 transitions Transition count delta: 1 1 rules applied. Total rules applied 2 place count 145 transition count 682 and 0 transitions. 1 rules applied. Total rules applied 3 place count 144 transition count 682 with 1 rule applications. Total rules 4 place count 143 transition count 675 1 rules applied. Total rules applied 5 place count 143 transition count 675 using F-continuation condition.Transition count delta: 1 places in 1 ms and 0 transitions. 2 rules applied. Total rules applied 7 place count 142 transition count 674 4 transitions. 4 rules applied. Total rules applied 11 place count 142 transition count 670 rules discarded 33 transitions 33 rules applied. Total rules applied 44 place count 142 transition count 637 113 ms. Remains 142 /146 variables (removed 4) and now considering 637/685 (removed 48) transitions. in REACHABILITY mode , in 1 iterations and 114 ms. Remains : 142/146 places, 637/685 transitions. steps, including 149 resets, run finished after 372 ms. (steps per millisecond=26 ) properties (out of 3) seen :1 steps, including 17 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 2) seen :0 steps, including 9 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 2) seen :0 Flow matrix only has 342 transitions (discarded 295 similar events) Computed 22 place invariants in 4 ms [Real]Absence check using 6 positive place invariants in 5 ms returned sat [Real]Absence check using 6 positive and 16 generalized place invariants in 8 ms returned sat After 234ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:1 State equation strengthened by 202 read => feed constraints. After 76ms SMT Verify possible using 202 Read/Feed constraints in real domain returned unsat :0 sat :0 real:2 After 410ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2 [Nat]Absence check using 6 positive place invariants in 4 ms returned sat [Nat]Absence check using 6 positive and 16 generalized place invariants in 8 ms returned sat After 216ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2 After 156ms SMT Verify possible using 202 Read/Feed constraints in natural domain returned unsat :0 sat :2 Deduced a trap composed of 4 places in 156 ms of which 2 ms to minimize. Trap strengthening (SAT) tested/added 2/1 trap constraints in 190 ms After 459ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2 found. After 863ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2 in 7 ms. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 142/142 places, 637/637 transitions. using F-continuation condition.Transition count delta: 1 places in 1 ms and 0 transitions. 2 rules applied. Total rules applied 2 place count 141 transition count 636 ms. Remains 141 /142 variables (removed 1) and now considering 636/637 (removed 1) transitions. in REACHABILITY mode , in 1 iterations and 29 ms. Remains : 141/142 places, 636/637 transitions. steps, including 140 resets, run finished after 140 ms. (steps per millisecond=71 ) properties (out of 2) seen :0 steps, including 15 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 2) seen :0 steps, including 10 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 2) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=177 ) properties seen :{} steps, saw 68247 distinct states, run finished after 3008 ms. (steps per millisecond=177 ) properties seen :0 Flow matrix only has 341 transitions (discarded 295 similar events) Computed 22 place invariants in 2 ms [Real]Absence check using 6 positive place invariants in 4 ms returned sat [Real]Absence check using 6 positive and 16 generalized place invariants in 9 ms returned sat After 187ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:1 State equation strengthened by 202 read => feed constraints. After 61ms SMT Verify possible using 202 Read/Feed constraints in real domain returned unsat :0 sat :0 real:2 After 335ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2 [Nat]Absence check using 6 positive place invariants in 2 ms returned sat [Nat]Absence check using 6 positive and 16 generalized place invariants in 5 ms returned sat After 155ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2 After 95ms SMT Verify possible using 202 Read/Feed constraints in natural domain returned unsat :0 sat :2 After 171ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2 found. After 430ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2 in 5 ms. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 141/141 places, 636/636 transitions. ms. Remains 141 /141 variables (removed 0) and now considering 636/636 (removed 0) transitions. in REACHABILITY mode , in 1 iterations and 16 ms. Remains : 141/141 places, 636/636 transitions. in REACHABILITY mode, iteration 0 : 141/141 places, 636/636 transitions. ms. Remains 141 /141 variables (removed 0) and now considering 636/636 (removed 0) transitions. Flow matrix only has 341 transitions (discarded 295 similar events) Invariant cache hit. Implicit Places using invariants in 135 ms returned [] Flow matrix only has 341 transitions (discarded 295 similar events) Invariant cache hit. State equation strengthened by 202 read => feed constraints. Implicit Places using invariants and state equation in 481 ms returned [] with State Equation took 623 ms to find 0 implicit places. Redundant transitions in 354 ms returned [] Flow matrix only has 341 transitions (discarded 295 similar events) Invariant cache hit. Dead Transitions using invariants and state equation in 474 ms found 0 transitions. in REACHABILITY mode , in 1 iterations and 1479 ms. Remains : 141/141 places, 636/636 transitions. 141 vertex of which 39 / 141 are part of one of the 5 SCC in 1 ms transitions 348 transitions. 11 transitions Transition count delta: 11 20 rules applied. Total rules applied 21 place count 98 transition count 277 and 0 transitions. using F-continuation condition.Transition count delta: 1 12 rules applied. Total rules applied 33 place count 87 transition count 276 and 0 transitions. 1 transitions. 2 rules applied. Total rules applied 35 place count 86 transition count 275 using Quasi-Persistent + Divergent Free condition.. 10 Pre rules applied. Total rules applied 35 place count 86 transition count 265 places in 0 ms and 0 transitions. 20 rules applied. Total rules applied 55 place count 76 transition count 265 with 4 rule applications. Total rules 59 place count 72 transition count 261 4 rules applied. Total rules applied 63 place count 72 transition count 261 with 4 rule applications. Total rules 67 place count 68 transition count 257 4 rules applied. Total rules applied 71 place count 68 transition count 257 with 4 rule applications. Total rules 75 place count 64 transition count 229 4 rules applied. Total rules applied 79 place count 64 transition count 229 s 68 transitions. 68 rules applied. Total rules applied 147 place count 64 transition count 161 using F-continuation condition.Transition count delta: 7 places in 1 ms and 0 transitions. 14 rules applied. Total rules applied 161 place count 57 transition count 154 s 10 transitions. 10 rules applied. Total rules applied 171 place count 57 transition count 144 using F-continuation condition.Transition count delta: -30 places in 0 ms and 0 transitions. 10 rules applied. Total rules applied 181 place count 52 transition count 174 rules discarded 54 transitions 54 rules applied. Total rules applied 235 place count 52 transition count 120 with 1 rule applications. Total rules 236 place count 51 transition count 117 1 rules applied. Total rules applied 237 place count 51 transition count 117 using F-continuation condition.Transition count delta: 4 places in 0 ms and 0 transitions. 8 rules applied. Total rules applied 245 place count 47 transition count 113 with 3 rule applications. Total rules 248 place count 44 transition count 89 3 rules applied. Total rules applied 251 place count 44 transition count 89 using F-continuation condition.Transition count delta: -9 places in 0 ms and 0 transitions. 2 rules applied. Total rules applied 253 place count 43 transition count 98 45 ms. Remains 43 /141 variables (removed 98) and now considering 98/636 (removed 538) transitions. Computed 10 place invariants in 33 ms [Real]Absence check using 3 positive place invariants in 1 ms returned sat [Real]Absence check using 3 positive and 7 generalized place invariants in 2 ms returned sat After 42ms SMT Verify possible using state equation in real domain returned unsat :0 sat :1 real:1 State equation strengthened by 8 read => feed constraints. After 7ms SMT Verify possible using 8 Read/Feed constraints in real domain returned unsat :0 sat :0 real:2 After 89ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2 [Nat]Absence check using 3 positive place invariants in 1 ms returned sat [Nat]Absence check using 3 positive and 7 generalized place invariants in 3 ms returned sat After 40ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2 After 15ms SMT Verify possible using 8 Read/Feed constraints in natural domain returned unsat :0 sat :2 After 33ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2 found. After 122ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2 propositions for a total of 16 simplifications. TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE ] Initial state reduction rules for CTL removed 1 formulas. Flatten gal took : 857 ms TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE ] Flatten gal took : 996 ms Input system was already deterministic with 6048 transitions. places (down from 62) after GAL structural reductions. places and 4758 stable transitions and 1155 vertex of which 1122 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.56 ms in LTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. 1 rules applied. Total rules applied 1 place count 1154 transition count 6048 with 28 rule applications. Total rules 29 place count 1126 transition count 1937 28 rules applied. Total rules applied 57 place count 1126 transition count 1937 1 transitions. 1 rules applied. Total rules applied 58 place count 1126 transition count 1936 with 8 rule applications. Total rules 66 place count 1118 transition count 1928 8 rules applied. Total rules applied 74 place count 1118 transition count 1928 with 2 rule applications. Total rules 76 place count 1116 transition count 1926 2 rules applied. Total rules applied 78 place count 1116 transition count 1926 425 ms. Remains 1116 /1155 variables (removed 39) and now considering 1926/6048 (removed 4122) transitions. in LTL mode , in 1 iterations and 426 ms. Remains : 1116/1155 places, 1926/6048 transitions. Flatten gal took : 62 ms Flatten gal took : 67 ms Input system was already deterministic with 1926 transitions. in LTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. 1 rules applied. Total rules applied 1 place count 1154 transition count 6048 with 27 rule applications. Total rules 28 place count 1127 transition count 1938 27 rules applied. Total rules applied 55 place count 1127 transition count 1938 1 transitions. 1 rules applied. Total rules applied 56 place count 1127 transition count 1937 with 7 rule applications. Total rules 63 place count 1120 transition count 1930 7 rules applied. Total rules applied 70 place count 1120 transition count 1930 with 2 rule applications. Total rules 72 place count 1118 transition count 1928 2 rules applied. Total rules applied 74 place count 1118 transition count 1928 659 ms. Remains 1118 /1155 variables (removed 37) and now considering 1928/6048 (removed 4120) transitions. in LTL mode , in 1 iterations and 660 ms. Remains : 1118/1155 places, 1928/6048 transitions. Flatten gal took : 64 ms Flatten gal took : 70 ms Input system was already deterministic with 1928 transitions. in SI_CTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. and 1155 vertex of which 412 / 1155 are part of one of the 45 SCC in 4 ms transitions 419 transitions. and 788 vertex of which 787 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.23 ms 311 transitions Transition count delta: 311 311 rules applied. Total rules applied 313 place count 787 transition count 5317 and 0 transitions. 2 transitions. using F-continuation condition.Transition count delta: 3 316 rules applied. Total rules applied 629 place count 476 transition count 5312 and 0 transitions. 3 rules applied. Total rules applied 632 place count 473 transition count 5312 using Quasi-Persistent + Divergent Free condition.. 62 Pre rules applied. Total rules applied 632 place count 473 transition count 5250 places in 2 ms and 0 transitions. 124 rules applied. Total rules applied 756 place count 411 transition count 5250 with 8 rule applications. Total rules 764 place count 403 transition count 5242 8 rules applied. Total rules applied 772 place count 403 transition count 5242 1 transitions. 1 rules applied. Total rules applied 773 place count 403 transition count 5241 Quasi-Persistent + Divergent Free condition.. 1 Pre rules applied. Total rules applied 773 place count 403 transition count 5240 places in 2 ms and 0 transitions. 2 rules applied. Total rules applied 775 place count 402 transition count 5240 using F-continuation condition.Transition count delta: 105 places in 1 ms and 0 transitions. 210 rules applied. Total rules applied 985 place count 297 transition count 5135 rules discarded 24 transitions 24 rules applied. Total rules applied 1009 place count 297 transition count 5111 12 transitions Transition count delta: 12 12 rules applied. Total rules applied 1021 place count 297 transition count 5099 and 0 transitions. 12 rules applied. Total rules applied 1033 place count 285 transition count 5099 using F-continuation condition.Transition count delta: 6 places in 0 ms and 0 transitions. 12 rules applied. Total rules applied 1045 place count 279 transition count 5093 644 ms. Remains 279 /1155 variables (removed 876) and now considering 5093/6048 (removed 955) transitions. in SI_CTL mode , in 1 iterations and 646 ms. Remains : 279/1155 places, 5093/6048 transitions. Flatten gal took : 844 ms Flatten gal took : 839 ms Input system was already deterministic with 5093 transitions. steps, including 241 resets, run finished after 287 ms. (steps per millisecond=34 ) properties (out of 1) seen :0 steps, including 17 resets, run finished after 57 ms. (steps per millisecond=175 ) properties (out of 1) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=44 ) properties seen :{} steps, saw 26511 distinct states, run finished after 3005 ms. (steps per millisecond=44 ) properties seen :0 Flow matrix only has 4911 transitions (discarded 182 similar events) Computed 19 place invariants in 56 ms After 60ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1 [Nat]Absence check using 0 positive and 19 generalized place invariants in 6 ms returned sat After 2093ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1 State equation strengthened by 233 read => feed constraints. After 694ms SMT Verify possible using 233 Read/Feed constraints in natural domain returned unsat :0 sat :1 After 1062ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1 found. After 3585ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1 in 1 ms. places. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 279/279 places, 5093/5093 transitions. 51 transitions. 51 rules applied. Total rules applied 51 place count 279 transition count 5042 using F-continuation condition.Transition count delta: 14 places in 0 ms and 0 transitions. 28 rules applied. Total rules applied 79 place count 265 transition count 5028 using F-continuation condition.Transition count delta: -192 places in 0 ms and 0 transitions. 36 rules applied. Total rules applied 115 place count 247 transition count 5220 12 transitions. 12 rules applied. Total rules applied 127 place count 247 transition count 5208 rules discarded 134 transitions 134 rules applied. Total rules applied 261 place count 247 transition count 5074 62 times with reduction of 16 identical transitions. 62 rules applied. Total rules applied 323 place count 247 transition count 4996 and 0 transitions. s 153 transitions. 215 rules applied. Total rules applied 538 place count 185 transition count 4843 with 6 rule applications. Total rules 544 place count 179 transition count 4799 6 rules applied. Total rules applied 550 place count 179 transition count 4799 rules discarded 2 transitions 2 rules applied. Total rules applied 552 place count 179 transition count 4797 applied 1 times. 1 rules applied. Total rules applied 553 place count 179 transition count 4797 732 ms. Remains 179 /279 variables (removed 100) and now considering 4797/5093 (removed 296) transitions. in REACHABILITY mode , in 1 iterations and 734 ms. Remains : 179/279 places, 4797/5093 transitions. steps, including 300 resets, run visited all 1 properties in 412 ms. (steps per millisecond=48 ) FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK in SI_CTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. and 1155 vertex of which 434 / 1155 are part of one of the 48 SCC in 1 ms transitions 440 transitions. and 769 vertex of which 736 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.7 ms and 1 transitions. 302 transitions Transition count delta: 302 302 rules applied. Total rules applied 304 place count 735 transition count 1208 and 0 transitions. using F-continuation condition.Transition count delta: 1 303 rules applied. Total rules applied 607 place count 433 transition count 1207 and 0 transitions. 1 rules applied. Total rules applied 608 place count 432 transition count 1207 using Quasi-Persistent + Divergent Free condition.. 61 Pre rules applied. Total rules applied 608 place count 432 transition count 1146 places in 1 ms and 0 transitions. 122 rules applied. Total rules applied 730 place count 371 transition count 1146 with 7 rule applications. Total rules 737 place count 364 transition count 1139 7 rules applied. Total rules applied 744 place count 364 transition count 1139 1 transitions. 1 rules applied. Total rules applied 745 place count 364 transition count 1138 using F-continuation condition.Transition count delta: 102 places in 0 ms and 0 transitions. 204 rules applied. Total rules applied 949 place count 262 transition count 1036 rules discarded 24 transitions 24 rules applied. Total rules applied 973 place count 262 transition count 1012 12 transitions Transition count delta: 12 12 rules applied. Total rules applied 985 place count 262 transition count 1000 and 0 transitions. 12 rules applied. Total rules applied 997 place count 250 transition count 1000 using F-continuation condition.Transition count delta: 6 places in 1 ms and 0 transitions. 12 rules applied. Total rules applied 1009 place count 244 transition count 994 and 1 transitions. 1 rules applied. Total rules applied 1010 place count 243 transition count 993 180 ms. Remains 243 /1155 variables (removed 912) and now considering 993/6048 (removed 5055) transitions. in SI_CTL mode , in 1 iterations and 180 ms. Remains : 243/1155 places, 993/6048 transitions. Flatten gal took : 38 ms Flatten gal took : 40 ms Input system was already deterministic with 993 transitions. steps, including 3 resets, run visited all 1 properties in 3 ms. (steps per millisecond=50 ) FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK in SI_CTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. and 1155 vertex of which 417 / 1155 are part of one of the 47 SCC in 1 ms transitions 421 transitions. and 785 vertex of which 752 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.7 ms 311 transitions Transition count delta: 311 311 rules applied. Total rules applied 313 place count 752 transition count 1219 and 0 transitions. 1 transitions. using F-continuation condition.Transition count delta: 2 314 rules applied. Total rules applied 627 place count 441 transition count 1216 and 0 transitions. 2 rules applied. Total rules applied 629 place count 439 transition count 1216 using Quasi-Persistent + Divergent Free condition.. 61 Pre rules applied. Total rules applied 629 place count 439 transition count 1155 places in 1 ms and 0 transitions. 122 rules applied. Total rules applied 751 place count 378 transition count 1155 with 8 rule applications. Total rules 759 place count 370 transition count 1147 8 rules applied. Total rules applied 767 place count 370 transition count 1147 1 transitions. 1 rules applied. Total rules applied 768 place count 370 transition count 1146 Quasi-Persistent + Divergent Free condition.. 2 Pre rules applied. Total rules applied 768 place count 370 transition count 1144 places in 1 ms and 0 transitions. 4 rules applied. Total rules applied 772 place count 368 transition count 1144 using F-continuation condition.Transition count delta: 104 places in 0 ms and 0 transitions. 208 rules applied. Total rules applied 980 place count 264 transition count 1040 rules discarded 25 transitions 25 rules applied. Total rules applied 1005 place count 264 transition count 1015 12 transitions Transition count delta: 12 12 rules applied. Total rules applied 1017 place count 264 transition count 1003 and 0 transitions. 12 rules applied. Total rules applied 1029 place count 252 transition count 1003 using F-continuation condition.Transition count delta: 7 places in 1 ms and 0 transitions. 14 rules applied. Total rules applied 1043 place count 245 transition count 996 160 ms. Remains 245 /1155 variables (removed 910) and now considering 996/6048 (removed 5052) transitions. in SI_CTL mode , in 1 iterations and 160 ms. Remains : 245/1155 places, 996/6048 transitions. Flatten gal took : 30 ms Flatten gal took : 34 ms Input system was already deterministic with 996 transitions. in LTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. 1 rules applied. Total rules applied 1 place count 1154 transition count 6048 with 28 rule applications. Total rules 29 place count 1126 transition count 1937 28 rules applied. Total rules applied 57 place count 1126 transition count 1937 1 transitions. 1 rules applied. Total rules applied 58 place count 1126 transition count 1936 with 8 rule applications. Total rules 66 place count 1118 transition count 1928 8 rules applied. Total rules applied 74 place count 1118 transition count 1928 with 2 rule applications. Total rules 76 place count 1116 transition count 1926 2 rules applied. Total rules applied 78 place count 1116 transition count 1926 395 ms. Remains 1116 /1155 variables (removed 39) and now considering 1926/6048 (removed 4122) transitions. in LTL mode , in 1 iterations and 395 ms. Remains : 1116/1155 places, 1926/6048 transitions. Flatten gal took : 64 ms Flatten gal took : 70 ms Input system was already deterministic with 1926 transitions. in SI_CTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. and 1155 vertex of which 434 / 1155 are part of one of the 48 SCC in 1 ms transitions 440 transitions. and 769 vertex of which 736 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.5 ms and 1 transitions. 304 transitions Transition count delta: 304 304 rules applied. Total rules applied 306 place count 735 transition count 1206 and 0 transitions. 304 rules applied. Total rules applied 610 place count 431 transition count 1206 using Quasi-Persistent + Divergent Free condition.. 60 Pre rules applied. Total rules applied 610 place count 431 transition count 1146 places in 1 ms and 0 transitions. 120 rules applied. Total rules applied 730 place count 371 transition count 1146 with 7 rule applications. Total rules 737 place count 364 transition count 1139 7 rules applied. Total rules applied 744 place count 364 transition count 1139 1 transitions. 1 rules applied. Total rules applied 745 place count 364 transition count 1138 using F-continuation condition.Transition count delta: 103 places in 0 ms and 0 transitions. 206 rules applied. Total rules applied 951 place count 261 transition count 1035 rules discarded 24 transitions 24 rules applied. Total rules applied 975 place count 261 transition count 1011 12 transitions Transition count delta: 12 12 rules applied. Total rules applied 987 place count 261 transition count 999 and 0 transitions. 12 rules applied. Total rules applied 999 place count 249 transition count 999 using F-continuation condition.Transition count delta: 6 places in 0 ms and 0 transitions. 12 rules applied. Total rules applied 1011 place count 243 transition count 993 and 1 transitions. 1 rules applied. Total rules applied 1012 place count 242 transition count 992 169 ms. Remains 242 /1155 variables (removed 913) and now considering 992/6048 (removed 5056) transitions. in SI_CTL mode , in 1 iterations and 170 ms. Remains : 242/1155 places, 992/6048 transitions. Flatten gal took : 38 ms Flatten gal took : 41 ms Input system was already deterministic with 992 transitions. in LTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. 1 rules applied. Total rules applied 1 place count 1154 transition count 6048 with 28 rule applications. Total rules 29 place count 1126 transition count 1937 28 rules applied. Total rules applied 57 place count 1126 transition count 1937 1 transitions. 1 rules applied. Total rules applied 58 place count 1126 transition count 1936 with 8 rule applications. Total rules 66 place count 1118 transition count 1928 8 rules applied. Total rules applied 74 place count 1118 transition count 1928 with 2 rule applications. Total rules 76 place count 1116 transition count 1926 2 rules applied. Total rules applied 78 place count 1116 transition count 1926 401 ms. Remains 1116 /1155 variables (removed 39) and now considering 1926/6048 (removed 4122) transitions. in LTL mode , in 1 iterations and 401 ms. Remains : 1116/1155 places, 1926/6048 transitions. Flatten gal took : 64 ms Flatten gal took : 70 ms Input system was already deterministic with 1926 transitions. in SI_CTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. and 1155 vertex of which 434 / 1155 are part of one of the 48 SCC in 1 ms transitions 440 transitions. and 769 vertex of which 736 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.4 ms and 1 transitions. 303 transitions Transition count delta: 303 303 rules applied. Total rules applied 305 place count 735 transition count 1207 and 0 transitions. using F-continuation condition.Transition count delta: 2 305 rules applied. Total rules applied 610 place count 432 transition count 1205 and 0 transitions. 2 rules applied. Total rules applied 612 place count 430 transition count 1205 using Quasi-Persistent + Divergent Free condition.. 61 Pre rules applied. Total rules applied 612 place count 430 transition count 1144 places in 1 ms and 0 transitions. 122 rules applied. Total rules applied 734 place count 369 transition count 1144 with 6 rule applications. Total rules 740 place count 363 transition count 1138 6 rules applied. Total rules applied 746 place count 363 transition count 1138 1 transitions. 1 rules applied. Total rules applied 747 place count 363 transition count 1137 using F-continuation condition.Transition count delta: 103 places in 0 ms and 0 transitions. 206 rules applied. Total rules applied 953 place count 260 transition count 1034 rules discarded 24 transitions 24 rules applied. Total rules applied 977 place count 260 transition count 1010 12 transitions Transition count delta: 12 12 rules applied. Total rules applied 989 place count 260 transition count 998 and 0 transitions. 12 rules applied. Total rules applied 1001 place count 248 transition count 998 using F-continuation condition.Transition count delta: 6 places in 1 ms and 0 transitions. 12 rules applied. Total rules applied 1013 place count 242 transition count 992 and 1 transitions. 1 rules applied. Total rules applied 1014 place count 241 transition count 991 161 ms. Remains 241 /1155 variables (removed 914) and now considering 991/6048 (removed 5057) transitions. in SI_CTL mode , in 1 iterations and 161 ms. Remains : 241/1155 places, 991/6048 transitions. Flatten gal took : 36 ms Flatten gal took : 40 ms Input system was already deterministic with 991 transitions. in SI_CTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. and 1155 vertex of which 434 / 1155 are part of one of the 48 SCC in 1 ms transitions 440 transitions. and 769 vertex of which 736 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.4 ms and 1 transitions. 306 transitions Transition count delta: 306 306 rules applied. Total rules applied 308 place count 735 transition count 1204 and 0 transitions. 306 rules applied. Total rules applied 614 place count 429 transition count 1204 using Quasi-Persistent + Divergent Free condition.. 61 Pre rules applied. Total rules applied 614 place count 429 transition count 1143 places in 1 ms and 0 transitions. 122 rules applied. Total rules applied 736 place count 368 transition count 1143 with 6 rule applications. Total rules 742 place count 362 transition count 1137 6 rules applied. Total rules applied 748 place count 362 transition count 1137 1 transitions. 1 rules applied. Total rules applied 749 place count 362 transition count 1136 using F-continuation condition.Transition count delta: 103 places in 0 ms and 0 transitions. 206 rules applied. Total rules applied 955 place count 259 transition count 1033 rules discarded 24 transitions 24 rules applied. Total rules applied 979 place count 259 transition count 1009 12 transitions Transition count delta: 12 12 rules applied. Total rules applied 991 place count 259 transition count 997 and 0 transitions. 12 rules applied. Total rules applied 1003 place count 247 transition count 997 using F-continuation condition.Transition count delta: 6 places in 0 ms and 0 transitions. 12 rules applied. Total rules applied 1015 place count 241 transition count 991 and 1 transitions. 1 rules applied. Total rules applied 1016 place count 240 transition count 990 150 ms. Remains 240 /1155 variables (removed 915) and now considering 990/6048 (removed 5058) transitions. in SI_CTL mode , in 1 iterations and 152 ms. Remains : 240/1155 places, 990/6048 transitions. Flatten gal took : 38 ms Flatten gal took : 42 ms Input system was already deterministic with 990 transitions. steps, including 242 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 1) seen :0 steps, including 12 resets, run finished after 9 ms. (steps per millisecond=1111 ) properties (out of 1) seen :0 steps, run timeout after 3001 ms. (steps per millisecond=232 ) properties seen :{} steps, saw 100933 distinct states, run finished after 3004 ms. (steps per millisecond=232 ) properties seen :0 Flow matrix only has 799 transitions (discarded 191 similar events) Computed 6 place invariants in 6 ms [Real]Absence check using 0 positive and 6 generalized place invariants in 3 ms returned sat After 299ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1 [Nat]Absence check using 0 positive and 6 generalized place invariants in 4 ms returned sat After 235ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1 State equation strengthened by 36 read => feed constraints. After 41ms SMT Verify possible using 36 Read/Feed constraints in natural domain returned unsat :0 sat :1 After 81ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1 found. After 401ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1 in 10 ms. Attempting structural reductions. in REACHABILITY mode, iteration 0 : 240/240 places, 990/990 transitions. 72 transitions. 72 rules applied. Total rules applied 72 place count 240 transition count 918 using F-continuation condition.Transition count delta: 18 places in 0 ms and 0 transitions. 36 rules applied. Total rules applied 108 place count 222 transition count 900 using F-continuation condition.Transition count delta: -192 places in 1 ms and 0 transitions. 36 rules applied. Total rules applied 144 place count 204 transition count 1092 18 transitions. 18 rules applied. Total rules applied 162 place count 204 transition count 1074 rules discarded 191 transitions 191 rules applied. Total rules applied 353 place count 204 transition count 883 66 times with reduction of 30 identical transitions. 66 rules applied. Total rules applied 419 place count 204 transition count 787 and 0 transitions. s 210 transitions. and 138 vertex of which 137 are kept as prefixes of interest. Removing 1 places using SCC suffix rule.1 ms 277 rules applied. Total rules applied 696 place count 137 transition count 577 1 transitions. 1 rules applied. Total rules applied 697 place count 137 transition count 576 with 6 rule applications. Total rules 703 place count 131 transition count 534 6 rules applied. Total rules applied 709 place count 131 transition count 534 78 ms. Remains 131 /240 variables (removed 109) and now considering 534/990 (removed 456) transitions. in REACHABILITY mode , in 1 iterations and 79 ms. Remains : 131/240 places, 534/990 transitions. steps, including 4 resets, run visited all 1 properties in 2 ms. (steps per millisecond=166 ) TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK in LTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. 1 rules applied. Total rules applied 1 place count 1154 transition count 6048 with 27 rule applications. Total rules 28 place count 1127 transition count 1938 27 rules applied. Total rules applied 55 place count 1127 transition count 1938 1 transitions. 1 rules applied. Total rules applied 56 place count 1127 transition count 1937 with 7 rule applications. Total rules 63 place count 1120 transition count 1930 7 rules applied. Total rules applied 70 place count 1120 transition count 1930 with 2 rule applications. Total rules 72 place count 1118 transition count 1928 2 rules applied. Total rules applied 74 place count 1118 transition count 1928 416 ms. Remains 1118 /1155 variables (removed 37) and now considering 1928/6048 (removed 4120) transitions. in LTL mode , in 1 iterations and 418 ms. Remains : 1118/1155 places, 1928/6048 transitions. Flatten gal took : 67 ms Flatten gal took : 73 ms Input system was already deterministic with 1928 transitions. in LTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. 1 rules applied. Total rules applied 1 place count 1154 transition count 6048 with 26 rule applications. Total rules 27 place count 1128 transition count 1939 26 rules applied. Total rules applied 53 place count 1128 transition count 1939 1 transitions. 1 rules applied. Total rules applied 54 place count 1128 transition count 1938 with 7 rule applications. Total rules 61 place count 1121 transition count 1931 7 rules applied. Total rules applied 68 place count 1121 transition count 1931 with 1 rule applications. Total rules 69 place count 1120 transition count 1930 1 rules applied. Total rules applied 70 place count 1120 transition count 1930 394 ms. Remains 1120 /1155 variables (removed 35) and now considering 1930/6048 (removed 4118) transitions. in LTL mode , in 1 iterations and 394 ms. Remains : 1120/1155 places, 1930/6048 transitions. Flatten gal took : 59 ms Flatten gal took : 64 ms Input system was already deterministic with 1930 transitions. in SI_CTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. and 1155 vertex of which 434 / 1155 are part of one of the 48 SCC in 2 ms transitions 440 transitions. and 769 vertex of which 736 are kept as prefixes of interest. Removing 33 places using SCC suffix rule.3 ms and 1 transitions. 303 transitions Transition count delta: 303 303 rules applied. Total rules applied 305 place count 735 transition count 1207 and 0 transitions. using F-continuation condition.Transition count delta: 1 304 rules applied. Total rules applied 609 place count 432 transition count 1206 and 0 transitions. 1 rules applied. Total rules applied 610 place count 431 transition count 1206 using Quasi-Persistent + Divergent Free condition.. 61 Pre rules applied. Total rules applied 610 place count 431 transition count 1145 places in 1 ms and 0 transitions. 122 rules applied. Total rules applied 732 place count 370 transition count 1145 with 7 rule applications. Total rules 739 place count 363 transition count 1138 7 rules applied. Total rules applied 746 place count 363 transition count 1138 1 transitions. 1 rules applied. Total rules applied 747 place count 363 transition count 1137 using F-continuation condition.Transition count delta: 103 places in 0 ms and 0 transitions. 206 rules applied. Total rules applied 953 place count 260 transition count 1034 rules discarded 24 transitions 24 rules applied. Total rules applied 977 place count 260 transition count 1010 12 transitions Transition count delta: 12 12 rules applied. Total rules applied 989 place count 260 transition count 998 and 0 transitions. 12 rules applied. Total rules applied 1001 place count 248 transition count 998 using F-continuation condition.Transition count delta: 6 places in 1 ms and 0 transitions. 12 rules applied. Total rules applied 1013 place count 242 transition count 992 and 1 transitions. 1 rules applied. Total rules applied 1014 place count 241 transition count 991 154 ms. Remains 241 /1155 variables (removed 914) and now considering 991/6048 (removed 5057) transitions. in SI_CTL mode , in 1 iterations and 155 ms. Remains : 241/1155 places, 991/6048 transitions. Flatten gal took : 38 ms Flatten gal took : 43 ms Input system was already deterministic with 991 transitions. in LTL mode, iteration 0 : 1155/1155 places, 6048/6048 transitions. 1 rules applied. Total rules applied 1 place count 1154 transition count 6048 with 28 rule applications. Total rules 29 place count 1126 transition count 1937 28 rules applied. Total rules applied 57 place count 1126 transition count 1937 1 transitions. 1 rules applied. Total rules applied 58 place count 1126 transition count 1936 with 8 rule applications. Total rules 66 place count 1118 transition count 1928 8 rules applied. Total rules applied 74 place count 1118 transition count 1928 with 2 rule applications. Total rules 76 place count 1116 transition count 1926 2 rules applied. Total rules applied 78 place count 1116 transition count 1926 419 ms. Remains 1116 /1155 variables (removed 39) and now considering 1926/6048 (removed 4122) transitions. in LTL mode , in 1 iterations and 419 ms. Remains : 1116/1155 places, 1926/6048 transitions. Flatten gal took : 61 ms Flatten gal took : 67 ms Input system was already deterministic with 1926 transitions. Flatten gal took : 847 ms Flatten gal took : 909 ms Export to MCC of 11 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms. Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 1155 places, 6048 transitions and 90240 arcs took 87 ms. ITS could not solve within timeout ./reducer/bin//../../lola/bin/ 73 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT after 3600 seconds tstools/pylibs /pylibs Kit/itstools/pylibs: tools/pylibs: /bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar //../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML tion/373/model.pnml net ion/373/model.pnml xecution/373/CTLFireability.xml rewrite.k:96 rewrite.k:138 rewrite.k:550 rewrite.k:475 rewrite.k:96 rewrite.k:138 rewrite.k:325 rewrite.k:337 rewrite.k:296 rewrite.k:296 rewrite.k:325 rewrite.k:328 rewrite.k:296 rewrite.k:96 rewrite.k:138 rewrite.k:199 rewrite.k:150 rewrite.k:96 rewrite.k:138 secs. secs. VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 AFAG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 AFAG 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 0 secs. secs. secs. VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 AFAG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 CTL 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 AFAG 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 0 secs. secs. secs. places removed VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS 0 0 0 0 0 0 0 0 CTL 0 0 0 0 1 0 0 0 AFAG 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 CTL 0 0 0 0 1 0 0 0 AFAG 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 0 secs. for 0 CloudDeployment-PT-6b-CTLFireability-00 CNST) for CloudDeployment-PT-6b-CTLFireability-00 secs. rewrite.k:813 rewrite.k:806 rewrite.k:813 rewrite.k:811 EXCL) for 18 CloudDeployment-PT-6b-CTLFireability-09 rewrite.k:813 rewrite.k:811 rewrite.k:815 rewrite.k:811 rewrite.k:808 rewrite.k:812 rewrite.k:807 rewrite.k:812 rewrite.k:806 rewrite.k:811 rewrite.k:807 rewrite.k:807 rewrite.k:812 rewrite.k:808 rewrite.k:679 rewrite.k:679 rewrite.k:813 rewrite.k:809 rewrite.k:811 rewrite.k:808 rewrite.k:807 rewrite.k:812 rewrite.k:811 rewrite.k:749 rewrite.k:776 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 CloudDeployment-PT-6b-CTLFireability-09 38489 m, 7697 m/sec, 207014 t fired, . in use: 1 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 CloudDeployment-PT-6b-CTLFireability-09 255048 m, 43311 m/sec, 1620421 t fired, . in use: 2 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 CloudDeployment-PT-6b-CTLFireability-09 478532 m, 44696 m/sec, 2993370 t fired, . in use: 3 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 CloudDeployment-PT-6b-CTLFireability-09 689652 m, 42224 m/sec, 4383513 t fired, . in use: 4 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 CloudDeployment-PT-6b-CTLFireability-09 880479 m, 38165 m/sec, 5842551 t fired, . in use: 4 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 CloudDeployment-PT-6b-CTLFireability-09 1073399 m, 38584 m/sec, 7313306 t fired, . in use: 5 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 CloudDeployment-PT-6b-CTLFireability-09 1276318 m, 40583 m/sec, 8612902 t fired, . in use: 6 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 CloudDeployment-PT-6b-CTLFireability-09 1484583 m, 41653 m/sec, 9971989 t fired, . in use: 7 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 CloudDeployment-PT-6b-CTLFireability-09 1691779 m, 41439 m/sec, 11308637 t fired, . in use: 8 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-6b-CTLFireability-09 1878614 m, 37367 m/sec, 12758213 t fired, . in use: 9 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 CloudDeployment-PT-6b-CTLFireability-09 2047602 m, 33797 m/sec, 14112804 t fired, . in use: 10 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 CloudDeployment-PT-6b-CTLFireability-09 2220306 m, 34540 m/sec, 15597055 t fired, . in use: 10 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 CloudDeployment-PT-6b-CTLFireability-09 2378927 m, 31724 m/sec, 16929484 t fired, . in use: 11 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-6b-CTLFireability-09 2543149 m, 32844 m/sec, 18331100 t fired, . in use: 12 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-6b-CTLFireability-09 2699322 m, 31234 m/sec, 19872916 t fired, . in use: 12 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 CloudDeployment-PT-6b-CTLFireability-09 2865404 m, 33216 m/sec, 21161012 t fired, . in use: 13 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 CloudDeployment-PT-6b-CTLFireability-09 3064444 m, 39808 m/sec, 22493642 t fired, . in use: 14 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-6b-CTLFireability-09 3260737 m, 39258 m/sec, 23732070 t fired, . in use: 15 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 CloudDeployment-PT-6b-CTLFireability-09 3448732 m, 37599 m/sec, 25070695 t fired, . in use: 16 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-6b-CTLFireability-09 3628276 m, 35908 m/sec, 26473077 t fired, . in use: 17 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-6b-CTLFireability-09 3790957 m, 32536 m/sec, 27964272 t fired, . in use: 17 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 CloudDeployment-PT-6b-CTLFireability-09 3957268 m, 33262 m/sec, 29488938 t fired, . in use: 18 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-6b-CTLFireability-09 4113535 m, 31253 m/sec, 30983159 t fired, . in use: 19 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-6b-CTLFireability-09 4260090 m, 29311 m/sec, 32500773 t fired, . in use: 19 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-6b-CTLFireability-09 4414446 m, 30871 m/sec, 34095811 t fired, . in use: 20 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 CloudDeployment-PT-6b-CTLFireability-09 4591859 m, 35482 m/sec, 35494752 t fired, . in use: 21 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 CloudDeployment-PT-6b-CTLFireability-09 4807836 m, 43195 m/sec, 36836905 t fired, . in use: 22 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-6b-CTLFireability-09 5014929 m, 41418 m/sec, 38201003 t fired, . in use: 23 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-6b-CTLFireability-09 5208251 m, 38664 m/sec, 39700953 t fired, . in use: 24 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-6b-CTLFireability-09 5385878 m, 35525 m/sec, 41103711 t fired, . in use: 24 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 CloudDeployment-PT-6b-CTLFireability-09 5548730 m, 32570 m/sec, 42669207 t fired, . in use: 25 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-6b-CTLFireability-09 5701871 m, 30628 m/sec, 44133613 t fired, . in use: 26 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-6b-CTLFireability-09 5862054 m, 32036 m/sec, 45623180 t fired, . in use: 26 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 CloudDeployment-PT-6b-CTLFireability-09 6013486 m, 30286 m/sec, 47208547 t fired, . in use: 27 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 CloudDeployment-PT-6b-CTLFireability-09 6150044 m, 27311 m/sec, 48718956 t fired, . in use: 28 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 CloudDeployment-PT-6b-CTLFireability-09 6324302 m, 34851 m/sec, 50149123 t fired, . in use: 29 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 CloudDeployment-PT-6b-CTLFireability-09 6503356 m, 35810 m/sec, 51616436 t fired, . in use: 29 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 CloudDeployment-PT-6b-CTLFireability-09 6665374 m, 32403 m/sec, 53010390 t fired, . in use: 30 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 CloudDeployment-PT-6b-CTLFireability-09 6823494 m, 31624 m/sec, 54487716 t fired, . in use: 31 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 CloudDeployment-PT-6b-CTLFireability-09 6976894 m, 30680 m/sec, 55985961 t fired, . in use: 31 VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-6b-CTLFireability-09 7176097 m, 39840 m/sec, 57300036 t fired, . in use: 32 EXCL) for CloudDeployment-PT-6b-CTLFireability-09 (memory limit exceeded) VALUE PRODUCED BY false preprocessing IDL ACT RUN SUS FIN C/T C/M OBS CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 AFAG 0 1 0 0 1 0 0 0 F 0 1 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 EXCL) for 24 CloudDeployment-PT-6b-CTLFireability-12 EXCL) for CloudDeployment-PT-6b-CTLFireability-12 4989 15423 0.000000 1 EXCL) for 21 CloudDeployment-PT-6b-CTLFireability-11 EXCL) for CloudDeployment-PT-6b-CTLFireability-11 236 236 0.000000 1 EXCL) for 9 CloudDeployment-PT-6b-CTLFireability-06 EXCL) for CloudDeployment-PT-6b-CTLFireability-06 237 237 0.000000 1 for 3 CloudDeployment-PT-6b-CTLFireability-01 EXCL) for CloudDeployment-PT-6b-CTLFireability-01 229 228 0.000000 1 EXCL) for 30 CloudDeployment-PT-6b-CTLFireability-14 EXCL) for CloudDeployment-PT-6b-CTLFireability-14 71 71 0.000000 1 EXCL) for 27 CloudDeployment-PT-6b-CTLFireability-13 EXCL) for CloudDeployment-PT-6b-CTLFireability-13 15 30 0.000000 1 for 6 CloudDeployment-PT-6b-CTLFireability-05 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 1/32 CloudDeployment-PT-6b-CTLFireability-05 215711 m, 43142 m/sec, 1272808 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 2/32 CloudDeployment-PT-6b-CTLFireability-05 410695 m, 38996 m/sec, 2788821 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 3/32 CloudDeployment-PT-6b-CTLFireability-05 607903 m, 39441 m/sec, 4107163 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 4/32 CloudDeployment-PT-6b-CTLFireability-05 817774 m, 41974 m/sec, 5504428 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 5/32 CloudDeployment-PT-6b-CTLFireability-05 1016304 m, 39706 m/sec, 6883184 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 6/32 CloudDeployment-PT-6b-CTLFireability-05 1202820 m, 37303 m/sec, 8265902 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 7/32 CloudDeployment-PT-6b-CTLFireability-05 1417780 m, 42992 m/sec, 9608765 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 8/32 CloudDeployment-PT-6b-CTLFireability-05 1602269 m, 36897 m/sec, 11053285 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-6b-CTLFireability-05 1790288 m, 37603 m/sec, 12464365 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 9/32 CloudDeployment-PT-6b-CTLFireability-05 1986036 m, 39149 m/sec, 13741183 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 10/32 CloudDeployment-PT-6b-CTLFireability-05 2171965 m, 37185 m/sec, 15098047 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 11/32 CloudDeployment-PT-6b-CTLFireability-05 2374034 m, 40413 m/sec, 16546279 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 12/32 CloudDeployment-PT-6b-CTLFireability-05 2565614 m, 38316 m/sec, 17824188 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 13/32 CloudDeployment-PT-6b-CTLFireability-05 2758543 m, 38585 m/sec, 19118177 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 14/32 CloudDeployment-PT-6b-CTLFireability-05 2946575 m, 37606 m/sec, 20479779 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-6b-CTLFireability-05 3119381 m, 34561 m/sec, 21829484 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 15/32 CloudDeployment-PT-6b-CTLFireability-05 3281654 m, 32454 m/sec, 23181803 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 16/32 CloudDeployment-PT-6b-CTLFireability-05 3434753 m, 30619 m/sec, 24591315 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-6b-CTLFireability-05 3609069 m, 34863 m/sec, 26178120 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 17/32 CloudDeployment-PT-6b-CTLFireability-05 3766893 m, 31564 m/sec, 27476888 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 18/32 CloudDeployment-PT-6b-CTLFireability-05 3904417 m, 27504 m/sec, 28830224 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-6b-CTLFireability-05 4070254 m, 33167 m/sec, 30201630 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 19/32 CloudDeployment-PT-6b-CTLFireability-05 4223884 m, 30726 m/sec, 31668918 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 20/32 CloudDeployment-PT-6b-CTLFireability-05 4362951 m, 27813 m/sec, 33047267 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 21/32 CloudDeployment-PT-6b-CTLFireability-05 4554799 m, 38369 m/sec, 34255927 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 22/32 CloudDeployment-PT-6b-CTLFireability-05 4740390 m, 37118 m/sec, 35530025 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-6b-CTLFireability-05 4930988 m, 38119 m/sec, 36920769 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 23/32 CloudDeployment-PT-6b-CTLFireability-05 5109517 m, 35705 m/sec, 38136516 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 24/32 CloudDeployment-PT-6b-CTLFireability-05 5297006 m, 37497 m/sec, 39377750 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 25/32 CloudDeployment-PT-6b-CTLFireability-05 5462753 m, 33149 m/sec, 40604239 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-6b-CTLFireability-05 5619597 m, 31368 m/sec, 41853870 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 26/32 CloudDeployment-PT-6b-CTLFireability-05 5783823 m, 32845 m/sec, 43283804 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 27/32 CloudDeployment-PT-6b-CTLFireability-05 5925799 m, 28395 m/sec, 44799377 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 CloudDeployment-PT-6b-CTLFireability-05 6092992 m, 33438 m/sec, 46388479 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 28/32 CloudDeployment-PT-6b-CTLFireability-05 6242315 m, 29864 m/sec, 47870030 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 29/32 CloudDeployment-PT-6b-CTLFireability-05 6384491 m, 28435 m/sec, 49315306 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 CloudDeployment-PT-6b-CTLFireability-05 6526655 m, 28432 m/sec, 50691581 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 30/32 CloudDeployment-PT-6b-CTLFireability-05 6668431 m, 28355 m/sec, 52133933 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 31/32 CloudDeployment-PT-6b-CTLFireability-05 6816733 m, 29660 m/sec, 53693053 t fired, . in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 1 0 1 0 0 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS 32/32 CloudDeployment-PT-6b-CTLFireability-05 6982455 m, 33144 m/sec, 55043429 t fired, . in use: 32 EXCL) for CloudDeployment-PT-6b-CTLFireability-05 (memory limit exceeded) VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 1 0 0 1 0 0 0 0 1 0 0 1 0 0 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 EXCL) for 15 CloudDeployment-PT-6b-CTLFireability-08 EXCL) for CloudDeployment-PT-6b-CTLFireability-08 71 71 0.000000 1 EXCL) for 12 CloudDeployment-PT-6b-CTLFireability-07 EXCL) for CloudDeployment-PT-6b-CTLFireability-07 15 45 0.000000 1 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS in use: 32 VALUE PRODUCED BY false preprocessing CTL true CTL model checker CTL false CTL model checker CTL true CTL model checker false LTL model checker CTL true CTL model checker CTL false CTL model checker AFAG false CTL model checker F false state space / EG IDL ACT RUN SUS FIN C/T C/M OBS AFAG 0 0 0 0 1 0 1 0 CTL 0 0 0 0 1 0 1 0 MEM PG/PGLIMIT FORMULA STATUS truncated ====== if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CloudDeployment-PT-6b"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is CloudDeployment-PT-6b, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-smll-167814398000434"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CloudDeployment-PT-6b.tgz
mv CloudDeployment-PT-6b execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;