About the Execution of LoLa+red for ClientsAndServers-PT-N2000P0
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 3079.451 | 155567.00 | 141220.00 | 1131.70 | ??T?T?FTTT?FF?T? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r071-smll-167814397900346.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ClientsAndServers-PT-N2000P0, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-smll-167814397900346
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 496K
-rw-r--r-- 1 mcc users 7.1K Feb 26 13:15 CTLCardinality.txt
-rw-r--r-- 1 mcc users 75K Feb 26 13:15 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 26 13:14 CTLFireability.txt
-rw-r--r-- 1 mcc users 60K Feb 26 13:14 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 13:16 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 140K Feb 26 13:16 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.4K Feb 26 13:15 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 13:15 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 9.2K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-00
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-01
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-02
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-03
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-04
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-05
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-06
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-07
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-08
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-09
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-10
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-11
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-12
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-13
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-14
FORMULA_NAME ClientsAndServers-PT-N2000P0-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678274351870
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ClientsAndServers-PT-N2000P0
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 11:19:15] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 11:19:15] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 11:19:15] [INFO ] Load time of PNML (sax parser for PT used): 45 ms
[2023-03-08 11:19:15] [INFO ] Transformed 25 places.
[2023-03-08 11:19:15] [INFO ] Transformed 18 transitions.
[2023-03-08 11:19:15] [INFO ] Parsed PT model containing 25 places and 18 transitions and 54 arcs in 207 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 28 ms.
Support contains 25 out of 25 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Applied a total of 0 rules in 21 ms. Remains 25 /25 variables (removed 0) and now considering 18/18 (removed 0) transitions.
// Phase 1: matrix 18 rows 25 cols
[2023-03-08 11:19:16] [INFO ] Computed 8 place invariants in 9 ms
[2023-03-08 11:19:16] [INFO ] Implicit Places using invariants in 252 ms returned []
[2023-03-08 11:19:16] [INFO ] Invariant cache hit.
[2023-03-08 11:19:16] [INFO ] Implicit Places using invariants and state equation in 90 ms returned []
Implicit Place search using SMT with State Equation took 404 ms to find 0 implicit places.
[2023-03-08 11:19:16] [INFO ] Invariant cache hit.
[2023-03-08 11:19:16] [INFO ] Dead Transitions using invariants and state equation in 86 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 513 ms. Remains : 25/25 places, 18/18 transitions.
Support contains 25 out of 25 places after structural reductions.
[2023-03-08 11:19:16] [INFO ] Flatten gal took : 34 ms
[2023-03-08 11:19:16] [INFO ] Flatten gal took : 15 ms
[2023-03-08 11:19:16] [INFO ] Input system was already deterministic with 18 transitions.
Incomplete random walk after 16001 steps, including 0 resets, run finished after 41 ms. (steps per millisecond=390 ) properties (out of 41) seen :3
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 89 ms. (steps per millisecond=11 ) properties (out of 38) seen :23
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 49 ms. (steps per millisecond=20 ) properties (out of 15) seen :6
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 48 ms. (steps per millisecond=20 ) properties (out of 9) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 50 ms. (steps per millisecond=20 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 51 ms. (steps per millisecond=19 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 81 ms. (steps per millisecond=12 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 27 ms. (steps per millisecond=37 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 18 ms. (steps per millisecond=55 ) properties (out of 6) seen :4
Running SMT prover for 2 properties.
[2023-03-08 11:19:17] [INFO ] Invariant cache hit.
[2023-03-08 11:19:17] [INFO ] [Real]Absence check using 5 positive place invariants in 5 ms returned sat
[2023-03-08 11:19:17] [INFO ] [Real]Absence check using 5 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-08 11:19:17] [INFO ] After 145ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:2
[2023-03-08 11:19:17] [INFO ] [Nat]Absence check using 5 positive place invariants in 4 ms returned sat
[2023-03-08 11:19:17] [INFO ] [Nat]Absence check using 5 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-08 11:19:17] [INFO ] After 39ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :2
[2023-03-08 11:19:17] [INFO ] After 59ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :2
Attempting to minimize the solution found.
Minimization took 27 ms.
[2023-03-08 11:19:17] [INFO ] After 161ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :2
Fused 2 Parikh solutions to 1 different solutions.
Finished Parikh walk after 24000 steps, including 0 resets, run visited all 2 properties in 622 ms. (steps per millisecond=38 )
Parikh walk visited 2 properties in 626 ms.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 8 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 9 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 3 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 4 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 23 transition count 18
Applied a total of 2 rules in 2 ms. Remains 23 /25 variables (removed 2) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 23/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 4 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 4 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 1 with 2 Pre rules applied. Total rules applied 3 place count 22 transition count 16
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 1 with 4 rules applied. Total rules applied 7 place count 20 transition count 16
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 1 with 2 rules applied. Total rules applied 9 place count 19 transition count 15
Applied a total of 9 rules in 12 ms. Remains 19 /25 variables (removed 6) and now considering 15/18 (removed 3) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 19/25 places, 15/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 15 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 2 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 24 transition count 18
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 1 with 1 Pre rules applied. Total rules applied 1 place count 24 transition count 17
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 1 with 2 rules applied. Total rules applied 3 place count 23 transition count 17
Applied a total of 3 rules in 4 ms. Remains 23 /25 variables (removed 2) and now considering 17/18 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 23/25 places, 17/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 17 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 22 transition count 17
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 5 place count 21 transition count 17
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 1 Pre rules applied. Total rules applied 5 place count 21 transition count 16
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 1 places and 0 transitions.
Iterating global reduction 2 with 2 rules applied. Total rules applied 7 place count 20 transition count 16
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 11 place count 18 transition count 14
Applied a total of 11 rules in 12 ms. Remains 18 /25 variables (removed 7) and now considering 14/18 (removed 4) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 18/25 places, 14/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 14 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Applied a total of 3 rules in 2 ms. Remains 22 /25 variables (removed 3) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 22/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Applied a total of 3 rules in 1 ms. Remains 22 /25 variables (removed 3) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 2 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Applied a total of 3 rules in 1 ms. Remains 22 /25 variables (removed 3) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Applied a total of 3 rules in 1 ms. Remains 22 /25 variables (removed 3) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 22/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 5 rules applied. Total rules applied 5 place count 21 transition count 17
Reduce places removed 1 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 3 rules applied. Total rules applied 8 place count 20 transition count 15
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 10 place count 18 transition count 15
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 10 place count 18 transition count 11
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 18 place count 14 transition count 11
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 22 place count 12 transition count 9
Applied a total of 22 rules in 8 ms. Remains 12 /25 variables (removed 13) and now considering 9/18 (removed 9) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 12/25 places, 9/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 1 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 24 transition count 18
Applied a total of 1 rules in 1 ms. Remains 24 /25 variables (removed 1) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 24/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Applied a total of 3 rules in 1 ms. Remains 22 /25 variables (removed 3) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 23 transition count 18
Applied a total of 2 rules in 1 ms. Remains 23 /25 variables (removed 2) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 23/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 2 places :
Implicit places reduction removed 2 places
Iterating post reduction 0 with 2 rules applied. Total rules applied 2 place count 23 transition count 18
Applied a total of 2 rules in 1 ms. Remains 23 /25 variables (removed 2) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 23/25 places, 18/18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 3 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 2 ms
[2023-03-08 11:19:18] [INFO ] Input system was already deterministic with 18 transitions.
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 5 ms
[2023-03-08 11:19:18] [INFO ] Flatten gal took : 4 ms
[2023-03-08 11:19:18] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-08 11:19:18] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 25 places, 18 transitions and 54 arcs took 1 ms.
Total runtime 3322 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ClientsAndServers-PT-N2000P0
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA ClientsAndServers-PT-N2000P0-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678274507437
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 34 (type EXCL) for 33 ClientsAndServers-PT-N2000P0-CTLFireability-07
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 34 (type EXCL) for ClientsAndServers-PT-N2000P0-CTLFireability-07
lola: result : true
lola: markings : 251988
lola: fired transitions : 351988
lola: time used : 0.000000
lola: memory pages used : 2
lola: LAUNCH task # 62 (type EXCL) for 61 ClientsAndServers-PT-N2000P0-CTLFireability-15
lola: time limit : 189 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ClientsAndServers-PT-N2000P0-CTLFireability-07: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ClientsAndServers-PT-N2000P0-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-06: CONJ 0 4 0 0 4 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-11: EG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-15: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
62 CTL EXCL 5/189 17/32 ClientsAndServers-PT-N2000P0-CTLFireability-15 3517005 m, 703401 m/sec, 3555880 t fired, .
Time elapsed: 5 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 62 (type EXCL) for ClientsAndServers-PT-N2000P0-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ClientsAndServers-PT-N2000P0-CTLFireability-07: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ClientsAndServers-PT-N2000P0-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-06: CONJ 0 4 0 0 4 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-11: EG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 10 secs. Pages in use: 32
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lola: LAUNCH task # 59 (type EXCL) for 58 ClientsAndServers-PT-N2000P0-CTLFireability-14
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for ClientsAndServers-PT-N2000P0-CTLFireability-14
lola: result : true
lola: markings : 100000
lola: fired transitions : 99999
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 55 ClientsAndServers-PT-N2000P0-CTLFireability-13
lola: time limit : 211 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ClientsAndServers-PT-N2000P0-CTLFireability-07: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ClientsAndServers-PT-N2000P0-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-06: CONJ 0 4 0 0 4 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-11: EG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 5/211 9/32 ClientsAndServers-PT-N2000P0-CTLFireability-13 1835422 m, 367084 m/sec, 4851264 t fired, .
Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ClientsAndServers-PT-N2000P0-CTLFireability-07: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ClientsAndServers-PT-N2000P0-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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ClientsAndServers-PT-N2000P0-CTLFireability-08: DISJ true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-09: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-11: EG false state space / EG
ClientsAndServers-PT-N2000P0-CTLFireability-12: CTL false CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ClientsAndServers-PT-N2000P0-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/1155 22/32 ClientsAndServers-PT-N2000P0-CTLFireability-00 4781490 m, 956298 m/sec, 4810117 t fired, .
Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for ClientsAndServers-PT-N2000P0-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ClientsAndServers-PT-N2000P0-CTLFireability-06: CONJ false CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-07: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-08: DISJ true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-09: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-11: EG false state space / EG
ClientsAndServers-PT-N2000P0-CTLFireability-12: CTL false CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-14: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ClientsAndServers-PT-N2000P0-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N2000P0-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
ClientsAndServers-PT-N2000P0-CTLFireability-15: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 ClientsAndServers-PT-N2000P0-CTLFireability-02
lola: time limit : 1727 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for ClientsAndServers-PT-N2000P0-CTLFireability-02
lola: result : true
lola: markings : 520066
lola: fired transitions : 1440042
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 13 (type EXCL) for 12 ClientsAndServers-PT-N2000P0-CTLFireability-04
lola: time limit : 3454 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for ClientsAndServers-PT-N2000P0-CTLFireability-04
lola: result : true
lola: markings : 91994
lola: fired transitions : 147995
lola: time used : 1.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ClientsAndServers-PT-N2000P0-CTLFireability-00: CTL unknown AGGR
ClientsAndServers-PT-N2000P0-CTLFireability-01: CTL unknown AGGR
ClientsAndServers-PT-N2000P0-CTLFireability-02: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-03: CTL unknown AGGR
ClientsAndServers-PT-N2000P0-CTLFireability-04: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-05: CTL unknown AGGR
ClientsAndServers-PT-N2000P0-CTLFireability-06: CONJ false CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-07: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-08: DISJ true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-09: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-10: CTL unknown AGGR
ClientsAndServers-PT-N2000P0-CTLFireability-11: EG false state space / EG
ClientsAndServers-PT-N2000P0-CTLFireability-12: CTL false CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-13: CTL unknown AGGR
ClientsAndServers-PT-N2000P0-CTLFireability-14: CTL true CTL model checker
ClientsAndServers-PT-N2000P0-CTLFireability-15: CTL unknown AGGR
Time elapsed: 147 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ClientsAndServers-PT-N2000P0"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ClientsAndServers-PT-N2000P0, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-smll-167814397900346"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/ClientsAndServers-PT-N2000P0.tgz
mv ClientsAndServers-PT-N2000P0 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;