Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r071-smll-167814397800322.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ClientsAndServers-PT-N0200P0, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-smll-167814397800322
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 456K
-rw-r--r-- 1 mcc users 6.2K Feb 26 13:20 CTLCardinality.txt
-rw-r--r-- 1 mcc users 64K Feb 26 13:20 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.1K Feb 26 13:19 CTLFireability.txt
-rw-r--r-- 1 mcc users 45K Feb 26 13:19 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:44 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:44 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:44 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:44 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 13:21 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 139K Feb 26 13:21 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.5K Feb 26 13:21 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 63K Feb 26 13:21 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:44 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:44 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 8 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 9.2K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-00
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-01
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-02
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-03
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-04
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-05
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-06
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-07
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-08
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-09
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-10
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-11
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-12
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-13
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-14
FORMULA_NAME ClientsAndServers-PT-N0200P0-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678270198507

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ClientsAndServers-PT-N0200P0
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 10:10:01] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 10:10:01] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 10:10:01] [INFO ] Load time of PNML (sax parser for PT used): 31 ms
[2023-03-08 10:10:01] [INFO ] Transformed 25 places.
[2023-03-08 10:10:01] [INFO ] Transformed 18 transitions.
[2023-03-08 10:10:01] [INFO ] Parsed PT model containing 25 places and 18 transitions and 54 arcs in 168 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 16 ms.
Support contains 25 out of 25 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Applied a total of 0 rules in 13 ms. Remains 25 /25 variables (removed 0) and now considering 18/18 (removed 0) transitions.
// Phase 1: matrix 18 rows 25 cols
[2023-03-08 10:10:02] [INFO ] Computed 8 place invariants in 11 ms
[2023-03-08 10:10:02] [INFO ] Implicit Places using invariants in 347 ms returned []
[2023-03-08 10:10:02] [INFO ] Invariant cache hit.
[2023-03-08 10:10:02] [INFO ] Implicit Places using invariants and state equation in 87 ms returned []
Implicit Place search using SMT with State Equation took 483 ms to find 0 implicit places.
[2023-03-08 10:10:02] [INFO ] Invariant cache hit.
[2023-03-08 10:10:02] [INFO ] Dead Transitions using invariants and state equation in 72 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 571 ms. Remains : 25/25 places, 18/18 transitions.
Support contains 25 out of 25 places after structural reductions.
[2023-03-08 10:10:02] [INFO ] Flatten gal took : 26 ms
[2023-03-08 10:10:02] [INFO ] Flatten gal took : 10 ms
[2023-03-08 10:10:02] [INFO ] Input system was already deterministic with 18 transitions.
Incomplete random walk after 10018 steps, including 2 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 33) seen :11
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 64 ms. (steps per millisecond=15 ) properties (out of 22) seen :14
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=40 ) properties (out of 8) seen :7
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 9 ms. (steps per millisecond=111 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
[2023-03-08 10:10:03] [INFO ] Invariant cache hit.
[2023-03-08 10:10:03] [INFO ] [Real]Absence check using 5 positive place invariants in 6 ms returned sat
[2023-03-08 10:10:03] [INFO ] [Real]Absence check using 5 positive and 3 generalized place invariants in 2 ms returned sat
[2023-03-08 10:10:03] [INFO ] After 82ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 10:10:03] [INFO ] [Nat]Absence check using 5 positive place invariants in 3 ms returned sat
[2023-03-08 10:10:03] [INFO ] [Nat]Absence check using 5 positive and 3 generalized place invariants in 1 ms returned sat
[2023-03-08 10:10:03] [INFO ] After 19ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 10:10:03] [INFO ] After 28ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 7 ms.
[2023-03-08 10:10:03] [INFO ] After 83ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Finished Parikh walk after 120 steps, including 0 resets, run visited all 1 properties in 5 ms. (steps per millisecond=24 )
Parikh walk visited 1 properties in 6 ms.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 5 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 7 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 2 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 3 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 3 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 21 transition count 12
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 16 place count 15 transition count 12
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 16 place count 15 transition count 10
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 20 place count 13 transition count 10
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 28 place count 9 transition count 6
Applied a total of 28 rules in 12 ms. Remains 9 /25 variables (removed 16) and now considering 6/18 (removed 12) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 12 ms. Remains : 9/25 places, 6/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 6 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 2 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 21 transition count 12
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 16 place count 15 transition count 12
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 16 place count 15 transition count 10
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 20 place count 13 transition count 10
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 6 rules applied. Total rules applied 26 place count 10 transition count 7
Applied a total of 26 rules in 4 ms. Remains 10 /25 variables (removed 15) and now considering 7/18 (removed 11) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 10/25 places, 7/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 22 transition count 15
Reduce places removed 3 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 4 rules applied. Total rules applied 10 place count 19 transition count 14
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 11 place count 18 transition count 14
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 2 Pre rules applied. Total rules applied 11 place count 18 transition count 12
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 15 place count 16 transition count 12
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 21 place count 13 transition count 9
Applied a total of 21 rules in 4 ms. Remains 13 /25 variables (removed 12) and now considering 9/18 (removed 9) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 13/25 places, 9/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 9 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Drop transitions removed 2 transitions
Trivial Post-agglo rules discarded 2 transitions
Performed 2 trivial Post agglomeration. Transition count delta: 2
Iterating post reduction 0 with 6 rules applied. Total rules applied 6 place count 21 transition count 16
Reduce places removed 2 places and 0 transitions.
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Iterating post reduction 1 with 4 rules applied. Total rules applied 10 place count 19 transition count 14
Reduce places removed 2 places and 0 transitions.
Iterating post reduction 2 with 2 rules applied. Total rules applied 12 place count 17 transition count 14
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 12 place count 17 transition count 10
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 20 place count 13 transition count 10
Performed 2 Post agglomeration using F-continuation condition.Transition count delta: 2
Deduced a syphon composed of 2 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 3 with 4 rules applied. Total rules applied 24 place count 11 transition count 8
Applied a total of 24 rules in 4 ms. Remains 11 /25 variables (removed 14) and now considering 8/18 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 11/25 places, 8/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 8 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 1 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 3 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 1 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 3 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Applied a total of 3 rules in 0 ms. Remains 22 /25 variables (removed 3) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Applied a total of 3 rules in 1 ms. Remains 22 /25 variables (removed 3) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Iterating post reduction 0 with 4 rules applied. Total rules applied 4 place count 21 transition count 18
Applied a total of 4 rules in 1 ms. Remains 21 /25 variables (removed 4) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 21/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 24 transition count 18
Applied a total of 1 rules in 0 ms. Remains 24 /25 variables (removed 1) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 24/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 4 places :
Implicit places reduction removed 4 places
Drop transitions removed 6 transitions
Trivial Post-agglo rules discarded 6 transitions
Performed 6 trivial Post agglomeration. Transition count delta: 6
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 21 transition count 12
Reduce places removed 6 places and 0 transitions.
Iterating post reduction 1 with 6 rules applied. Total rules applied 16 place count 15 transition count 12
Performed 2 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 2 Pre rules applied. Total rules applied 16 place count 15 transition count 10
Deduced a syphon composed of 2 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 2 with 4 rules applied. Total rules applied 20 place count 13 transition count 10
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 2 with 6 rules applied. Total rules applied 26 place count 10 transition count 7
Applied a total of 26 rules in 3 ms. Remains 10 /25 variables (removed 15) and now considering 7/18 (removed 11) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 10/25 places, 7/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 7 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 3 places :
Implicit places reduction removed 3 places
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 22 transition count 18
Applied a total of 3 rules in 0 ms. Remains 22 /25 variables (removed 3) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 22/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 1 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 25/25 places, 18/18 transitions.
Discarding 1 places :
Implicit places reduction removed 1 places
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 24 transition count 18
Applied a total of 1 rules in 1 ms. Remains 24 /25 variables (removed 1) and now considering 18/18 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 24/25 places, 18/18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 2 ms
[2023-03-08 10:10:03] [INFO ] Input system was already deterministic with 18 transitions.
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 3 ms
[2023-03-08 10:10:03] [INFO ] Flatten gal took : 3 ms
[2023-03-08 10:10:03] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 10:10:03] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 25 places, 18 transitions and 54 arcs took 0 ms.
Total runtime 1866 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ClientsAndServers-PT-N0200P0
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ClientsAndServers-PT-N0200P0-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678270335814

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
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lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 56 (type EXCL) for 9 ClientsAndServers-PT-N0200P0-CTLFireability-03
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
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lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
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lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: Created skeleton in 0.000000 secs.
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lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ClientsAndServers-PT-N0200P0-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-01: EFEG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-02: EXEG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-03: F 0 0 1 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-05: F 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-08: CONJ 0 3 0 0 3 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-13: EG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 EG EXCL 5/200 16/32 ClientsAndServers-PT-N0200P0-CTLFireability-03 4124647 m, 824929 m/sec, 5671771 t fired, .

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ClientsAndServers-PT-N0200P0-CTLFireability-02: EXEG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-03: F 0 0 1 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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ClientsAndServers-PT-N0200P0-CTLFireability-08: CONJ 0 3 0 0 3 0 0 0
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ClientsAndServers-PT-N0200P0-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-13: EG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 EG EXCL 10/200 32/32 ClientsAndServers-PT-N0200P0-CTLFireability-03 8453482 m, 865767 m/sec, 11728053 t fired, .

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ClientsAndServers-PT-N0200P0-CTLFireability-02: EXEG 0 1 0 0 1 0 0 0
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ClientsAndServers-PT-N0200P0-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-13: EG 0 1 0 0 1 0 0 0
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lola: time limit : 210 sec
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lola: FINISHED task # 54 (type EXCL) for ClientsAndServers-PT-N0200P0-CTLFireability-15
lola: result : false
lola: markings : 669237
lola: fired transitions : 1638865
lola: time used : 2.000000
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ClientsAndServers-PT-N0200P0-CTLFireability-15: CTL false CTL model checker

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ClientsAndServers-PT-N0200P0-CTLFireability-02: EXEG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-03: F 0 0 0 0 1 0 1 0
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ClientsAndServers-PT-N0200P0-CTLFireability-13: EG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 3/223 8/32 ClientsAndServers-PT-N0200P0-CTLFireability-14 1882711 m, 376542 m/sec, 4298571 t fired, .

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ClientsAndServers-PT-N0200P0-CTLFireability-02: EXEG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-03: F 0 0 0 0 1 0 1 0
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ClientsAndServers-PT-N0200P0-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-08: CONJ 0 3 0 0 3 0 0 0
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ClientsAndServers-PT-N0200P0-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-13: EG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-14: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 8/223 18/32 ClientsAndServers-PT-N0200P0-CTLFireability-14 4222065 m, 467870 m/sec, 10081062 t fired, .

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ClientsAndServers-PT-N0200P0-CTLFireability-02: EXEG 0 1 0 0 1 0 0 0
ClientsAndServers-PT-N0200P0-CTLFireability-03: F 0 0 0 0 1 0 1 0
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42 CTL EXCL 35/253 25/32 ClientsAndServers-PT-N0200P0-CTLFireability-11 5757877 m, 158858 m/sec, 27899695 t fired, .

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42 CTL EXCL 40/253 28/32 ClientsAndServers-PT-N0200P0-CTLFireability-11 6544197 m, 157264 m/sec, 31788671 t fired, .

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42 CTL EXCL 45/253 31/32 ClientsAndServers-PT-N0200P0-CTLFireability-11 7332909 m, 157742 m/sec, 35699255 t fired, .

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19 CTL EXCL 7/388 29/32 ClientsAndServers-PT-N0200P0-CTLFireability-06 6432647 m, 791007 m/sec, 8829680 t fired, .

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FINAL RESULTS
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ClientsAndServers-PT-N0200P0-CTLFireability-00: CTL false CTL model checker
ClientsAndServers-PT-N0200P0-CTLFireability-01: EFEG true state space /EFEG
ClientsAndServers-PT-N0200P0-CTLFireability-02: EXEG true state space /EXEG
ClientsAndServers-PT-N0200P0-CTLFireability-03: F unknown AGGR
ClientsAndServers-PT-N0200P0-CTLFireability-04: CTL true CTL model checker
ClientsAndServers-PT-N0200P0-CTLFireability-05: F false state space / EG
ClientsAndServers-PT-N0200P0-CTLFireability-06: CTL unknown AGGR
ClientsAndServers-PT-N0200P0-CTLFireability-07: CTL false CTL model checker
ClientsAndServers-PT-N0200P0-CTLFireability-08: CONJ false state space / EG
ClientsAndServers-PT-N0200P0-CTLFireability-09: CTL false CTL model checker
ClientsAndServers-PT-N0200P0-CTLFireability-10: CTL false CTL model checker
ClientsAndServers-PT-N0200P0-CTLFireability-11: CTL unknown AGGR
ClientsAndServers-PT-N0200P0-CTLFireability-12: CTL unknown AGGR
ClientsAndServers-PT-N0200P0-CTLFireability-13: EG unknown AGGR
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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ClientsAndServers-PT-N0200P0"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ClientsAndServers-PT-N0200P0, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-smll-167814397800322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ClientsAndServers-PT-N0200P0.tgz
mv ClientsAndServers-PT-N0200P0 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;