Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r071-smll-167814397600170.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is CircularTrains-PT-096, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-smll-167814397600170
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 540K
-rw-r--r-- 1 mcc users 6.0K Feb 26 04:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 60K Feb 26 04:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.4K Feb 26 04:31 CTLFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 04:31 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K Feb 25 15:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 15:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K Feb 25 15:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 26 04:33 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 131K Feb 26 04:33 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 11K Feb 26 04:33 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 82K Feb 26 04:33 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 73K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CircularTrains-PT-096-CTLFireability-00
FORMULA_NAME CircularTrains-PT-096-CTLFireability-01
FORMULA_NAME CircularTrains-PT-096-CTLFireability-02
FORMULA_NAME CircularTrains-PT-096-CTLFireability-03
FORMULA_NAME CircularTrains-PT-096-CTLFireability-04
FORMULA_NAME CircularTrains-PT-096-CTLFireability-05
FORMULA_NAME CircularTrains-PT-096-CTLFireability-06
FORMULA_NAME CircularTrains-PT-096-CTLFireability-07
FORMULA_NAME CircularTrains-PT-096-CTLFireability-08
FORMULA_NAME CircularTrains-PT-096-CTLFireability-09
FORMULA_NAME CircularTrains-PT-096-CTLFireability-10
FORMULA_NAME CircularTrains-PT-096-CTLFireability-11
FORMULA_NAME CircularTrains-PT-096-CTLFireability-12
FORMULA_NAME CircularTrains-PT-096-CTLFireability-13
FORMULA_NAME CircularTrains-PT-096-CTLFireability-14
FORMULA_NAME CircularTrains-PT-096-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678249855091

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CircularTrains-PT-096
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 04:30:58] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 04:30:58] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 04:30:58] [INFO ] Load time of PNML (sax parser for PT used): 172 ms
[2023-03-08 04:30:58] [INFO ] Transformed 192 places.
[2023-03-08 04:30:58] [INFO ] Transformed 96 transitions.
[2023-03-08 04:30:58] [INFO ] Parsed PT model containing 192 places and 96 transitions and 384 arcs in 384 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 15 ms.
Support contains 144 out of 192 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 192/192 places, 96/96 transitions.
Applied a total of 0 rules in 21 ms. Remains 192 /192 variables (removed 0) and now considering 96/96 (removed 0) transitions.
// Phase 1: matrix 96 rows 192 cols
[2023-03-08 04:30:58] [INFO ] Computed 97 place invariants in 46 ms
[2023-03-08 04:30:59] [INFO ] Implicit Places using invariants in 695 ms returned [4, 10, 109, 123, 125, 185, 189]
Discarding 7 places :
Implicit Place search using SMT only with invariants took 753 ms to find 7 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 185/192 places, 96/96 transitions.
Applied a total of 0 rules in 7 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 782 ms. Remains : 185/192 places, 96/96 transitions.
Support contains 144 out of 185 places after structural reductions.
[2023-03-08 04:30:59] [INFO ] Flatten gal took : 95 ms
[2023-03-08 04:30:59] [INFO ] Flatten gal took : 30 ms
[2023-03-08 04:31:00] [INFO ] Input system was already deterministic with 96 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 450 ms. (steps per millisecond=22 ) properties (out of 78) seen :77
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 66 ms. (steps per millisecond=151 ) properties (out of 1) seen :0
Running SMT prover for 1 properties.
// Phase 1: matrix 96 rows 185 cols
[2023-03-08 04:31:00] [INFO ] Computed 90 place invariants in 15 ms
[2023-03-08 04:31:00] [INFO ] [Real]Absence check using 55 positive place invariants in 22 ms returned sat
[2023-03-08 04:31:00] [INFO ] [Real]Absence check using 55 positive and 35 generalized place invariants in 17 ms returned sat
[2023-03-08 04:31:00] [INFO ] After 173ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0
Fused 1 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 1 atomic propositions for a total of 16 simplifications.
[2023-03-08 04:31:00] [INFO ] Flatten gal took : 20 ms
[2023-03-08 04:31:00] [INFO ] Flatten gal took : 20 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Support contains 134 out of 185 places (down from 140) after GAL structural reductions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 33 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 33 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 17 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 16 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 30 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 30 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 15 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 16 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 8 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 14 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 16 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Drop transitions removed 3 transitions
Trivial Post-agglo rules discarded 3 transitions
Performed 3 trivial Post agglomeration. Transition count delta: 3
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 185 transition count 93
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 1 with 3 rules applied. Total rules applied 6 place count 182 transition count 93
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 4 Pre rules applied. Total rules applied 6 place count 182 transition count 89
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 14 place count 178 transition count 89
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 22 place count 174 transition count 85
Applied a total of 22 rules in 42 ms. Remains 174 /185 variables (removed 11) and now considering 85/96 (removed 11) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 42 ms. Remains : 174/185 places, 85/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 12 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 85 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 7 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 12 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 5 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 12 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 185 transition count 95
Reduce places removed 1 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 2 rules applied. Total rules applied 3 place count 184 transition count 94
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 4 place count 183 transition count 94
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 4 place count 183 transition count 90
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 12 place count 179 transition count 90
Performed 3 Post agglomeration using F-continuation condition.Transition count delta: 3
Deduced a syphon composed of 3 places in 0 ms
Reduce places removed 3 places and 0 transitions.
Iterating global reduction 3 with 6 rules applied. Total rules applied 18 place count 176 transition count 87
Applied a total of 18 rules in 32 ms. Remains 176 /185 variables (removed 9) and now considering 87/96 (removed 9) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 32 ms. Remains : 176/185 places, 87/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 10 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 10 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 87 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 7 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 10 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 6 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 6 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 11 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Drop transitions removed 1 transitions
Trivial Post-agglo rules discarded 1 transitions
Performed 1 trivial Post agglomeration. Transition count delta: 1
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 185 transition count 95
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 1 with 1 rules applied. Total rules applied 2 place count 184 transition count 95
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 5 Pre rules applied. Total rules applied 2 place count 184 transition count 90
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 2 with 10 rules applied. Total rules applied 12 place count 179 transition count 90
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 2 with 8 rules applied. Total rules applied 20 place count 175 transition count 86
Applied a total of 20 rules in 16 ms. Remains 175 /185 variables (removed 10) and now considering 86/96 (removed 10) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 175/185 places, 86/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 86 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:31:01] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 1 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:31:01] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:31:02] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:02] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:31:02] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:31:02] [INFO ] Input system was already deterministic with 96 transitions.
Starting structural reductions in LTL mode, iteration 0 : 185/185 places, 96/96 transitions.
Applied a total of 0 rules in 2 ms. Remains 185 /185 variables (removed 0) and now considering 96/96 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 185/185 places, 96/96 transitions.
[2023-03-08 04:31:02] [INFO ] Flatten gal took : 5 ms
[2023-03-08 04:31:02] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:31:02] [INFO ] Input system was already deterministic with 96 transitions.
[2023-03-08 04:31:02] [INFO ] Flatten gal took : 6 ms
[2023-03-08 04:31:02] [INFO ] Flatten gal took : 7 ms
[2023-03-08 04:31:02] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 5 ms.
[2023-03-08 04:31:02] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 185 places, 96 transitions and 370 arcs took 11 ms.
Total runtime 3974 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT CircularTrains-PT-096
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA CircularTrains-PT-096-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircularTrains-PT-096-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircularTrains-PT-096-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircularTrains-PT-096-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircularTrains-PT-096-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircularTrains-PT-096-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678250359238

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
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16 CTL EXCL 10/211 10/32 CircularTrains-PT-096-CTLFireability-05 2014130 m, 185706 m/sec, 4527379 t fired, .

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16 CTL EXCL 15/211 14/32 CircularTrains-PT-096-CTLFireability-05 2884742 m, 174122 m/sec, 6613501 t fired, .

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CircularTrains-PT-096-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
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CircularTrains-PT-096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 20/3165 13/32 CircularTrains-PT-096-CTLFireability-06 2749114 m, 130701 m/sec, 12648717 t fired, .

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CircularTrains-PT-096-CTLFireability-07: CONJ 0 0 0 0 3 0 1 0
CircularTrains-PT-096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 25/3165 15/32 CircularTrains-PT-096-CTLFireability-06 3380680 m, 126313 m/sec, 15839473 t fired, .

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CircularTrains-PT-096-CTLFireability-09: DISJ true CTL model checker
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CircularTrains-PT-096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/3165 18/32 CircularTrains-PT-096-CTLFireability-06 4031221 m, 130108 m/sec, 18987416 t fired, .

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CircularTrains-PT-096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/3165 21/32 CircularTrains-PT-096-CTLFireability-06 4665178 m, 126791 m/sec, 22159361 t fired, .

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CircularTrains-PT-096-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
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CircularTrains-PT-096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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19 CTL EXCL 40/3165 24/32 CircularTrains-PT-096-CTLFireability-06 5311693 m, 129303 m/sec, 25246520 t fired, .

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CircularTrains-PT-096-CTLFireability-09: DISJ true CTL model checker
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CircularTrains-PT-096-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
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CircularTrains-PT-096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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19 CTL EXCL 45/3165 27/32 CircularTrains-PT-096-CTLFireability-06 5945991 m, 126859 m/sec, 28387171 t fired, .

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CircularTrains-PT-096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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19 CTL EXCL 50/3165 29/32 CircularTrains-PT-096-CTLFireability-06 6558794 m, 122560 m/sec, 31558728 t fired, .

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CircularTrains-PT-096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
CircularTrains-PT-096-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 55/3165 32/32 CircularTrains-PT-096-CTLFireability-06 7157034 m, 119648 m/sec, 34711735 t fired, .

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CircularTrains-PT-096-CTLFireability-09: DISJ true CTL model checker
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CircularTrains-PT-096-CTLFireability-00: CTL false CTL model checker
CircularTrains-PT-096-CTLFireability-01: CTL unknown AGGR
CircularTrains-PT-096-CTLFireability-02: CTL unknown AGGR
CircularTrains-PT-096-CTLFireability-03: CTL unknown AGGR
CircularTrains-PT-096-CTLFireability-04: CTL false CTL model checker
CircularTrains-PT-096-CTLFireability-05: CTL unknown AGGR
CircularTrains-PT-096-CTLFireability-06: CTL unknown AGGR
CircularTrains-PT-096-CTLFireability-07: CONJ unknown CONJ
CircularTrains-PT-096-CTLFireability-08: CTL true CTL model checker
CircularTrains-PT-096-CTLFireability-09: DISJ true CTL model checker
CircularTrains-PT-096-CTLFireability-10: CTL unknown AGGR
CircularTrains-PT-096-CTLFireability-11: CTL false CTL model checker
CircularTrains-PT-096-CTLFireability-12: CTL unknown AGGR
CircularTrains-PT-096-CTLFireability-13: CTL unknown AGGR
CircularTrains-PT-096-CTLFireability-14: CTL false CTL model checker
CircularTrains-PT-096-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CircularTrains-PT-096"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is CircularTrains-PT-096, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-smll-167814397600170"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CircularTrains-PT-096.tgz
mv CircularTrains-PT-096 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;