Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r071-smll-167814397600130.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is CircadianClock-PT-010000, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-smll-167814397600130
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 7.8K Feb 26 10:40 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 26 10:40 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 26 10:36 CTLFireability.txt
-rw-r--r-- 1 mcc users 46K Feb 26 10:36 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Feb 25 15:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 26 10:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 115K Feb 26 10:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 26 10:41 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 26 10:41 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 7 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 11K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-00
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-01
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-02
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-03
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-04
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-05
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-06
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-07
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-08
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-09
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-10
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-11
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-12
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-13
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-14
FORMULA_NAME CircadianClock-PT-010000-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678244798119

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CircadianClock-PT-010000
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-08 03:06:41] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-08 03:06:41] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-08 03:06:41] [INFO ] Load time of PNML (sax parser for PT used): 51 ms
[2023-03-08 03:06:41] [INFO ] Transformed 14 places.
[2023-03-08 03:06:41] [INFO ] Transformed 16 transitions.
[2023-03-08 03:06:41] [INFO ] Parsed PT model containing 14 places and 16 transitions and 58 arcs in 190 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 22 ms.
Initial state reduction rules removed 1 formulas.
FORMULA CircadianClock-PT-010000-CTLFireability-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 14 out of 14 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 20 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
[2023-03-08 03:06:41] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
// Phase 1: matrix 14 rows 14 cols
[2023-03-08 03:06:41] [INFO ] Computed 7 place invariants in 7 ms
[2023-03-08 03:06:42] [INFO ] Implicit Places using invariants in 221 ms returned []
[2023-03-08 03:06:42] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 03:06:42] [INFO ] Invariant cache hit.
[2023-03-08 03:06:42] [INFO ] State equation strengthened by 2 read => feed constraints.
[2023-03-08 03:06:42] [INFO ] Implicit Places using invariants and state equation in 72 ms returned []
Implicit Place search using SMT with State Equation took 356 ms to find 0 implicit places.
[2023-03-08 03:06:42] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 03:06:42] [INFO ] Invariant cache hit.
[2023-03-08 03:06:42] [INFO ] Dead Transitions using invariants and state equation in 63 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 442 ms. Remains : 14/14 places, 16/16 transitions.
Support contains 14 out of 14 places after structural reductions.
[2023-03-08 03:06:42] [INFO ] Flatten gal took : 31 ms
[2023-03-08 03:06:42] [INFO ] Flatten gal took : 12 ms
[2023-03-08 03:06:42] [INFO ] Input system was already deterministic with 16 transitions.
Incomplete random walk after 10001 steps, including 0 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 32) seen :2
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 56 ms. (steps per millisecond=17 ) properties (out of 30) seen :25
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 28 ms. (steps per millisecond=35 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 22 ms. (steps per millisecond=45 ) properties (out of 4) seen :1
Incomplete Best-First random walk after 1000 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=50 ) properties (out of 3) seen :1
Running SMT prover for 2 properties.
[2023-03-08 03:06:42] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 03:06:42] [INFO ] Invariant cache hit.
[2023-03-08 03:06:42] [INFO ] [Real]Absence check using 7 positive place invariants in 4 ms returned sat
[2023-03-08 03:06:42] [INFO ] After 83ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:1
[2023-03-08 03:06:42] [INFO ] [Nat]Absence check using 7 positive place invariants in 4 ms returned sat
[2023-03-08 03:06:42] [INFO ] After 28ms SMT Verify possible using state equation in natural domain returned unsat :1 sat :1
[2023-03-08 03:06:42] [INFO ] State equation strengthened by 2 read => feed constraints.
[2023-03-08 03:06:43] [INFO ] After 7ms SMT Verify possible using 2 Read/Feed constraints in natural domain returned unsat :1 sat :1
[2023-03-08 03:06:43] [INFO ] After 17ms SMT Verify possible using trap constraints in natural domain returned unsat :1 sat :1
Attempting to minimize the solution found.
Minimization took 12 ms.
[2023-03-08 03:06:43] [INFO ] After 112ms SMT Verify possible using all constraints in natural domain returned unsat :1 sat :1
Fused 2 Parikh solutions to 1 different solutions.
Parikh walk visited 0 properties in 3 ms.
Support contains 4 out of 14 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 9 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 9 ms. Remains : 14/14 places, 16/16 transitions.
Incomplete random walk after 10001 steps, including 0 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 1) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 1) seen :0
Interrupted probabilistic random walk after 2017235 steps, run timeout after 3001 ms. (steps per millisecond=672 ) properties seen :{}
Probabilistic random walk after 2017235 steps, saw 1370838 distinct states, run finished after 3002 ms. (steps per millisecond=671 ) properties seen :0
Running SMT prover for 1 properties.
[2023-03-08 03:06:46] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 03:06:46] [INFO ] Invariant cache hit.
[2023-03-08 03:06:46] [INFO ] [Real]Absence check using 7 positive place invariants in 3 ms returned sat
[2023-03-08 03:06:46] [INFO ] After 43ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 03:06:46] [INFO ] [Nat]Absence check using 7 positive place invariants in 3 ms returned sat
[2023-03-08 03:06:46] [INFO ] After 12ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 03:06:46] [INFO ] State equation strengthened by 2 read => feed constraints.
[2023-03-08 03:06:46] [INFO ] After 4ms SMT Verify possible using 2 Read/Feed constraints in natural domain returned unsat :0 sat :1
[2023-03-08 03:06:46] [INFO ] After 10ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 11 ms.
[2023-03-08 03:06:46] [INFO ] After 63ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Parikh walk visited 0 properties in 1 ms.
Support contains 4 out of 14 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 2 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 2 ms. Remains : 14/14 places, 16/16 transitions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 2 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
[2023-03-08 03:06:46] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 03:06:46] [INFO ] Invariant cache hit.
[2023-03-08 03:06:46] [INFO ] Implicit Places using invariants in 36 ms returned []
[2023-03-08 03:06:46] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 03:06:46] [INFO ] Invariant cache hit.
[2023-03-08 03:06:46] [INFO ] State equation strengthened by 2 read => feed constraints.
[2023-03-08 03:06:46] [INFO ] Implicit Places using invariants and state equation in 44 ms returned []
Implicit Place search using SMT with State Equation took 82 ms to find 0 implicit places.
[2023-03-08 03:06:46] [INFO ] Redundant transitions in 13 ms returned []
[2023-03-08 03:06:46] [INFO ] Flow matrix only has 14 transitions (discarded 2 similar events)
[2023-03-08 03:06:46] [INFO ] Invariant cache hit.
[2023-03-08 03:06:46] [INFO ] Dead Transitions using invariants and state equation in 40 ms found 0 transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 143 ms. Remains : 14/14 places, 16/16 transitions.
Graph (trivial) has 5 edges and 14 vertex of which 4 / 14 are part of one of the 2 SCC in 2 ms
Free SCC test removed 2 places
Drop transitions removed 5 transitions
Ensure Unique test removed 1 transitions
Reduce isomorphic transitions removed 6 transitions.
Graph (complete) has 20 edges and 12 vertex of which 7 are kept as prefixes of interest. Removing 5 places using SCC suffix rule.1 ms
Discarding 5 places :
Also discarding 0 output transitions
Reduce places removed 1 places and 0 transitions.
Drop transitions removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Iterating post reduction 0 with 5 rules applied. Total rules applied 7 place count 6 transition count 6
Applied a total of 7 rules in 5 ms. Remains 6 /14 variables (removed 8) and now considering 6/16 (removed 10) transitions.
Running SMT prover for 1 properties.
// Phase 1: matrix 6 rows 6 cols
[2023-03-08 03:06:46] [INFO ] Computed 3 place invariants in 1 ms
[2023-03-08 03:06:46] [INFO ] [Real]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-08 03:06:46] [INFO ] After 32ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:1
[2023-03-08 03:06:46] [INFO ] [Nat]Absence check using 3 positive place invariants in 1 ms returned sat
[2023-03-08 03:06:46] [INFO ] After 6ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :1
[2023-03-08 03:06:46] [INFO ] After 13ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :1
Attempting to minimize the solution found.
Minimization took 3 ms.
[2023-03-08 03:06:46] [INFO ] After 40ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :1
Successfully simplified 1 atomic propositions for a total of 15 simplifications.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 5 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 5 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 7 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 3 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 2 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 3 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 2 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 1 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 1 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 1 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 1 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 1 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 0 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 1 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 2 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 2 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
Starting structural reductions in LTL mode, iteration 0 : 14/14 places, 16/16 transitions.
Applied a total of 0 rules in 1 ms. Remains 14 /14 variables (removed 0) and now considering 16/16 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 14/14 places, 16/16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Input system was already deterministic with 16 transitions.
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 3 ms
[2023-03-08 03:06:46] [INFO ] Flatten gal took : 2 ms
[2023-03-08 03:06:46] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-08 03:06:46] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 14 places, 16 transitions and 58 arcs took 0 ms.
Total runtime 5458 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT CircadianClock-PT-010000
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/373
CTLFireability

FORMULA CircadianClock-PT-010000-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircadianClock-PT-010000-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircadianClock-PT-010000-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircadianClock-PT-010000-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CircadianClock-PT-010000-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678245294081

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/373/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/373/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/373/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
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10 AGEF EXCL 20/1572 24/32 CircadianClock-PT-010000-CTLFireability-03 6397678 m, 286392 m/sec, 25292417 t fired, .

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CircadianClock-PT-010000-CTLFireability-10: CTL false CTL model checker
CircadianClock-PT-010000-CTLFireability-11: EXEF true state space /EXEF
CircadianClock-PT-010000-CTLFireability-12: CTL false CTL model checker
CircadianClock-PT-010000-CTLFireability-14: DISJ true state space / EXEU

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CircadianClock-PT-010000-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-03: AGEF 0 0 1 0 1 0 0 0
CircadianClock-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-08: AGEF 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-09: DISJ 0 0 0 0 2 0 2 0
CircadianClock-PT-010000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 AGEF EXCL 25/1572 29/32 CircadianClock-PT-010000-CTLFireability-03 7783918 m, 277248 m/sec, 31049388 t fired, .

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CircadianClock-PT-010000-CTLFireability-10: CTL false CTL model checker
CircadianClock-PT-010000-CTLFireability-11: EXEF true state space /EXEF
CircadianClock-PT-010000-CTLFireability-12: CTL false CTL model checker
CircadianClock-PT-010000-CTLFireability-14: DISJ true state space / EXEU

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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CircadianClock-PT-010000-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-03: AGEF 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-08: AGEF 0 0 0 0 1 0 1 0
CircadianClock-PT-010000-CTLFireability-09: DISJ 0 0 0 0 2 0 2 0
CircadianClock-PT-010000-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CircadianClock-PT-010000-CTLFireability-00: CTL unknown AGGR
CircadianClock-PT-010000-CTLFireability-01: CTL unknown AGGR
CircadianClock-PT-010000-CTLFireability-02: CTL unknown AGGR
CircadianClock-PT-010000-CTLFireability-03: AGEF unknown AGGR
CircadianClock-PT-010000-CTLFireability-04: CTL unknown AGGR
CircadianClock-PT-010000-CTLFireability-05: CTL unknown AGGR
CircadianClock-PT-010000-CTLFireability-06: CTL unknown AGGR
CircadianClock-PT-010000-CTLFireability-07: CTL unknown AGGR
CircadianClock-PT-010000-CTLFireability-08: AGEF unknown AGGR
CircadianClock-PT-010000-CTLFireability-09: DISJ unknown DISJ
CircadianClock-PT-010000-CTLFireability-10: CTL false CTL model checker
CircadianClock-PT-010000-CTLFireability-11: EXEF true state space /EXEF
CircadianClock-PT-010000-CTLFireability-12: CTL false CTL model checker
CircadianClock-PT-010000-CTLFireability-13: CTL true CTL model checker
CircadianClock-PT-010000-CTLFireability-14: DISJ true state space / EXEU


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CircadianClock-PT-010000"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is CircadianClock-PT-010000, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-smll-167814397600130"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CircadianClock-PT-010000.tgz
mv CircadianClock-PT-010000 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;