Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r071-smll-167814397500042.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is CSRepetitions-COL-10, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r071-smll-167814397500042
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 8.8K Feb 25 12:42 CTLCardinality.txt
-rw-r--r-- 1 mcc users 78K Feb 25 12:42 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 25 12:30 CTLFireability.txt
-rw-r--r-- 1 mcc users 57K Feb 25 12:30 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5.1K Feb 25 15:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 30K Feb 25 15:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 15:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 15:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 25 13:30 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 139K Feb 25 13:30 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.7K Feb 25 13:11 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 59K Feb 25 13:11 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:42 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:42 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 18K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-00
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-01
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-02
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-03
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-04
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-05
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-06
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-07
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-08
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-09
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-10
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-11
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-12
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-13
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-14
FORMULA_NAME CSRepetitions-COL-10-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678227099891

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CSRepetitions-COL-10
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-07 22:11:42] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-07 22:11:43] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-07 22:11:43] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-07 22:11:43] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-07 22:11:44] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 1044 ms
[2023-03-07 22:11:44] [INFO ] Imported 6 HL places and 5 HL transitions for a total of 1311 PT places and 2300.0 transition bindings in 28 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 32 ms.
[2023-03-07 22:11:44] [INFO ] Built PT skeleton of HLPN with 6 places and 5 transitions 15 arcs in 8 ms.
[2023-03-07 22:11:44] [INFO ] Skeletonized 16 HLPN properties in 5 ms.
Computed a total of 0 stabilizing places and 1 stable transitions
Remains 6 properties that can be checked using skeleton over-approximation.
Computed a total of 0 stabilizing places and 1 stable transitions
Finished random walk after 237 steps, including 1 resets, run visited all 9 properties in 16 ms. (steps per millisecond=14 )
[2023-03-07 22:11:44] [INFO ] Flatten gal took : 28 ms
[2023-03-07 22:11:44] [INFO ] Flatten gal took : 4 ms
Transition Send_Answer forces synchronizations/join behavior on parameter c of sort Client
Symmetric sort wr.t. initial and guards and successors and join/free detected :Server
Symmetric sort wr.t. initial detected :Server
Symmetric sort wr.t. initial and guards detected :Server
Applying symmetric unfolding of full symmetric sort :Server domain size was 10
[2023-03-07 22:11:44] [INFO ] Unfolded HLPN to a Petri net with 402 places and 500 transitions 1500 arcs in 47 ms.
[2023-03-07 22:11:44] [INFO ] Unfolded 16 HLPN properties in 6 ms.
Support contains 402 out of 402 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 24 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
// Phase 1: matrix 500 rows 402 cols
[2023-03-07 22:11:44] [INFO ] Computed 101 place invariants in 56 ms
[2023-03-07 22:11:45] [INFO ] Implicit Places using invariants in 518 ms returned []
[2023-03-07 22:11:45] [INFO ] Invariant cache hit.
[2023-03-07 22:11:45] [INFO ] State equation strengthened by 100 read => feed constraints.
[2023-03-07 22:11:46] [INFO ] Implicit Places using invariants and state equation in 589 ms returned []
Implicit Place search using SMT with State Equation took 1164 ms to find 0 implicit places.
[2023-03-07 22:11:46] [INFO ] Invariant cache hit.
[2023-03-07 22:11:46] [INFO ] Dead Transitions using invariants and state equation in 697 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1901 ms. Remains : 402/402 places, 500/500 transitions.
Support contains 402 out of 402 places after structural reductions.
[2023-03-07 22:11:47] [INFO ] Flatten gal took : 132 ms
[2023-03-07 22:11:48] [INFO ] Flatten gal took : 143 ms
[2023-03-07 22:11:48] [INFO ] Input system was already deterministic with 500 transitions.
Finished random walk after 150 steps, including 0 resets, run visited all 29 properties in 108 ms. (steps per millisecond=1 )
[2023-03-07 22:11:49] [INFO ] Flatten gal took : 60 ms
[2023-03-07 22:11:49] [INFO ] Flatten gal took : 111 ms
[2023-03-07 22:11:50] [INFO ] Input system was already deterministic with 500 transitions.
Computed a total of 0 stabilizing places and 100 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 13 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:50] [INFO ] Flatten gal took : 24 ms
[2023-03-07 22:11:50] [INFO ] Flatten gal took : 25 ms
[2023-03-07 22:11:50] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 35 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 37 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:50] [INFO ] Flatten gal took : 20 ms
[2023-03-07 22:11:50] [INFO ] Flatten gal took : 21 ms
[2023-03-07 22:11:50] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 4 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:50] [INFO ] Flatten gal took : 20 ms
[2023-03-07 22:11:50] [INFO ] Flatten gal took : 24 ms
[2023-03-07 22:11:50] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 33 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 34 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:50] [INFO ] Flatten gal took : 19 ms
[2023-03-07 22:11:50] [INFO ] Flatten gal took : 22 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 3 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 20 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 27 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 3 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 22 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 31 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 30 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 31 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 15 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 15 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 4 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 16 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 20 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 4 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 13 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 14 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 8 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 13 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 15 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 16 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 15 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 20 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 3 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 15 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 21 ms
[2023-03-07 22:11:51] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 17 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 19 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 16 ms
[2023-03-07 22:11:51] [INFO ] Flatten gal took : 20 ms
[2023-03-07 22:11:52] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 14 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:52] [INFO ] Flatten gal took : 14 ms
[2023-03-07 22:11:52] [INFO ] Flatten gal took : 19 ms
[2023-03-07 22:11:52] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 14 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 15 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:52] [INFO ] Flatten gal took : 15 ms
[2023-03-07 22:11:52] [INFO ] Flatten gal took : 20 ms
[2023-03-07 22:11:52] [INFO ] Input system was already deterministic with 500 transitions.
Starting structural reductions in LTL mode, iteration 0 : 402/402 places, 500/500 transitions.
Applied a total of 0 rules in 3 ms. Remains 402 /402 variables (removed 0) and now considering 500/500 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 402/402 places, 500/500 transitions.
[2023-03-07 22:11:52] [INFO ] Flatten gal took : 14 ms
[2023-03-07 22:11:52] [INFO ] Flatten gal took : 17 ms
[2023-03-07 22:11:52] [INFO ] Input system was already deterministic with 500 transitions.
[2023-03-07 22:11:52] [INFO ] Flatten gal took : 92 ms
[2023-03-07 22:11:53] [INFO ] Flatten gal took : 93 ms
[2023-03-07 22:11:53] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 80 ms.
[2023-03-07 22:11:53] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 402 places, 500 transitions and 1500 arcs took 3 ms.
Total runtime 10622 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT CSRepetitions-COL-10
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/372
CTLFireability

FORMULA CSRepetitions-COL-10-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-10-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678227368375

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/372/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/372/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/372/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 92 (type SKEL/SRCH) for 6 CSRepetitions-COL-10-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 93 (type SKEL/SRCH) for 6 CSRepetitions-COL-10-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 92 (type SKEL/SRCH) for CSRepetitions-COL-10-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 93 (type SKEL/SRCH) for CSRepetitions-COL-10-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 94 (type SKEL/SRCH) for 6 CSRepetitions-COL-10-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 94 (type SKEL/SRCH) for CSRepetitions-COL-10-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 95 (type SKEL/SRCH) for 6 CSRepetitions-COL-10-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 95 (type SKEL/SRCH) for CSRepetitions-COL-10-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 4 (type EXCL) for 3 CSRepetitions-COL-10-CTLFireability-01
lola: time limit : 98 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 4 (type EXCL) for CSRepetitions-COL-10-CTLFireability-01
lola: result : true
lola: markings : 120
lola: fired transitions : 250
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 CSRepetitions-COL-10-CTLFireability-04
lola: time limit : 101 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for CSRepetitions-COL-10-CTLFireability-04
lola: result : true
lola: markings : 121
lola: fired transitions : 424
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 98 (type EXCL) for 81 CSRepetitions-COL-10-CTLFireability-15
lola: time limit : 104 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 96 (type FNDP) for 81 CSRepetitions-COL-10-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 97 (type EQUN) for 81 CSRepetitions-COL-10-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 99 (type SRCH) for 81 CSRepetitions-COL-10-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 98 (type EXCL) for CSRepetitions-COL-10-CTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 96 (type FNDP) for CSRepetitions-COL-10-CTLFireability-15 (obsolete)
lola: CANCELED task # 97 (type EQUN) for CSRepetitions-COL-10-CTLFireability-15 (obsolete)
lola: CANCELED task # 99 (type SRCH) for CSRepetitions-COL-10-CTLFireability-15 (obsolete)
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 96 (type FNDP) for CSRepetitions-COL-10-CTLFireability-15
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 40 (type EXCL) for 37 CSRepetitions-COL-10-CTLFireability-03
lola: time limit : 131 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 40 (type EXCL) for CSRepetitions-COL-10-CTLFireability-03
lola: result : true
lola: markings : 124
lola: fired transitions : 493
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
sara: try reading problem file /home/mcc/execution/372/CTLFireability-97.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: place or transition ordering is non-deterministic
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 61 (type EXCL) for 60 CSRepetitions-COL-10-CTLFireability-08
lola: time limit : 136 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for CSRepetitions-COL-10-CTLFireability-08
lola: result : true
lola: markings : 123
lola: fired transitions : 262
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 51 CSRepetitions-COL-10-CTLFireability-05
lola: time limit : 142 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806

lola: FINISHED task # 97 (type EQUN) for CSRepetitions-COL-10-CTLFireability-15
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 101 (type SKEL/SRCH) for 6 CSRepetitions-COL-10-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 101 (type SKEL/SRCH) for CSRepetitions-COL-10-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 4/209 2/32 CSRepetitions-COL-10-CTLFireability-05 201746 m, 40349 m/sec, 541541 t fired, .

Time elapsed: 48 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 9/209 4/32 CSRepetitions-COL-10-CTLFireability-05 477064 m, 55063 m/sec, 1288087 t fired, .

Time elapsed: 53 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 14/209 6/32 CSRepetitions-COL-10-CTLFireability-05 744290 m, 53445 m/sec, 2033239 t fired, .

Time elapsed: 58 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 19/209 8/32 CSRepetitions-COL-10-CTLFireability-05 1005277 m, 52197 m/sec, 2832961 t fired, .

Time elapsed: 63 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 24/209 10/32 CSRepetitions-COL-10-CTLFireability-05 1296076 m, 58159 m/sec, 3599265 t fired, .

Time elapsed: 68 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 29/209 12/32 CSRepetitions-COL-10-CTLFireability-05 1555329 m, 51850 m/sec, 4277110 t fired, .

Time elapsed: 73 secs. Pages in use: 12
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 34/209 14/32 CSRepetitions-COL-10-CTLFireability-05 1812673 m, 51468 m/sec, 4965064 t fired, .

Time elapsed: 78 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 39/209 16/32 CSRepetitions-COL-10-CTLFireability-05 2074571 m, 52379 m/sec, 5698028 t fired, .

Time elapsed: 83 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 44/209 18/32 CSRepetitions-COL-10-CTLFireability-05 2353824 m, 55850 m/sec, 6480522 t fired, .

Time elapsed: 88 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 49/209 20/32 CSRepetitions-COL-10-CTLFireability-05 2602088 m, 49652 m/sec, 7127418 t fired, .

Time elapsed: 93 secs. Pages in use: 20
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 54/209 21/32 CSRepetitions-COL-10-CTLFireability-05 2847469 m, 49076 m/sec, 7778686 t fired, .

Time elapsed: 98 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 59/209 23/32 CSRepetitions-COL-10-CTLFireability-05 3097769 m, 50060 m/sec, 8463630 t fired, .

Time elapsed: 103 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 64/209 25/32 CSRepetitions-COL-10-CTLFireability-05 3362462 m, 52938 m/sec, 9237152 t fired, .

Time elapsed: 108 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 69/209 27/32 CSRepetitions-COL-10-CTLFireability-05 3621686 m, 51844 m/sec, 9910377 t fired, .

Time elapsed: 113 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 74/209 29/32 CSRepetitions-COL-10-CTLFireability-05 3867762 m, 49215 m/sec, 10559738 t fired, .

Time elapsed: 118 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 79/209 30/32 CSRepetitions-COL-10-CTLFireability-05 4116844 m, 49816 m/sec, 11234396 t fired, .

Time elapsed: 123 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 84/209 32/32 CSRepetitions-COL-10-CTLFireability-05 4372122 m, 51055 m/sec, 11993375 t fired, .

Time elapsed: 128 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for CSRepetitions-COL-10-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-02: CONJ 0 3 0 0 12 0 0 1
CSRepetitions-COL-10-CTLFireability-03: CONJ 0 2 0 0 4 0 0 0
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-15: DISJ 0 2 0 0 6 0 0 1

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 133 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 88 (type EXCL) for 81 CSRepetitions-COL-10-CTLFireability-15
lola: time limit : 216 sec
lola: memory limit: 32 pages
lola: FINISHED task # 88 (type EXCL) for CSRepetitions-COL-10-CTLFireability-15
lola: result : true
lola: markings : 119
lola: fired transitions : 237
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 70 (type EXCL) for 69 CSRepetitions-COL-10-CTLFireability-11
lola: time limit : 247 sec
lola: memory limit: 32 pages
lola: FINISHED task # 70 (type EXCL) for CSRepetitions-COL-10-CTLFireability-11
lola: result : true
lola: markings : 140
lola: fired transitions : 149
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 64 (type EXCL) for 63 CSRepetitions-COL-10-CTLFireability-09
lola: time limit : 266 sec
lola: memory limit: 32 pages
lola: FINISHED task # 64 (type EXCL) for CSRepetitions-COL-10-CTLFireability-09
lola: result : true
lola: markings : 101
lola: fired transitions : 100
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 57 CSRepetitions-COL-10-CTLFireability-07
lola: time limit : 288 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for CSRepetitions-COL-10-CTLFireability-07
lola: result : false
lola: markings : 121
lola: fired transitions : 249
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 6 CSRepetitions-COL-10-CTLFireability-02
lola: time limit : 315 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for CSRepetitions-COL-10-CTLFireability-02
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 6 CSRepetitions-COL-10-CTLFireability-02
lola: time limit : 346 sec
lola: memory limit: 32 pages
lola: FINISHED task # 13 (type EXCL) for CSRepetitions-COL-10-CTLFireability-02
lola: result : true
lola: markings : 10001
lola: fired transitions : 14851
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 6 CSRepetitions-COL-10-CTLFireability-02
lola: time limit : 385 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for CSRepetitions-COL-10-CTLFireability-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 CSRepetitions-COL-10-CTLFireability-00
lola: time limit : 433 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for CSRepetitions-COL-10-CTLFireability-00
lola: result : true
lola: markings : 123
lola: fired transitions : 268
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 100 (type EXCL) for 37 CSRepetitions-COL-10-CTLFireability-03
lola: time limit : 495 sec
lola: memory limit: 32 pages
lola: FINISHED task # 100 (type EXCL) for CSRepetitions-COL-10-CTLFireability-03
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 55 (type EXCL) for 54 CSRepetitions-COL-10-CTLFireability-06
lola: time limit : 693 sec
lola: memory limit: 32 pages
lola: FINISHED task # 55 (type EXCL) for CSRepetitions-COL-10-CTLFireability-06
lola: result : false
lola: markings : 121
lola: fired transitions : 241
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 76 (type EXCL) for 75 CSRepetitions-COL-10-CTLFireability-13
lola: time limit : 866 sec
lola: memory limit: 32 pages
lola: FINISHED task # 76 (type EXCL) for CSRepetitions-COL-10-CTLFireability-13
lola: result : true
lola: markings : 5052
lola: fired transitions : 5352
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 67 (type EXCL) for 66 CSRepetitions-COL-10-CTLFireability-10
lola: time limit : 1155 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 5/1155 2/32 CSRepetitions-COL-10-CTLFireability-10 260565 m, 52113 m/sec, 1596161 t fired, .

Time elapsed: 138 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 10/1155 4/32 CSRepetitions-COL-10-CTLFireability-10 518837 m, 51654 m/sec, 3384511 t fired, .

Time elapsed: 143 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 15/1155 5/32 CSRepetitions-COL-10-CTLFireability-10 766103 m, 49453 m/sec, 5164120 t fired, .

Time elapsed: 148 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 20/1155 7/32 CSRepetitions-COL-10-CTLFireability-10 1003024 m, 47384 m/sec, 6939343 t fired, .

Time elapsed: 153 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 25/1155 8/32 CSRepetitions-COL-10-CTLFireability-10 1227076 m, 44810 m/sec, 8694539 t fired, .

Time elapsed: 158 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 30/1155 9/32 CSRepetitions-COL-10-CTLFireability-10 1463557 m, 47296 m/sec, 10453702 t fired, .

Time elapsed: 163 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 35/1155 11/32 CSRepetitions-COL-10-CTLFireability-10 1699324 m, 47153 m/sec, 12212390 t fired, .

Time elapsed: 168 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 40/1155 12/32 CSRepetitions-COL-10-CTLFireability-10 1916260 m, 43387 m/sec, 13952178 t fired, .

Time elapsed: 173 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 45/1155 14/32 CSRepetitions-COL-10-CTLFireability-10 2136498 m, 44047 m/sec, 15698934 t fired, .

Time elapsed: 178 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 50/1155 15/32 CSRepetitions-COL-10-CTLFireability-10 2352722 m, 43244 m/sec, 17484514 t fired, .

Time elapsed: 183 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 55/1155 16/32 CSRepetitions-COL-10-CTLFireability-10 2555407 m, 40537 m/sec, 19264060 t fired, .

Time elapsed: 188 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 60/1155 18/32 CSRepetitions-COL-10-CTLFireability-10 2792277 m, 47374 m/sec, 21068274 t fired, .

Time elapsed: 193 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 65/1155 19/32 CSRepetitions-COL-10-CTLFireability-10 3032979 m, 48140 m/sec, 22874337 t fired, .

Time elapsed: 198 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 70/1155 20/32 CSRepetitions-COL-10-CTLFireability-10 3252577 m, 43919 m/sec, 24660304 t fired, .

Time elapsed: 203 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 75/1155 22/32 CSRepetitions-COL-10-CTLFireability-10 3482816 m, 46047 m/sec, 26457566 t fired, .

Time elapsed: 208 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 80/1155 23/32 CSRepetitions-COL-10-CTLFireability-10 3696222 m, 42681 m/sec, 28243167 t fired, .

Time elapsed: 213 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 85/1155 24/32 CSRepetitions-COL-10-CTLFireability-10 3893895 m, 39534 m/sec, 30010074 t fired, .

Time elapsed: 218 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 90/1155 26/32 CSRepetitions-COL-10-CTLFireability-10 4116779 m, 44576 m/sec, 31790763 t fired, .

Time elapsed: 223 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 95/1155 27/32 CSRepetitions-COL-10-CTLFireability-10 4329145 m, 42473 m/sec, 33556302 t fired, .

Time elapsed: 228 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 100/1155 28/32 CSRepetitions-COL-10-CTLFireability-10 4528172 m, 39805 m/sec, 35311075 t fired, .

Time elapsed: 233 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 105/1155 29/32 CSRepetitions-COL-10-CTLFireability-10 4730326 m, 40430 m/sec, 37072911 t fired, .

Time elapsed: 238 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 110/1155 30/32 CSRepetitions-COL-10-CTLFireability-10 4921323 m, 38199 m/sec, 38826404 t fired, .

Time elapsed: 243 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
67 CTL EXCL 115/1155 32/32 CSRepetitions-COL-10-CTLFireability-10 5110633 m, 37862 m/sec, 40570960 t fired, .

Time elapsed: 248 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 67 (type EXCL) for CSRepetitions-COL-10-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-10-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
CSRepetitions-COL-10-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-10-CTLFireability-14: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 253 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 79 (type EXCL) for 78 CSRepetitions-COL-10-CTLFireability-14
lola: time limit : 1673 sec
lola: memory limit: 32 pages
lola: FINISHED task # 79 (type EXCL) for CSRepetitions-COL-10-CTLFireability-14
lola: result : false
lola: markings : 15862
lola: fired transitions : 48057
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 73 (type EXCL) for 72 CSRepetitions-COL-10-CTLFireability-12
lola: time limit : 3347 sec
lola: memory limit: 32 pages
lola: FINISHED task # 73 (type EXCL) for CSRepetitions-COL-10-CTLFireability-12
lola: result : false
lola: markings : 5071
lola: fired transitions : 5662
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-10-CTLFireability-00: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-01: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-02: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-03: CONJ true CONJ
CSRepetitions-COL-10-CTLFireability-04: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-05: CTL unknown AGGR
CSRepetitions-COL-10-CTLFireability-06: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-07: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-08: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-09: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-10: CTL unknown AGGR
CSRepetitions-COL-10-CTLFireability-11: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-12: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-13: CTL true CTL model checker
CSRepetitions-COL-10-CTLFireability-14: CTL false CTL model checker
CSRepetitions-COL-10-CTLFireability-15: DISJ true DISJ


Time elapsed: 253 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CSRepetitions-COL-10"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is CSRepetitions-COL-10, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r071-smll-167814397500042"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CSRepetitions-COL-10.tgz
mv CSRepetitions-COL-10 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;