fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r070-smll-167814396600028
Last Updated
May 14, 2023

About the Execution of LoLA for CSRepetitions-COL-05

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
1909.504 80229.00 80038.00 1381.20 FFFFFFFTTTFFFFFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r070-smll-167814396600028.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is CSRepetitions-COL-05, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r070-smll-167814396600028
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 524K
-rw-r--r-- 1 mcc users 8.6K Feb 25 11:59 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 25 11:59 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.3K Feb 25 11:56 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 25 11:56 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 15:41 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:41 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Feb 25 15:41 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:41 LTLFireability.xml
-rw-r--r-- 1 mcc users 12K Feb 25 12:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 95K Feb 25 12:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 18K Feb 25 12:09 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 136K Feb 25 12:09 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:41 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:41 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 15K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-00
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-01
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-02
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-03
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-04
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-05
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-06
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-07
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-08
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-09
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-10
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-11
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-12
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-13
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-14
FORMULA_NAME CSRepetitions-COL-05-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678227676202

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=CSRepetitions-COL-05
Not applying reductions.
Model is COL
LTLFireability PT
[2023-03-07 22:21:19] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, LTLFireability, --reduce-single, STATESPACE]
[2023-03-07 22:21:19] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-07 22:21:19] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-07 22:21:20] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-07 22:21:20] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 1072 ms
[2023-03-07 22:21:20] [INFO ] Imported 6 HL places and 5 HL transitions for a total of 206 PT places and 325.0 transition bindings in 25 ms.
Parsed 16 properties from file ./LTLFireability.xml in 23 ms.
[2023-03-07 22:21:20] [INFO ] Unfolded HLPN to a Petri net with 206 places and 325 transitions 1175 arcs in 64 ms.
[2023-03-07 22:21:20] [INFO ] Unfolded 16 HLPN properties in 2 ms.
Initial state reduction rules removed 4 formulas.
[2023-03-07 22:21:20] [INFO ] Export to MCC of 16 properties in file ./LTLFireability.STATESPACE.xml took 67 ms.
[2023-03-07 22:21:20] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 206 places, 325 transitions and 1175 arcs took 7 ms.
Total runtime 1609 ms.
starting LoLA
BK_INPUT CSRepetitions-COL-05
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfLTLFireability
LTLCardinality

FORMULA CSRepetitions-COL-05-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA CSRepetitions-COL-05-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678227756431

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfLTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfLTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfLTLFireability/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 14 (type CNST) for 13 CSRepetitions-COL-05-LTLFireability-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 33 (type CNST) for 32 CSRepetitions-COL-05-LTLFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 36 (type CNST) for 35 CSRepetitions-COL-05-LTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 39 (type CNST) for 38 CSRepetitions-COL-05-LTLFireability-10
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 39 (type CNST) for CSRepetitions-COL-05-LTLFireability-10
lola: result : false
lola: FINISHED task # 33 (type CNST) for CSRepetitions-COL-05-LTLFireability-08
lola: result : true
lola: FINISHED task # 36 (type CNST) for CSRepetitions-COL-05-LTLFireability-09
lola: result : true
lola: FINISHED task # 14 (type CNST) for CSRepetitions-COL-05-LTLFireability-03
lola: result : false
lola: LAUNCH INITIAL
lola: LAUNCH task # 45 (type CNST) for 44 CSRepetitions-COL-05-LTLFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 8 (type EXCL) for 7 CSRepetitions-COL-05-LTLFireability-01
lola: time limit : 199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type CNST) for CSRepetitions-COL-05-LTLFireability-12
lola: result : false
lola: FINISHED task # 8 (type EXCL) for CSRepetitions-COL-05-LTLFireability-01
lola: result : false
lola: markings : 20
lola: fired transitions : 26
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 CSRepetitions-COL-05-LTLFireability-02
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for CSRepetitions-COL-05-LTLFireability-02
lola: result : false
lola: markings : 44
lola: fired transitions : 44
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 3 (type EXCL) for 0 CSRepetitions-COL-05-LTLFireability-00
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 5/326 3/32 CSRepetitions-COL-05-LTLFireability-00 407572 m, 81514 m/sec, 2719199 t fired, .

Time elapsed: 9 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 10/326 6/32 CSRepetitions-COL-05-LTLFireability-00 796974 m, 77880 m/sec, 5643865 t fired, .

Time elapsed: 14 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 15/326 9/32 CSRepetitions-COL-05-LTLFireability-00 1178098 m, 76224 m/sec, 8565971 t fired, .

Time elapsed: 19 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 20/326 11/32 CSRepetitions-COL-05-LTLFireability-00 1541352 m, 72650 m/sec, 11506532 t fired, .

Time elapsed: 24 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 25/326 14/32 CSRepetitions-COL-05-LTLFireability-00 1877971 m, 67323 m/sec, 14415915 t fired, .

Time elapsed: 29 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 30/326 16/32 CSRepetitions-COL-05-LTLFireability-00 2228095 m, 70024 m/sec, 17095636 t fired, .

Time elapsed: 34 secs. Pages in use: 16
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 35/326 18/32 CSRepetitions-COL-05-LTLFireability-00 2576537 m, 69688 m/sec, 19985673 t fired, .

Time elapsed: 39 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 40/326 21/32 CSRepetitions-COL-05-LTLFireability-00 2911839 m, 67060 m/sec, 22856392 t fired, .

Time elapsed: 44 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 45/326 23/32 CSRepetitions-COL-05-LTLFireability-00 3234272 m, 64486 m/sec, 25723892 t fired, .

Time elapsed: 49 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 50/326 25/32 CSRepetitions-COL-05-LTLFireability-00 3543319 m, 61809 m/sec, 28566375 t fired, .

Time elapsed: 54 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 55/326 27/32 CSRepetitions-COL-05-LTLFireability-00 3887531 m, 68842 m/sec, 31438254 t fired, .

Time elapsed: 59 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 60/326 30/32 CSRepetitions-COL-05-LTLFireability-00 4248708 m, 72235 m/sec, 34334109 t fired, .

Time elapsed: 64 secs. Pages in use: 30
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 1 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
3 LTL EXCL 65/326 32/32 CSRepetitions-COL-05-LTLFireability-00 4575396 m, 65337 m/sec, 37213919 t fired, .

Time elapsed: 69 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 3 (type EXCL) for CSRepetitions-COL-05-LTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
CSRepetitions-COL-05-LTLFireability-00: CONJ 0 1 0 0 2 0 1 0
CSRepetitions-COL-05-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-05: CONJ 0 2 0 0 2 0 0 0
CSRepetitions-COL-05-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-13: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
CSRepetitions-COL-05-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 74 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 54 (type EXCL) for 53 CSRepetitions-COL-05-LTLFireability-15
lola: time limit : 352 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for CSRepetitions-COL-05-LTLFireability-15
lola: result : false
lola: markings : 39
lola: fired transitions : 41
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 CSRepetitions-COL-05-LTLFireability-14
lola: time limit : 391 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for CSRepetitions-COL-05-LTLFireability-14
lola: result : false
lola: markings : 36
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 CSRepetitions-COL-05-LTLFireability-13
lola: time limit : 440 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for CSRepetitions-COL-05-LTLFireability-13
lola: result : false
lola: markings : 88
lola: fired transitions : 113
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 CSRepetitions-COL-05-LTLFireability-11
lola: time limit : 503 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for CSRepetitions-COL-05-LTLFireability-11
lola: result : false
lola: markings : 90
lola: fired transitions : 90
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 CSRepetitions-COL-05-LTLFireability-07
lola: time limit : 587 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for CSRepetitions-COL-05-LTLFireability-07
lola: result : true
lola: markings : 26
lola: fired transitions : 25
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 CSRepetitions-COL-05-LTLFireability-06
lola: time limit : 705 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for CSRepetitions-COL-05-LTLFireability-06
lola: result : false
lola: markings : 36
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 19 CSRepetitions-COL-05-LTLFireability-05
lola: time limit : 881 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for CSRepetitions-COL-05-LTLFireability-05
lola: result : false
lola: markings : 36
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 CSRepetitions-COL-05-LTLFireability-04
lola: time limit : 1763 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for CSRepetitions-COL-05-LTLFireability-04
lola: result : false
lola: markings : 36
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 5 (type EXCL) for 0 CSRepetitions-COL-05-LTLFireability-00
lola: time limit : 3526 sec
lola: memory limit: 32 pages
lola: FINISHED task # 5 (type EXCL) for CSRepetitions-COL-05-LTLFireability-00
lola: result : false
lola: markings : 60
lola: fired transitions : 60
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
CSRepetitions-COL-05-LTLFireability-00: CONJ false LTL model checker
CSRepetitions-COL-05-LTLFireability-01: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-02: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-03: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-04: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-05: CONJ false LTL model checker
CSRepetitions-COL-05-LTLFireability-06: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-07: LTL true LTL model checker
CSRepetitions-COL-05-LTLFireability-08: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-09: INITIAL true preprocessing
CSRepetitions-COL-05-LTLFireability-10: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-11: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-12: INITIAL false preprocessing
CSRepetitions-COL-05-LTLFireability-13: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-14: LTL false LTL model checker
CSRepetitions-COL-05-LTLFireability-15: LTL false LTL model checker


Time elapsed: 74 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="CSRepetitions-COL-05"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is CSRepetitions-COL-05, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r070-smll-167814396600028"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/CSRepetitions-COL-05.tgz
mv CSRepetitions-COL-05 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;