Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r011-oct2-167813599600006.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................
=====================================================================
Generated by BenchKit 2-5348
Executing tool smartxred
Input is ARMCacheCoherence-PT-none, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r011-oct2-167813599600006
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 6.6K Feb 25 21:34 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 25 21:34 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 21:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 21:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 21:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 163K Feb 25 21:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 25 21:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 21:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:28 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 14M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-00
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-01
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-02
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-03
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-04
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-05
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-06
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-07
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-08
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-09
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-10
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-11
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-12
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-13
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-14
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityCardinality-15

=== Now, execution of the tool begins

BK_START 1678719069932

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=smartxred
BK_EXAMINATION=ReachabilityCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ARMCacheCoherence-PT-none
Applying reductions before tool smart
Invoking reducer
Running Version 202303021504
[2023-03-13 14:51:12] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityCardinality, -timeout, 360, -rebuildPNML]
[2023-03-13 14:51:12] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-13 14:51:12] [INFO ] Load time of PNML (sax parser for PT used): 874 ms
[2023-03-13 14:51:13] [INFO ] Transformed 87 places.
[2023-03-13 14:51:13] [INFO ] Transformed 33676 transitions.
[2023-03-13 14:51:13] [INFO ] Found NUPN structural information;
[2023-03-13 14:51:13] [INFO ] Parsed PT model containing 87 places and 33676 transitions and 246935 arcs in 1130 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityCardinality.xml in 37 ms.
Working with output stream class java.io.PrintStream
Ensure Unique test removed 32425 transitions
Reduce redundant transitions removed 32425 transitions.
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-02 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-03 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-09 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-11 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Incomplete random walk after 10000 steps, including 6 resets, run finished after 457 ms. (steps per millisecond=21 ) properties (out of 10) seen :3
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-13 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-10 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-05 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 44 ms. (steps per millisecond=227 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10000 steps, including 4 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 64 ms. (steps per millisecond=156 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 5 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 7) seen :1
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-14 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 6) seen :1
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-15 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Running SMT prover for 5 properties.
[2023-03-13 14:51:14] [INFO ] Flow matrix only has 500 transitions (discarded 751 similar events)
// Phase 1: matrix 500 rows 87 cols
[2023-03-13 14:51:14] [INFO ] Computed 12 place invariants in 9 ms
[2023-03-13 14:51:14] [INFO ] After 256ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:5
[2023-03-13 14:51:14] [INFO ] [Nat]Absence check using 12 positive place invariants in 6 ms returned sat
[2023-03-13 14:51:14] [INFO ] After 112ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :0
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-12 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-08 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-07 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-01 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityCardinality-00 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 5 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
All properties solved without resorting to model-checking.
Total runtime 2650 ms.
======================================================
========== this is Smart for the MCC'2018 ============
======================================================
Running ARMCacheCoherence (PT), instance none
Examination ReachabilityCardinality
Parser /home/mcc/BenchKit/bin//../reducer/bin//../../smart/bin//parser/Cardinality.jar
Model checker /home/mcc/BenchKit/bin//../reducer/bin//../../smart/bin//rem_exec//smart

GOT IT HERE. BS
Petri model created: 87 places, 33676 transitions, 246935 arcs.
Final Score: 8789.07
Took : 1316 seconds
Reachability Cardinality file is: ReachabilityCardinality.xml
READY TO PARSE. BS
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-00 (reachable &!potential( ( ( (tk(P1)) <= ( 0 ) ) | ( ( (! ( ( 1 ) <= (tk(P79)) )) | ( (tk(P18)) <= ( 0 ) ) ) | (! ( (tk(P78)) <= (tk(P50)) )) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-01 (reachable & potential(( ( ( (tk(P35)) <= ( 0 ) ) & ( (! ( (! ( ( ( ( (tk(P17)) <= (tk(P62)) ) | ( (tk(P32)) <= (tk(P7)) ) ) & ( ( (tk(P55)) <= (tk(P3)) ) | ( ( 1 ) <= (tk(P6)) ) ) ) & ( ( ( 1 ) <= (tk(P81)) ) & ( ( (tk(P72)) <= (tk(P62)) ) & ( (tk(P13)) <= ( 1 ) ) ) ) )) | ( (! ( ( (tk(P62)) <= (tk(P69)) ) & ( (tk(P50)) <= ( 1 ) ) )) | (! ( ( 1 ) <= (tk(P27)) )) ) )) & ( ( ( (tk(P37)) <= (tk(P46)) ) & (! ( ( ( (tk(P75)) <= (tk(P12)) ) | ( ( 1 ) <= (tk(P67)) ) ) & ( ( (tk(P10)) <= (tk(P10)) ) | ( (tk(P6)) <= ( 1 ) ) ) )) ) & ( ( 1 ) <= (tk(P83)) ) ) ) ) & ( (tk(P5)) <= (tk(P32)) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-02 (reachable & potential((! ( ( ( (tk(P5)) <= (tk(P38)) ) | (! ( (tk(P57)) <= (tk(P45)) )) ) | ( ( (tk(P15)) <= ( 1 ) ) | ( (! ( (tk(P83)) <= (tk(P75)) )) | ( ( 1 ) <= (tk(P13)) ) ) ) ))))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-03 (reachable &!potential( ( ( (tk(P28)) <= (tk(P45)) ) | ( ( (tk(P81)) <= (tk(P15)) ) | ( (tk(P70)) <= ( 1 ) ) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-04 (reachable &!potential( ( (tk(P13)) <= ( 1 ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-05 (reachable &!potential( ( ( (tk(P15)) <= (tk(P68)) ) | ( ( 1 ) <= (tk(P70)) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-06 (reachable &!potential( ( (tk(P73)) <= (tk(P73)) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-07 (reachable & potential(( ( ( 1 ) <= (tk(P67)) ) & ( ( 1 ) <= (tk(P69)) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-08 (reachable &!potential( ( ( ( ( 1 ) <= (tk(P3)) ) & ( (! ( (! ( ( (! ( ( 1 ) <= (tk(P59)) )) & ( ( ( 1 ) <= (tk(P50)) ) | ( (tk(P38)) <= ( 0 ) ) ) ) & ( (! ( (tk(P53)) <= ( 0 ) )) & (! ( (tk(P82)) <= (tk(P74)) )) ) )) | (! ( (! ( ( (tk(P56)) <= (tk(P10)) ) & ( (tk(P55)) <= ( 1 ) ) )) & ( ( (tk(P8)) <= (tk(P79)) ) & (! ( (tk(P82)) <= ( 1 ) )) ) )) )) | ( ( 1 ) <= (tk(P48)) ) ) ) | ( (! ( ( ( (tk(P74)) <= ( 0 ) ) & ( ( ( ( ( (tk(P15)) <= (tk(P48)) ) | ( (tk(P84)) <= (tk(P81)) ) ) | ( (tk(P63)) <= (tk(P22)) ) ) & ( (! ( (tk(P7)) <= ( 1 ) )) | (! ( (tk(P48)) <= (tk(P40)) )) ) ) & ( ( (tk(P67)) <= ( 0 ) ) & (! ( ( (tk(P5)) <= (tk(P11)) ) & ( (tk(P50)) <= ( 1 ) ) )) ) ) ) & ( ( ( ( ( ( (tk(P74)) <= ( 0 ) ) | ( (tk(P53)) <= ( 0 ) ) ) | ( ( ( 1 ) <= (tk(P36)) ) & ( (tk(P21)) <= ( 0 ) ) ) ) & ( ( ( 1 ) <= (tk(P35)) ) & ( ( ( 1 ) <= (tk(P74)) ) & ( (tk(P64)) <= (tk(P24)) ) ) ) ) | ( ( (tk(P29)) <= ( 0 ) ) | ( (tk(P47)) <= ( 0 ) ) ) ) & ( (! ( ( 1 ) <= (tk(P48)) )) & ( ( ( ( 1 ) <= (tk(P40)) ) & ( ( 1 ) <= (tk(P66)) ) ) & ( ( 1 ) <= (tk(P20)) ) ) ) ) )) | (! ( (tk(P67)) <= ( 1 ) )) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-09 (reachable &!potential( ( (! ( (tk(P20)) <= (tk(P54)) )) | ( (tk(P29)) <= ( 1 ) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-10 (reachable &!potential( ( ( (tk(P45)) <= ( 0 ) ) | ( ( ( (! ( ( ( (tk(P32)) <= (tk(P3)) ) | (! ( (tk(P73)) <= (tk(P56)) )) ) & ( (tk(P14)) <= (tk(P79)) ) )) & ( (tk(P68)) <= (tk(P48)) ) ) | ( ( 1 ) <= (tk(P41)) ) ) & ( ( ( ( (! ( ( ( ( 1 ) <= (tk(P21)) ) | ( (tk(P7)) <= (tk(P29)) ) ) | (! ( (tk(P27)) <= ( 1 ) )) )) | ( ( (tk(P20)) <= (tk(P73)) ) | (! ( (tk(P76)) <= (tk(P43)) )) ) ) | ( ( ( (! ( (tk(P27)) <= ( 1 ) )) | ( ( (tk(P84)) <= (tk(P34)) ) | ( ( 1 ) <= (tk(P53)) ) ) ) | ( ( (tk(P20)) <= ( 0 ) ) & ( ( (tk(P34)) <= (tk(P12)) ) | ( (tk(P67)) <= ( 0 ) ) ) ) ) | ( ( ( ( ( 1 ) <= (tk(P8)) ) | ( ( 1 ) <= (tk(P87)) ) ) | ( ( (tk(P24)) <= ( 1 ) ) & ( (tk(P39)) <= (tk(P21)) ) ) ) & (! ( ( ( 1 ) <= (tk(P44)) ) & ( ( 1 ) <= (tk(P44)) ) )) ) ) ) | (! ( (! ( ( (tk(P63)) <= (tk(P61)) ) & ( ( 1 ) <= (tk(P38)) ) )) & (! ( (! ( (tk(P36)) <= ( 0 ) )) & ( ( 1 ) <= (tk(P47)) ) )) )) ) | ( ( ( ( (tk(P58)) <= ( 0 ) ) | ( ( ( ( 1 ) <= (tk(P60)) ) & (! ( (tk(P29)) <= (tk(P2)) )) ) | ( ( ( (tk(P73)) <= ( 1 ) ) | ( (tk(P2)) <= (tk(P72)) ) ) | ( ( ( 1 ) <= (tk(P87)) ) & ( (tk(P2)) <= ( 0 ) ) ) ) ) ) | (! ( (! ( (tk(P10)) <= ( 0 ) )) & ( (tk(P78)) <= (tk(P59)) ) )) ) & ( (! ( (! ( ( ( 1 ) <= (tk(P16)) ) | ( (tk(P63)) <= ( 1 ) ) )) | ( ( ( ( 1 ) <= (tk(P16)) ) | ( (tk(P49)) <= ( 1 ) ) ) | ( ( ( 1 ) <= (tk(P43)) ) | ( (tk(P28)) <= ( 1 ) ) ) ) )) & ( ( ( (tk(P85)) <= (tk(P87)) ) & ( ( 1 ) <= (tk(P21)) ) ) & ( ( ( ( (tk(P4)) <= (tk(P21)) ) | ( (tk(P63)) <= (tk(P44)) ) ) | (! ( (tk(P34)) <= (tk(P59)) )) ) | ( ( (tk(P80)) <= ( 1 ) ) & ( (tk(P3)) <= ( 1 ) ) ) ) ) ) ) ) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-11 (reachable &!potential( ( (tk(P23)) <= ( 1 ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-12 (reachable &!potential( ( ( (! ( ( ( ( ( (tk(P1)) <= (tk(P26)) ) | ( (tk(P4)) <= (tk(P78)) ) ) & ( ( 1 ) <= (tk(P51)) ) ) & ( (tk(P76)) <= (tk(P80)) ) ) & ( ( ( ( 1 ) <= (tk(P5)) ) | ( (! ( ( (tk(P61)) <= (tk(P13)) ) | ( ( 1 ) <= (tk(P53)) ) )) | (! ( ( (tk(P40)) <= (tk(P12)) ) | ( ( 1 ) <= (tk(P69)) ) )) ) ) & ( (! ( ( ( (tk(P42)) <= ( 0 ) ) | ( ( 1 ) <= (tk(P14)) ) ) & ( ( (tk(P61)) <= (tk(P42)) ) | ( (tk(P15)) <= ( 0 ) ) ) )) & ( (tk(P75)) <= (tk(P27)) ) ) ) )) | (! ( ( ( (! ( (! ( ( 1 ) <= (tk(P74)) )) & ( ( (tk(P7)) <= (tk(P82)) ) & ( (tk(P45)) <= (tk(P36)) ) ) )) | ( ( (! ( (tk(P7)) <= (tk(P24)) )) | ( ( (tk(P54)) <= ( 0 ) ) | ( (tk(P22)) <= (tk(P45)) ) ) ) | ( (tk(P2)) <= ( 0 ) ) ) ) | ( (tk(P70)) <= ( 0 ) ) ) & ( ( ( ( 1 ) <= (tk(P64)) ) | (! ( ( ( (tk(P11)) <= ( 0 ) ) | ( ( 1 ) <= (tk(P24)) ) ) | (! ( (tk(P9)) <= ( 1 ) )) )) ) | (! ( ( (tk(P42)) <= ( 0 ) ) & ( (! ( (tk(P46)) <= ( 1 ) )) | ( (tk(P18)) <= (tk(P12)) ) ) )) ) )) ) | (! ( ( ( ( (tk(P56)) <= (tk(P74)) ) & ( ( (tk(P26)) <= ( 0 ) ) | (! ( ( ( (tk(P29)) <= (tk(P47)) ) & ( ( 1 ) <= (tk(P53)) ) ) | ( ( ( 1 ) <= (tk(P86)) ) | ( (tk(P17)) <= (tk(P33)) ) ) )) ) ) & ( ( (tk(P9)) <= (tk(P55)) ) & ( ( (! ( (tk(P76)) <= ( 1 ) )) & ( ( ( (tk(P23)) <= ( 1 ) ) | ( (tk(P36)) <= ( 1 ) ) ) | (! ( (tk(P78)) <= (tk(P7)) )) ) ) | ( ( (tk(P15)) <= (tk(P83)) ) & (! ( (tk(P31)) <= ( 0 ) )) ) ) ) ) | ( (! ( (! ( (! ( ( 1 ) <= (tk(P53)) )) | ( (tk(P49)) <= ( 1 ) ) )) | ( ( (tk(P22)) <= ( 0 ) ) & ( ( 1 ) <= (tk(P75)) ) ) )) | (! ( ( 1 ) <= (tk(P44)) )) ) )) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-13 (reachable &!potential( ( ( ( (tk(P18)) <= (tk(P74)) ) | ( ( ( ( 1 ) <= (tk(P2)) ) | ( ( ( (tk(P43)) <= ( 0 ) ) & (! ( ( (tk(P55)) <= (tk(P43)) ) & ( (tk(P32)) <= ( 0 ) ) )) ) | (! ( ( (! ( (tk(P23)) <= ( 0 ) )) & ( ( (tk(P40)) <= ( 1 ) ) & ( ( 1 ) <= (tk(P19)) ) ) ) | (! ( ( (tk(P46)) <= (tk(P87)) ) | ( ( 1 ) <= (tk(P59)) ) )) )) ) ) | ( (! ( (! ( ( ( 1 ) <= (tk(P33)) ) | ( (tk(P29)) <= ( 1 ) ) )) | ( ( ( ( 1 ) <= (tk(P15)) ) | ( (tk(P57)) <= (tk(P69)) ) ) & ( (tk(P11)) <= (tk(P55)) ) ) )) | (! ( (tk(P40)) <= ( 0 ) )) ) ) ) & ( ( ( ( 1 ) <= (tk(P16)) ) | (! ( (! ( ( (! ( ( 1 ) <= (tk(P28)) )) | (! ( (tk(P68)) <= (tk(P81)) )) ) | ( (! ( (tk(P46)) <= ( 0 ) )) | ( ( ( 1 ) <= (tk(P47)) ) & ( (tk(P62)) <= ( 0 ) ) ) ) )) & (! ( ( ( 1 ) <= (tk(P6)) ) | ( ( ( ( 1 ) <= (tk(P73)) ) & ( ( 1 ) <= (tk(P41)) ) ) & ( ( (tk(P2)) <= (tk(P22)) ) & ( ( 1 ) <= (tk(P69)) ) ) ) )) )) ) | ( ( ( ( ( (tk(P42)) <= ( 0 ) ) & (! ( ( 1 ) <= (tk(P50)) )) ) & ( (! ( (! ( (tk(P67)) <= (tk(P1)) )) & (! ( (tk(P55)) <= (tk(P59)) )) )) | ( (! ( ( (tk(P80)) <= ( 0 ) ) & ( (tk(P42)) <= (tk(P71)) ) )) & (! ( (tk(P56)) <= ( 1 ) )) ) ) ) & ( ( ( ( ( 1 ) <= (tk(P5)) ) & ( ( ( ( 1 ) <= (tk(P12)) ) & ( (tk(P81)) <= ( 0 ) ) ) & ( ( (tk(P87)) <= ( 0 ) ) | ( (tk(P14)) <= ( 1 ) ) ) ) ) & ( ( ( ( 1 ) <= (tk(P82)) ) & ( ( (tk(P69)) <= (tk(P82)) ) | ( ( 1 ) <= (tk(P54)) ) ) ) & ( ( 1 ) <= (tk(P71)) ) ) ) & ( ( ( ( ( ( 1 ) <= (tk(P68)) ) | ( ( 1 ) <= (tk(P63)) ) ) | ( ( (tk(P1)) <= ( 1 ) ) & ( (tk(P22)) <= ( 0 ) ) ) ) | ( ( ( (tk(P74)) <= ( 1 ) ) | ( (tk(P55)) <= ( 1 ) ) ) | ( ( ( 1 ) <= (tk(P58)) ) | ( (tk(P20)) <= (tk(P82)) ) ) ) ) & ( ( ( ( (tk(P13)) <= (tk(P11)) ) & ( (tk(P54)) <= (tk(P59)) ) ) | ( (tk(P77)) <= ( 0 ) ) ) & (! ( (tk(P32)) <= (tk(P60)) )) ) ) ) ) & ( ( ( ( ( 1 ) <= (tk(P45)) ) | (! ( ( ( 1 ) <= (tk(P52)) ) & ( (tk(P70)) <= (tk(P27)) ) )) ) & ( ( ( ( (tk(P27)) <= (tk(P44)) ) & ( ( (tk(P17)) <= (tk(P64)) ) & ( (tk(P33)) <= (tk(P3)) ) ) ) | ( ( ( (tk(P52)) <= ( 0 ) ) | ( (tk(P19)) <= (tk(P79)) ) ) & (! ( (tk(P74)) <= ( 1 ) )) ) ) & ( ( ( 1 ) <= (tk(P72)) ) | ( ( ( (tk(P27)) <= (tk(P30)) ) & ( (tk(P52)) <= ( 1 ) ) ) | (! ( (tk(P48)) <= ( 1 ) )) ) ) ) ) & ( (! ( (! ( ( 1 ) <= (tk(P57)) )) & ( ( ( (tk(P65)) <= ( 1 ) ) & ( (tk(P85)) <= (tk(P56)) ) ) & ( ( (tk(P18)) <= (tk(P63)) ) & ( ( 1 ) <= (tk(P4)) ) ) ) )) & ( ( 1 ) <= (tk(P67)) ) ) ) ) ) )))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-14 (reachable & potential((! ( ( ( ( (tk(P71)) <= ( 0 ) ) | ( (! ( (! ( ( ( 1 ) <= (tk(P82)) ) | ( (tk(P52)) <= (tk(P50)) ) )) & ( ( ( (tk(P43)) <= ( 0 ) ) & ( ( 1 ) <= (tk(P11)) ) ) & ( ( (tk(P38)) <= ( 0 ) ) & ( (tk(P63)) <= (tk(P44)) ) ) ) )) & ( ( (! ( ( (tk(P86)) <= ( 1 ) ) | ( (tk(P19)) <= (tk(P8)) ) )) | ( (tk(P58)) <= ( 0 ) ) ) | ( ( (tk(P87)) <= ( 0 ) ) | ( (tk(P64)) <= ( 1 ) ) ) ) ) ) | ( (tk(P31)) <= ( 0 ) ) ) | ( ( 1 ) <= (tk(P62)) ) ))))
PROPERTY: ARMCacheCoherence-PT-none-ReachabilityCardinality-15 (reachable &!potential( ( ( ( (! ( ( ( ( 1 ) <= (tk(P83)) ) | (! ( ( (tk(P84)) <= (tk(P62)) ) & ( ( 1 ) <= (tk(P37)) ) )) ) & ( ( (tk(P50)) <= ( 0 ) ) & ( ( (tk(P36)) <= (tk(P28)) ) & ( ( ( 1 ) <= (tk(P80)) ) | ( ( 1 ) <= (tk(P38)) ) ) ) ) )) | (! ( ( (! ( ( ( (tk(P18)) <= ( 0 ) ) & ( (tk(P60)) <= ( 1 ) ) ) & ( ( ( 1 ) <= (tk(P9)) ) | ( (tk(P21)) <= ( 0 ) ) ) )) & ( ( (tk(P87)) <= (tk(P85)) ) & (! ( (tk(P34)) <= (tk(P79)) )) ) ) & ( ( (tk(P74)) <= ( 1 ) ) & ( ( ( ( 1 ) <= (tk(P35)) ) & ( ( (tk(P47)) <= ( 0 ) ) & ( ( 1 ) <= (tk(P26)) ) ) ) | ( (tk(P44)) <= (tk(P35)) ) ) ) )) ) & ( ( ( 1 ) <= (tk(P87)) ) | ( ( (! ( ( ( (tk(P78)) <= ( 1 ) ) & ( ( ( 1 ) <= (tk(P14)) ) | ( ( 1 ) <= (tk(P17)) ) ) ) | (! ( (tk(P38)) <= (tk(P86)) )) )) & ( (! ( ( ( ( 1 ) <= (tk(P1)) ) & ( ( 1 ) <= (tk(P22)) ) ) | ( ( (tk(P29)) <= ( 0 ) ) & ( ( 1 ) <= (tk(P1)) ) ) )) & ( ( ( 1 ) <= (tk(P75)) ) | ( (! ( (tk(P79)) <= ( 0 ) )) & ( ( ( 1 ) <= (tk(P26)) ) | ( ( 1 ) <= (tk(P15)) ) ) ) ) ) ) & ( (tk(P3)) <= ( 0 ) ) ) ) ) | ( ( (tk(P51)) <= ( 1 ) ) & (! ( ( ( ( ( ( ( 1 ) <= (tk(P1)) ) & (! ( (tk(P15)) <= ( 1 ) )) ) & (! ( ( (tk(P37)) <= (tk(P24)) ) & ( (tk(P7)) <= ( 1 ) ) )) ) & (! ( ( 1 ) <= (tk(P29)) )) ) & ( (! ( ( ( (tk(P71)) <= (tk(P40)) ) | ( (tk(P73)) <= (tk(P42)) ) ) & ( ( (tk(P69)) <= (tk(P30)) ) & ( (tk(P8)) <= ( 1 ) ) ) )) & ( ( (! ( (tk(P48)) <= (tk(P31)) )) & ( ( (tk(P62)) <= (tk(P34)) ) | ( (tk(P1)) <= ( 0 ) ) ) ) | ( (tk(P46)) <= ( 0 ) ) ) ) ) | ( ( ( (! ( ( (tk(P35)) <= ( 0 ) ) | ( (tk(P12)) <= ( 0 ) ) )) | ( ( ( ( 1 ) <= (tk(P84)) ) & ( ( 1 ) <= (tk(P20)) ) ) & ( ( ( 1 ) <= (tk(P77)) ) | ( (tk(P45)) <= (tk(P29)) ) ) ) ) & ( (! ( (tk(P75)) <= ( 0 ) )) & ( (tk(P35)) <= ( 0 ) ) ) ) & ( ( ( (tk(P75)) <= (tk(P82)) ) & (! ( ( 1 ) <= (tk(P9)) )) ) & ( (! ( ( ( 1 ) <= (tk(P56)) ) | ( (tk(P22)) <= (tk(P66)) ) )) | ( ( ( (tk(P45)) <= ( 1 ) ) | ( (tk(P11)) <= ( 0 ) ) ) & ( ( (tk(P34)) <= ( 1 ) ) | ( (tk(P79)) <= ( 0 ) ) ) ) ) ) ) )) ) )))

BK_STOP 1678721425243

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityCardinality -timeout 360 -rebuildPNML
/home/mcc/BenchKit/bin//../reducer/bin//../../smart/bin//smart.sh: line 116: 601 Killed ${SMART}/smart ${INPUT_SM}

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="smartxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool smartxred"
echo " Input is ARMCacheCoherence-PT-none, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r011-oct2-167813599600006"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;