Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595500434.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AutoFlight-PT-05a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595500434
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 444K
-rw-r--r-- 1 mcc users 7.1K Feb 25 18:13 CTLCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 18:13 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.3K Feb 25 18:11 CTLFireability.txt
-rw-r--r-- 1 mcc users 48K Feb 25 18:11 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.5K Feb 25 15:32 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:32 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 15:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 7.9K Feb 25 18:15 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 80K Feb 25 18:15 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.2K Feb 25 18:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 25 18:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:32 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:32 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 36K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-00
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-01
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-02
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-03
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-04
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-05
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-06
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-07
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-08
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-09
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-10
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-11
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-12
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-13
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-14
FORMULA_NAME AutoFlight-PT-05a-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678348648820

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AutoFlight-PT-05a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:57:31] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 07:57:31] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:57:31] [INFO ] Load time of PNML (sax parser for PT used): 40 ms
[2023-03-09 07:57:31] [INFO ] Transformed 132 places.
[2023-03-09 07:57:31] [INFO ] Transformed 130 transitions.
[2023-03-09 07:57:31] [INFO ] Found NUPN structural information;
[2023-03-09 07:57:31] [INFO ] Parsed PT model containing 132 places and 130 transitions and 420 arcs in 114 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Ensure Unique test removed 25 transitions
Reduce redundant transitions removed 25 transitions.
Support contains 91 out of 132 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 132/132 places, 105/105 transitions.
Applied a total of 0 rules in 17 ms. Remains 132 /132 variables (removed 0) and now considering 105/105 (removed 0) transitions.
// Phase 1: matrix 105 rows 132 cols
[2023-03-09 07:57:31] [INFO ] Computed 34 place invariants in 10 ms
[2023-03-09 07:57:32] [INFO ] Implicit Places using invariants in 896 ms returned []
[2023-03-09 07:57:32] [INFO ] Invariant cache hit.
[2023-03-09 07:57:32] [INFO ] State equation strengthened by 25 read => feed constraints.
[2023-03-09 07:57:32] [INFO ] Implicit Places using invariants and state equation in 396 ms returned [14, 47, 99, 129]
Discarding 4 places :
Implicit Place search using SMT with State Equation took 1321 ms to find 4 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 128/132 places, 105/105 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 127 transition count 104
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 127 transition count 104
Applied a total of 2 rules in 5 ms. Remains 127 /128 variables (removed 1) and now considering 104/105 (removed 1) transitions.
// Phase 1: matrix 104 rows 127 cols
[2023-03-09 07:57:32] [INFO ] Computed 30 place invariants in 3 ms
[2023-03-09 07:57:33] [INFO ] Implicit Places using invariants in 140 ms returned []
[2023-03-09 07:57:33] [INFO ] Invariant cache hit.
[2023-03-09 07:57:33] [INFO ] State equation strengthened by 20 read => feed constraints.
[2023-03-09 07:57:33] [INFO ] Implicit Places using invariants and state equation in 166 ms returned []
Implicit Place search using SMT with State Equation took 309 ms to find 0 implicit places.
Starting structural reductions in LTL mode, iteration 2 : 127/132 places, 104/105 transitions.
Finished structural reductions in LTL mode , in 2 iterations and 1653 ms. Remains : 127/132 places, 104/105 transitions.
Support contains 91 out of 127 places after structural reductions.
[2023-03-09 07:57:33] [INFO ] Flatten gal took : 27 ms
[2023-03-09 07:57:33] [INFO ] Flatten gal took : 36 ms
[2023-03-09 07:57:33] [INFO ] Input system was already deterministic with 104 transitions.
Incomplete random walk after 10000 steps, including 286 resets, run finished after 388 ms. (steps per millisecond=25 ) properties (out of 76) seen :62
Incomplete Best-First random walk after 10001 steps, including 44 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 47 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 44 resets, run finished after 77 ms. (steps per millisecond=129 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 40 resets, run finished after 65 ms. (steps per millisecond=153 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 47 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10000 steps, including 37 resets, run finished after 32 ms. (steps per millisecond=312 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 41 resets, run finished after 56 ms. (steps per millisecond=178 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 47 resets, run finished after 55 ms. (steps per millisecond=181 ) properties (out of 14) seen :3
Incomplete Best-First random walk after 10001 steps, including 45 resets, run finished after 60 ms. (steps per millisecond=166 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 36 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 32 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 45 resets, run finished after 54 ms. (steps per millisecond=185 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 46 resets, run finished after 40 ms. (steps per millisecond=250 ) properties (out of 11) seen :0
Running SMT prover for 11 properties.
[2023-03-09 07:57:34] [INFO ] Invariant cache hit.
[2023-03-09 07:57:34] [INFO ] [Real]Absence check using 30 positive place invariants in 6 ms returned sat
[2023-03-09 07:57:35] [INFO ] After 228ms SMT Verify possible using state equation in real domain returned unsat :1 sat :1 real:9
[2023-03-09 07:57:35] [INFO ] State equation strengthened by 20 read => feed constraints.
[2023-03-09 07:57:35] [INFO ] After 14ms SMT Verify possible using 20 Read/Feed constraints in real domain returned unsat :1 sat :0 real:10
[2023-03-09 07:57:35] [INFO ] After 370ms SMT Verify possible using all constraints in real domain returned unsat :1 sat :0 real:10
[2023-03-09 07:57:35] [INFO ] [Nat]Absence check using 30 positive place invariants in 48 ms returned sat
[2023-03-09 07:57:35] [INFO ] After 199ms SMT Verify possible using state equation in natural domain returned unsat :3 sat :8
[2023-03-09 07:57:35] [INFO ] After 194ms SMT Verify possible using 20 Read/Feed constraints in natural domain returned unsat :3 sat :8
[2023-03-09 07:57:35] [INFO ] After 304ms SMT Verify possible using trap constraints in natural domain returned unsat :3 sat :8
Attempting to minimize the solution found.
Minimization took 114 ms.
[2023-03-09 07:57:36] [INFO ] After 921ms SMT Verify possible using all constraints in natural domain returned unsat :3 sat :8
Fused 11 Parikh solutions to 7 different solutions.
Parikh walk visited 4 properties in 11 ms.
Support contains 5 out of 127 places. Attempting structural reductions.
Starting structural reductions in REACHABILITY mode, iteration 0 : 127/127 places, 104/104 transitions.
Drop transitions removed 13 transitions
Trivial Post-agglo rules discarded 13 transitions
Performed 13 trivial Post agglomeration. Transition count delta: 13
Iterating post reduction 0 with 13 rules applied. Total rules applied 13 place count 127 transition count 91
Reduce places removed 13 places and 0 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 26 place count 114 transition count 91
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 12 Pre rules applied. Total rules applied 26 place count 114 transition count 79
Deduced a syphon composed of 12 places in 1 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 2 with 24 rules applied. Total rules applied 50 place count 102 transition count 79
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 2 with 18 rules applied. Total rules applied 68 place count 93 transition count 70
Free-agglomeration rule applied 9 times.
Iterating global reduction 2 with 9 rules applied. Total rules applied 77 place count 93 transition count 61
Reduce places removed 9 places and 0 transitions.
Iterating post reduction 2 with 9 rules applied. Total rules applied 86 place count 84 transition count 61
Applied a total of 86 rules in 32 ms. Remains 84 /127 variables (removed 43) and now considering 61/104 (removed 43) transitions.
Finished structural reductions in REACHABILITY mode , in 1 iterations and 32 ms. Remains : 84/127 places, 61/104 transitions.
Finished random walk after 912 steps, including 15 resets, run visited all 4 properties in 6 ms. (steps per millisecond=152 )
Successfully simplified 3 atomic propositions for a total of 16 simplifications.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 7 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 11 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Computed a total of 9 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 4 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 4 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 3 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 2 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 13 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 2 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 2 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 1 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Drop transitions removed 10 transitions
Trivial Post-agglo rules discarded 10 transitions
Performed 10 trivial Post agglomeration. Transition count delta: 10
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 127 transition count 94
Reduce places removed 10 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 11 rules applied. Total rules applied 21 place count 117 transition count 93
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 22 place count 116 transition count 93
Performed 11 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 11 Pre rules applied. Total rules applied 22 place count 116 transition count 82
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 3 with 22 rules applied. Total rules applied 44 place count 105 transition count 82
Performed 9 Post agglomeration using F-continuation condition.Transition count delta: 9
Deduced a syphon composed of 9 places in 0 ms
Reduce places removed 9 places and 0 transitions.
Iterating global reduction 3 with 18 rules applied. Total rules applied 62 place count 96 transition count 73
Applied a total of 62 rules in 18 ms. Remains 96 /127 variables (removed 31) and now considering 73/104 (removed 31) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 96/127 places, 73/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 73 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 1 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 1 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 16 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 18 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 2 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 2 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in LTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Applied a total of 0 rules in 1 ms. Remains 127 /127 variables (removed 0) and now considering 104/104 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 127/127 places, 104/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 104 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Reduce places removed 1 places and 1 transitions.
Reduce places removed 8 places and 0 transitions.
Drop transitions removed 30 transitions
Trivial Post-agglo rules discarded 30 transitions
Performed 30 trivial Post agglomeration. Transition count delta: 30
Iterating post reduction 0 with 38 rules applied. Total rules applied 38 place count 118 transition count 73
Reduce places removed 30 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 31 rules applied. Total rules applied 69 place count 88 transition count 72
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 70 place count 87 transition count 72
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 12 Pre rules applied. Total rules applied 70 place count 87 transition count 60
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 17 places and 0 transitions.
Iterating global reduction 3 with 29 rules applied. Total rules applied 99 place count 70 transition count 60
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 5 Pre rules applied. Total rules applied 99 place count 70 transition count 55
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 109 place count 65 transition count 55
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 3 with 20 rules applied. Total rules applied 129 place count 55 transition count 45
Applied a total of 129 rules in 6 ms. Remains 55 /127 variables (removed 72) and now considering 45/104 (removed 59) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 55/127 places, 45/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 45 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 127/127 places, 104/104 transitions.
Drop transitions removed 13 transitions
Trivial Post-agglo rules discarded 13 transitions
Performed 13 trivial Post agglomeration. Transition count delta: 13
Iterating post reduction 0 with 13 rules applied. Total rules applied 13 place count 127 transition count 91
Reduce places removed 13 places and 0 transitions.
Iterating post reduction 1 with 13 rules applied. Total rules applied 26 place count 114 transition count 91
Performed 12 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 12 Pre rules applied. Total rules applied 26 place count 114 transition count 79
Deduced a syphon composed of 12 places in 0 ms
Reduce places removed 12 places and 0 transitions.
Iterating global reduction 2 with 24 rules applied. Total rules applied 50 place count 102 transition count 79
Performed 10 Post agglomeration using F-continuation condition.Transition count delta: 10
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 2 with 20 rules applied. Total rules applied 70 place count 92 transition count 69
Applied a total of 70 rules in 7 ms. Remains 92 /127 variables (removed 35) and now considering 69/104 (removed 35) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 92/127 places, 69/104 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:57:36] [INFO ] Input system was already deterministic with 69 transitions.
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:57:36] [INFO ] Export to MCC of 16 properties in file /home/mcc/execution/CTLFireability.sr.xml took 3 ms.
[2023-03-09 07:57:36] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 127 places, 104 transitions and 349 arcs took 0 ms.
Total runtime 5218 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AutoFlight-PT-05a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/381
CTLFireability

FORMULA AutoFlight-PT-05a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AutoFlight-PT-05a-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678348797349

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/381/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/381/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/381/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 7 (type EXCL) for 6 AutoFlight-PT-05a-CTLFireability-02
lola: time limit : 109 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 73 (type FNDP) for 32 AutoFlight-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type EQUN) for 32 AutoFlight-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type SRCH) for 32 AutoFlight-PT-05a-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 7 (type EXCL) for AutoFlight-PT-05a-CTLFireability-02
lola: result : false
lola: markings : 12001
lola: fired transitions : 23685
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 30 (type EXCL) for 25 AutoFlight-PT-05a-CTLFireability-07
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for AutoFlight-PT-05a-CTLFireability-07
lola: result : true
lola: markings : 493
lola: fired transitions : 537
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 AutoFlight-PT-05a-CTLFireability-06
lola: time limit : 119 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 76 (type SRCH) for AutoFlight-PT-05a-CTLFireability-08
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 23 (type EXCL) for AutoFlight-PT-05a-CTLFireability-06
lola: result : true
lola: markings : 32
lola: fired transitions : 95
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 49 (type EXCL) for 48 AutoFlight-PT-05a-CTLFireability-12
lola: time limit : 128 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
sara: try reading problem file /home/mcc/execution/381/CTLFireability-74.sara.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 73 (type FNDP) for AutoFlight-PT-05a-CTLFireability-08
lola: result : true
lola: fired transitions : 7
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 74 (type EQUN) for AutoFlight-PT-05a-CTLFireability-08 (obsolete)
lola: FINISHED task # 74 (type EQUN) for AutoFlight-PT-05a-CTLFireability-08
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 79 (type FNDP) for 62 AutoFlight-PT-05a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 80 (type EQUN) for 62 AutoFlight-PT-05a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 82 (type SRCH) for 62 AutoFlight-PT-05a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 82 (type SRCH) for AutoFlight-PT-05a-CTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 79 (type FNDP) for AutoFlight-PT-05a-CTLFireability-14
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 80 (type EQUN) for AutoFlight-PT-05a-CTLFireability-14 (obsolete)
lola: LAUNCH task # 83 (type FNDP) for 62 AutoFlight-PT-05a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type EQUN) for 62 AutoFlight-PT-05a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type SRCH) for 62 AutoFlight-PT-05a-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 86 (type SRCH) for AutoFlight-PT-05a-CTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 83 (type FNDP) for AutoFlight-PT-05a-CTLFireability-14
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 84 (type EQUN) for AutoFlight-PT-05a-CTLFireability-14 (obsolete)
lola: FINISHED task # 84 (type EQUN) for AutoFlight-PT-05a-CTLFireability-14
lola: result : unknown
sara: try reading problem file /home/mcc/execution/381/CTLFireability-80.sara.

lola: FINISHED task # 80 (type EQUN) for AutoFlight-PT-05a-CTLFireability-14
lola: result : true
lola: FINISHED task # 49 (type EXCL) for AutoFlight-PT-05a-CTLFireability-12
lola: result : false
lola: markings : 87624
lola: fired transitions : 437220
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 77 (type EXCL) for 15 AutoFlight-PT-05a-CTLFireability-05
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 77 (type EXCL) for AutoFlight-PT-05a-CTLFireability-05
lola: result : true
lola: markings : 20
lola: fired transitions : 19
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type EXCL) for 51 AutoFlight-PT-05a-CTLFireability-13
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for AutoFlight-PT-05a-CTLFireability-13
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 51 AutoFlight-PT-05a-CTLFireability-13
lola: time limit : 359 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AutoFlight-PT-05a-CTLFireability-02: CTL false CTL model checker
AutoFlight-PT-05a-CTLFireability-05: CONJ false state space /EXEF
AutoFlight-PT-05a-CTLFireability-06: CTL true CTL model checker
AutoFlight-PT-05a-CTLFireability-07: DISJ true CTL model checker
AutoFlight-PT-05a-CTLFireability-12: CTL false CTL model checker
AutoFlight-PT-05a-CTLFireability-14: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AutoFlight-PT-05a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-08: DISJ 0 1 0 0 5 0 0 1
AutoFlight-PT-05a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-13: DISJ 0 0 1 0 4 0 0 1
AutoFlight-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 5/359 3/32 AutoFlight-PT-05a-CTLFireability-13 501352 m, 100270 m/sec, 4381419 t fired, .

Time elapsed: 6 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AutoFlight-PT-05a-CTLFireability-02: CTL false CTL model checker
AutoFlight-PT-05a-CTLFireability-05: CONJ false state space /EXEF
AutoFlight-PT-05a-CTLFireability-06: CTL true CTL model checker
AutoFlight-PT-05a-CTLFireability-07: DISJ true CTL model checker
AutoFlight-PT-05a-CTLFireability-12: CTL false CTL model checker
AutoFlight-PT-05a-CTLFireability-14: CONJ true CONJ

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AutoFlight-PT-05a-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-08: DISJ 0 1 0 0 5 0 0 1
AutoFlight-PT-05a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-05a-CTLFireability-13: DISJ 0 0 1 0 4 0 0 1
AutoFlight-PT-05a-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 10/359 5/32 AutoFlight-PT-05a-CTLFireability-13 1027091 m, 105147 m/sec, 9325944 t fired, .

Time elapsed: 11 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AutoFlight-PT-05a-CTLFireability-02: CTL false CTL model checker
AutoFlight-PT-05a-CTLFireability-05: CONJ false state space /EXEF
AutoFlight-PT-05a-CTLFireability-06: CTL true CTL model checker
AutoFlight-PT-05a-CTLFireability-07: DISJ true CTL model checker
AutoFlight-PT-05a-CTLFireability-12: CTL false CTL model checker
AutoFlight-PT-05a-CTLFireability-14: CONJ true CONJ

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4 CTL EXCL 5/879 4/32 AutoFlight-PT-05a-CTLFireability-01 757173 m, 151434 m/sec, 4248507 t fired, .

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4 CTL EXCL 20/879 13/32 AutoFlight-PT-05a-CTLFireability-01 2685545 m, 125006 m/sec, 16699444 t fired, .

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4 CTL EXCL 25/879 16/32 AutoFlight-PT-05a-CTLFireability-01 3307954 m, 124481 m/sec, 20969828 t fired, .

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4 CTL EXCL 30/879 18/32 AutoFlight-PT-05a-CTLFireability-01 3907275 m, 119864 m/sec, 25168342 t fired, .

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4 CTL EXCL 35/879 21/32 AutoFlight-PT-05a-CTLFireability-01 4399438 m, 98432 m/sec, 28669804 t fired, .

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4 CTL EXCL 40/879 23/32 AutoFlight-PT-05a-CTLFireability-01 4904849 m, 101082 m/sec, 32283770 t fired, .

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4 CTL EXCL 45/879 25/32 AutoFlight-PT-05a-CTLFireability-01 5447547 m, 108539 m/sec, 36246906 t fired, .

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4 CTL EXCL 50/879 28/32 AutoFlight-PT-05a-CTLFireability-01 6014252 m, 113341 m/sec, 40428068 t fired, .

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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AutoFlight-PT-05a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AutoFlight-PT-05a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595500434"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AutoFlight-PT-05a.tgz
mv AutoFlight-PT-05a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;