About the Execution of LoLa+red for AutoFlight-PT-04a
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 561.668 | 32834.00 | 41516.00 | 43.80 | FTFTFTFTFFTTTFTT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595500418.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AutoFlight-PT-04a, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595500418
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 528K
-rw-r--r-- 1 mcc users 6.2K Feb 25 17:56 CTLCardinality.txt
-rw-r--r-- 1 mcc users 68K Feb 25 17:56 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.2K Feb 25 17:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K Feb 25 17:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.4K Feb 25 15:32 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Feb 25 15:32 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Feb 25 15:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 13K Feb 25 17:58 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 146K Feb 25 17:58 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.4K Feb 25 17:57 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 86K Feb 25 17:57 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Feb 25 15:32 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:32 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 29K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-00
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-01
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-02
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-03
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-04
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-05
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-06
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-07
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-08
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-09
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-10
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-11
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-12
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-13
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-14
FORMULA_NAME AutoFlight-PT-04a-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678348370089
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AutoFlight-PT-04a
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:52:52] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 07:52:52] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:52:52] [INFO ] Load time of PNML (sax parser for PT used): 42 ms
[2023-03-09 07:52:52] [INFO ] Transformed 107 places.
[2023-03-09 07:52:52] [INFO ] Transformed 105 transitions.
[2023-03-09 07:52:52] [INFO ] Found NUPN structural information;
[2023-03-09 07:52:52] [INFO ] Parsed PT model containing 107 places and 105 transitions and 340 arcs in 113 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 19 ms.
Ensure Unique test removed 20 transitions
Reduce redundant transitions removed 20 transitions.
Support contains 91 out of 107 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 107/107 places, 85/85 transitions.
Applied a total of 0 rules in 14 ms. Remains 107 /107 variables (removed 0) and now considering 85/85 (removed 0) transitions.
// Phase 1: matrix 85 rows 107 cols
[2023-03-09 07:52:52] [INFO ] Computed 28 place invariants in 11 ms
[2023-03-09 07:52:53] [INFO ] Implicit Places using invariants in 546 ms returned [80, 98]
Discarding 2 places :
Implicit Place search using SMT only with invariants took 578 ms to find 2 implicit places.
Starting structural reductions in LTL mode, iteration 1 : 105/107 places, 85/85 transitions.
Applied a total of 0 rules in 1 ms. Remains 105 /105 variables (removed 0) and now considering 85/85 (removed 0) transitions.
Finished structural reductions in LTL mode , in 2 iterations and 594 ms. Remains : 105/107 places, 85/85 transitions.
Support contains 91 out of 105 places after structural reductions.
[2023-03-09 07:52:53] [INFO ] Flatten gal took : 29 ms
[2023-03-09 07:52:53] [INFO ] Flatten gal took : 14 ms
[2023-03-09 07:52:53] [INFO ] Input system was already deterministic with 85 transitions.
Support contains 89 out of 105 places (down from 91) after GAL structural reductions.
Incomplete random walk after 10000 steps, including 326 resets, run finished after 247 ms. (steps per millisecond=40 ) properties (out of 75) seen :61
Incomplete Best-First random walk after 10001 steps, including 57 resets, run finished after 49 ms. (steps per millisecond=204 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 61 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 62 resets, run finished after 29 ms. (steps per millisecond=344 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 63 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 59 resets, run finished after 113 ms. (steps per millisecond=88 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 45 resets, run finished after 34 ms. (steps per millisecond=294 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 63 resets, run finished after 45 ms. (steps per millisecond=222 ) properties (out of 14) seen :0
Incomplete Best-First random walk after 10001 steps, including 56 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 14) seen :1
Incomplete Best-First random walk after 10001 steps, including 60 resets, run finished after 50 ms. (steps per millisecond=200 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 63 resets, run finished after 24 ms. (steps per millisecond=416 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10000 steps, including 63 resets, run finished after 28 ms. (steps per millisecond=357 ) properties (out of 13) seen :0
Incomplete Best-First random walk after 10001 steps, including 53 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 13) seen :1
Incomplete Best-First random walk after 10001 steps, including 48 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 12) seen :0
Incomplete Best-First random walk after 10001 steps, including 65 resets, run finished after 52 ms. (steps per millisecond=192 ) properties (out of 12) seen :3
Running SMT prover for 9 properties.
// Phase 1: matrix 85 rows 105 cols
[2023-03-09 07:52:54] [INFO ] Computed 26 place invariants in 8 ms
[2023-03-09 07:52:54] [INFO ] [Real]Absence check using 26 positive place invariants in 6 ms returned sat
[2023-03-09 07:52:54] [INFO ] After 39ms SMT Verify possible using state equation in real domain returned unsat :7 sat :1 real:1
[2023-03-09 07:52:54] [INFO ] State equation strengthened by 20 read => feed constraints.
[2023-03-09 07:52:54] [INFO ] After 6ms SMT Verify possible using 20 Read/Feed constraints in real domain returned unsat :7 sat :0 real:2
[2023-03-09 07:52:54] [INFO ] After 156ms SMT Verify possible using all constraints in real domain returned unsat :7 sat :0 real:2
[2023-03-09 07:52:54] [INFO ] [Nat]Absence check using 26 positive place invariants in 4 ms returned sat
[2023-03-09 07:52:54] [INFO ] After 33ms SMT Verify possible using state equation in natural domain returned unsat :7 sat :2
[2023-03-09 07:52:54] [INFO ] After 12ms SMT Verify possible using 20 Read/Feed constraints in natural domain returned unsat :7 sat :2
[2023-03-09 07:52:54] [INFO ] After 40ms SMT Verify possible using trap constraints in natural domain returned unsat :7 sat :2
Attempting to minimize the solution found.
Minimization took 17 ms.
[2023-03-09 07:52:54] [INFO ] After 147ms SMT Verify possible using all constraints in natural domain returned unsat :7 sat :2
Fused 9 Parikh solutions to 2 different solutions.
Finished Parikh walk after 36 steps, including 1 resets, run visited all 1 properties in 2 ms. (steps per millisecond=18 )
Parikh walk visited 2 properties in 2 ms.
Successfully simplified 7 atomic propositions for a total of 16 simplifications.
FORMULA AutoFlight-PT-04a-CTLFireability-15 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 9 ms
[2023-03-09 07:52:54] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA AutoFlight-PT-04a-CTLFireability-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:52:54] [INFO ] Input system was already deterministic with 85 transitions.
Support contains 67 out of 105 places (down from 74) after GAL structural reductions.
Computed a total of 9 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 6 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:52:54] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 4 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:54] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 4 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:52:54] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Drop transitions removed 10 transitions
Trivial Post-agglo rules discarded 10 transitions
Performed 10 trivial Post agglomeration. Transition count delta: 10
Iterating post reduction 0 with 10 rules applied. Total rules applied 10 place count 105 transition count 75
Reduce places removed 10 places and 0 transitions.
Iterating post reduction 1 with 10 rules applied. Total rules applied 20 place count 95 transition count 75
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 6 Pre rules applied. Total rules applied 20 place count 95 transition count 69
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 2 with 12 rules applied. Total rules applied 32 place count 89 transition count 69
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 33 place count 88 transition count 68
Iterating global reduction 2 with 1 rules applied. Total rules applied 34 place count 88 transition count 68
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 50 place count 80 transition count 60
Applied a total of 50 rules in 15 ms. Remains 80 /105 variables (removed 25) and now considering 60/85 (removed 25) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 16 ms. Remains : 80/105 places, 60/85 transitions.
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:54] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:54] [INFO ] Input system was already deterministic with 60 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 3 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 105 transition count 77
Reduce places removed 8 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 9 rules applied. Total rules applied 17 place count 97 transition count 76
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 18 place count 96 transition count 76
Performed 4 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 4 Pre rules applied. Total rules applied 18 place count 96 transition count 72
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 26 place count 92 transition count 72
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 27 place count 91 transition count 71
Iterating global reduction 3 with 1 rules applied. Total rules applied 28 place count 91 transition count 71
Performed 5 Post agglomeration using F-continuation condition.Transition count delta: 5
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 3 with 10 rules applied. Total rules applied 38 place count 86 transition count 66
Applied a total of 38 rules in 10 ms. Remains 86 /105 variables (removed 19) and now considering 66/85 (removed 19) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 86/105 places, 66/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 105 transition count 78
Reduce places removed 7 places and 0 transitions.
Performed 1 Post agglomeration using F-continuation condition.Transition count delta: 1
Iterating post reduction 1 with 8 rules applied. Total rules applied 15 place count 98 transition count 77
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 2 with 1 rules applied. Total rules applied 16 place count 97 transition count 77
Performed 6 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 3 with 6 Pre rules applied. Total rules applied 16 place count 97 transition count 71
Deduced a syphon composed of 6 places in 0 ms
Reduce places removed 6 places and 0 transitions.
Iterating global reduction 3 with 12 rules applied. Total rules applied 28 place count 91 transition count 71
Discarding 1 places :
Symmetric choice reduction at 3 with 1 rule applications. Total rules 29 place count 90 transition count 70
Iterating global reduction 3 with 1 rules applied. Total rules applied 30 place count 90 transition count 70
Performed 4 Post agglomeration using F-continuation condition.Transition count delta: 4
Deduced a syphon composed of 4 places in 0 ms
Reduce places removed 4 places and 0 transitions.
Iterating global reduction 3 with 8 rules applied. Total rules applied 38 place count 86 transition count 66
Applied a total of 38 rules in 8 ms. Remains 86 /105 variables (removed 19) and now considering 66/85 (removed 19) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 86/105 places, 66/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Drop transitions removed 7 transitions
Trivial Post-agglo rules discarded 7 transitions
Performed 7 trivial Post agglomeration. Transition count delta: 7
Iterating post reduction 0 with 7 rules applied. Total rules applied 7 place count 105 transition count 78
Reduce places removed 7 places and 0 transitions.
Iterating post reduction 1 with 7 rules applied. Total rules applied 14 place count 98 transition count 78
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 5 Pre rules applied. Total rules applied 14 place count 98 transition count 73
Deduced a syphon composed of 5 places in 0 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 2 with 10 rules applied. Total rules applied 24 place count 93 transition count 73
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 25 place count 92 transition count 72
Iterating global reduction 2 with 1 rules applied. Total rules applied 26 place count 92 transition count 72
Performed 8 Post agglomeration using F-continuation condition.Transition count delta: 8
Deduced a syphon composed of 8 places in 0 ms
Reduce places removed 8 places and 0 transitions.
Iterating global reduction 2 with 16 rules applied. Total rules applied 42 place count 84 transition count 64
Applied a total of 42 rules in 9 ms. Remains 84 /105 variables (removed 21) and now considering 64/85 (removed 21) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 9 ms. Remains : 84/105 places, 64/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 9 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Drop transitions removed 8 transitions
Trivial Post-agglo rules discarded 8 transitions
Performed 8 trivial Post agglomeration. Transition count delta: 8
Iterating post reduction 0 with 8 rules applied. Total rules applied 8 place count 105 transition count 77
Reduce places removed 8 places and 0 transitions.
Iterating post reduction 1 with 8 rules applied. Total rules applied 16 place count 97 transition count 77
Performed 5 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 2 with 5 Pre rules applied. Total rules applied 16 place count 97 transition count 72
Deduced a syphon composed of 5 places in 1 ms
Reduce places removed 5 places and 0 transitions.
Iterating global reduction 2 with 10 rules applied. Total rules applied 26 place count 92 transition count 72
Discarding 1 places :
Symmetric choice reduction at 2 with 1 rule applications. Total rules 27 place count 91 transition count 71
Iterating global reduction 2 with 1 rules applied. Total rules applied 28 place count 91 transition count 71
Performed 7 Post agglomeration using F-continuation condition.Transition count delta: 7
Deduced a syphon composed of 7 places in 0 ms
Reduce places removed 7 places and 0 transitions.
Iterating global reduction 2 with 14 rules applied. Total rules applied 42 place count 84 transition count 64
Applied a total of 42 rules in 7 ms. Remains 84 /105 variables (removed 21) and now considering 64/85 (removed 21) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 7 ms. Remains : 84/105 places, 64/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 2 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 2 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 2 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 2 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 11 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 84 transitions.
Starting structural reductions in LTL mode, iteration 0 : 105/105 places, 85/85 transitions.
Discarding 1 places :
Symmetric choice reduction at 0 with 1 rule applications. Total rules 1 place count 104 transition count 84
Iterating global reduction 0 with 1 rules applied. Total rules applied 2 place count 104 transition count 84
Applied a total of 2 rules in 3 ms. Remains 104 /105 variables (removed 1) and now considering 84/85 (removed 1) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 104/105 places, 84/85 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:55] [INFO ] Input system was already deterministic with 84 transitions.
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:55] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:52:55] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-09 07:52:55] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 105 places, 85 transitions and 294 arcs took 1 ms.
Total runtime 2785 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AutoFlight-PT-04a
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/375
CTLFireability
FORMULA AutoFlight-PT-04a-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AutoFlight-PT-04a-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678348402923
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/375/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/375/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/375/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 27 (type EXCL) for 26 AutoFlight-PT-04a-CTLFireability-07
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for AutoFlight-PT-04a-CTLFireability-07
lola: result : true
lola: markings : 10
lola: fired transitions : 41
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 19 (type EXCL) for 16 AutoFlight-PT-04a-CTLFireability-05
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: FINISHED task # 19 (type EXCL) for AutoFlight-PT-04a-CTLFireability-05
lola: result : true
lola: markings : 15
lola: fired transitions : 30
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 AutoFlight-PT-04a-CTLFireability-01
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 1 (type EXCL) for AutoFlight-PT-04a-CTLFireability-01
lola: result : true
lola: markings : 880
lola: fired transitions : 1830
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 42 (type EXCL) for 41 AutoFlight-PT-04a-CTLFireability-12
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 50 (type FNDP) for 9 AutoFlight-PT-04a-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 51 (type EQUN) for 9 AutoFlight-PT-04a-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 53 (type SRCH) for 9 AutoFlight-PT-04a-CTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 53 (type SRCH) for AutoFlight-PT-04a-CTLFireability-04
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 50 (type FNDP) for AutoFlight-PT-04a-CTLFireability-04
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 51 (type EQUN) for AutoFlight-PT-04a-CTLFireability-04 (obsolete)
lola: FINISHED task # 51 (type EQUN) for AutoFlight-PT-04a-CTLFireability-04
lola: result : unknown
lola: FINISHED task # 42 (type EXCL) for AutoFlight-PT-04a-CTLFireability-12
lola: result : true
lola: markings : 9408
lola: fired transitions : 29040
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 AutoFlight-PT-04a-CTLFireability-14
lola: time limit : 360 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AutoFlight-PT-04a-CTLFireability-01: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-05: DISJ true CTL model checker
AutoFlight-PT-04a-CTLFireability-07: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-12: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AutoFlight-PT-04a-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-04a-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-04a-CTLFireability-04: CONJ 0 1 0 0 5 0 0 1
AutoFlight-PT-04a-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-04a-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-04a-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
AutoFlight-PT-04a-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
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AutoFlight-PT-04a-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 5/360 5/32 AutoFlight-PT-04a-CTLFireability-14 932872 m, 186574 m/sec, 5053174 t fired, .
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# running tasks: 1 of 4 Visible: 14
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AutoFlight-PT-04a-CTLFireability-01: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-05: DISJ true CTL model checker
AutoFlight-PT-04a-CTLFireability-07: CTL true CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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AutoFlight-PT-04a-CTLFireability-04: CONJ 0 1 0 0 5 0 0 1
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 10/360 9/32 AutoFlight-PT-04a-CTLFireability-14 1692470 m, 151919 m/sec, 10262094 t fired, .
Time elapsed: 10 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AutoFlight-PT-04a-CTLFireability-01: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-05: DISJ true CTL model checker
AutoFlight-PT-04a-CTLFireability-07: CTL true CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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AutoFlight-PT-04a-CTLFireability-04: CONJ 0 1 0 0 5 0 0 1
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 15/360 12/32 AutoFlight-PT-04a-CTLFireability-14 2366565 m, 134819 m/sec, 15435360 t fired, .
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AutoFlight-PT-04a-CTLFireability-01: CTL true CTL model checker
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AutoFlight-PT-04a-CTLFireability-07: CTL true CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 20/360 15/32 AutoFlight-PT-04a-CTLFireability-14 2965443 m, 119775 m/sec, 20554301 t fired, .
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AutoFlight-PT-04a-CTLFireability-01: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-05: DISJ true CTL model checker
AutoFlight-PT-04a-CTLFireability-07: CTL true CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 CTL EXCL 25/360 17/32 AutoFlight-PT-04a-CTLFireability-14 3332017 m, 73314 m/sec, 25345491 t fired, .
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# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 48 (type EXCL) for AutoFlight-PT-04a-CTLFireability-14
lola: result : true
lola: markings : 3332017
lola: fired transitions : 26684641
lola: time used : 27.000000
lola: memory pages used : 17
lola: LAUNCH task # 45 (type EXCL) for 44 AutoFlight-PT-04a-CTLFireability-13
lola: time limit : 397 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for AutoFlight-PT-04a-CTLFireability-13
lola: result : false
lola: markings : 34
lola: fired transitions : 34
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 AutoFlight-PT-04a-CTLFireability-11
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for AutoFlight-PT-04a-CTLFireability-11
lola: result : true
lola: markings : 34
lola: fired transitions : 107
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 AutoFlight-PT-04a-CTLFireability-10
lola: time limit : 510 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for AutoFlight-PT-04a-CTLFireability-10
lola: result : true
lola: markings : 16
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 AutoFlight-PT-04a-CTLFireability-03
lola: time limit : 595 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for AutoFlight-PT-04a-CTLFireability-03
lola: result : true
lola: markings : 463
lola: fired transitions : 1037
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 AutoFlight-PT-04a-CTLFireability-02
lola: time limit : 714 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for AutoFlight-PT-04a-CTLFireability-02
lola: result : false
lola: markings : 2
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 12 (type EXCL) for 9 AutoFlight-PT-04a-CTLFireability-04
lola: time limit : 893 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for AutoFlight-PT-04a-CTLFireability-04
lola: result : false
lola: markings : 9
lola: fired transitions : 18
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 AutoFlight-PT-04a-CTLFireability-09
lola: time limit : 1191 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for AutoFlight-PT-04a-CTLFireability-09
lola: result : false
lola: markings : 135
lola: fired transitions : 266
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 AutoFlight-PT-04a-CTLFireability-08
lola: time limit : 1786 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for AutoFlight-PT-04a-CTLFireability-08
lola: result : false
lola: markings : 25601
lola: fired transitions : 253394
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 AutoFlight-PT-04a-CTLFireability-06
lola: time limit : 3573 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for AutoFlight-PT-04a-CTLFireability-06
lola: result : false
lola: markings : 57939
lola: fired transitions : 766710
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AutoFlight-PT-04a-CTLFireability-01: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-02: CTL false CTL model checker
AutoFlight-PT-04a-CTLFireability-03: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-04: CONJ false CTL model checker
AutoFlight-PT-04a-CTLFireability-05: DISJ true CTL model checker
AutoFlight-PT-04a-CTLFireability-06: CTL false CTL model checker
AutoFlight-PT-04a-CTLFireability-07: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-08: CTL false CTL model checker
AutoFlight-PT-04a-CTLFireability-09: CTL false CTL model checker
AutoFlight-PT-04a-CTLFireability-10: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-11: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-12: CTL true CTL model checker
AutoFlight-PT-04a-CTLFireability-13: CTL false CTL model checker
AutoFlight-PT-04a-CTLFireability-14: CTL true CTL model checker
Time elapsed: 27 secs. Pages in use: 17
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AutoFlight-PT-04a"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AutoFlight-PT-04a, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595500418"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AutoFlight-PT-04a.tgz
mv AutoFlight-PT-04a execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;