About the Execution of LoLa+red for Angiogenesis-PT-20
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 6039.720 | 139701.00 | 133791.00 | 15.10 | TT?TFT???TT?T?FT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595400346.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Angiogenesis-PT-20, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595400346
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 512K
-rw-r--r-- 1 mcc users 8.3K Feb 26 14:55 CTLCardinality.txt
-rw-r--r-- 1 mcc users 82K Feb 26 14:55 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.5K Feb 26 14:55 CTLFireability.txt
-rw-r--r-- 1 mcc users 51K Feb 26 14:55 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:31 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:31 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Feb 25 15:31 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Feb 25 15:31 LTLFireability.xml
-rw-r--r-- 1 mcc users 16K Feb 26 14:57 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 146K Feb 26 14:57 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 7.4K Feb 26 14:56 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 64K Feb 26 14:56 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 33K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-00
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-01
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-02
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-03
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-04
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-05
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-06
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-07
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-08
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-09
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-10
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-11
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-12
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-13
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-14
FORMULA_NAME Angiogenesis-PT-20-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1678347573068
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Angiogenesis-PT-20
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:39:35] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 07:39:35] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:39:35] [INFO ] Load time of PNML (sax parser for PT used): 32 ms
[2023-03-09 07:39:35] [INFO ] Transformed 39 places.
[2023-03-09 07:39:35] [INFO ] Transformed 64 transitions.
[2023-03-09 07:39:35] [INFO ] Parsed PT model containing 39 places and 64 transitions and 185 arcs in 96 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 10 ms.
Support contains 36 out of 39 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 64/64 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 38 transition count 64
Applied a total of 1 rules in 11 ms. Remains 38 /39 variables (removed 1) and now considering 64/64 (removed 0) transitions.
// Phase 1: matrix 64 rows 38 cols
[2023-03-09 07:39:35] [INFO ] Computed 7 place invariants in 5 ms
[2023-03-09 07:39:35] [INFO ] Implicit Places using invariants in 228 ms returned []
[2023-03-09 07:39:35] [INFO ] Invariant cache hit.
[2023-03-09 07:39:35] [INFO ] Implicit Places using invariants and state equation in 121 ms returned []
Implicit Place search using SMT with State Equation took 375 ms to find 0 implicit places.
[2023-03-09 07:39:35] [INFO ] Invariant cache hit.
[2023-03-09 07:39:35] [INFO ] Dead Transitions using invariants and state equation in 108 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 38/39 places, 64/64 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 496 ms. Remains : 38/39 places, 64/64 transitions.
Support contains 36 out of 38 places after structural reductions.
[2023-03-09 07:39:35] [INFO ] Flatten gal took : 25 ms
[2023-03-09 07:39:35] [INFO ] Flatten gal took : 11 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Incomplete random walk after 10011 steps, including 2 resets, run finished after 145 ms. (steps per millisecond=69 ) properties (out of 51) seen :41
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 53 ms. (steps per millisecond=188 ) properties (out of 10) seen :3
Incomplete Best-First random walk after 10000 steps, including 2 resets, run finished after 35 ms. (steps per millisecond=285 ) properties (out of 7) seen :2
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=476 ) properties (out of 5) seen :1
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 15 ms. (steps per millisecond=666 ) properties (out of 4) seen :0
Running SMT prover for 4 properties.
[2023-03-09 07:39:36] [INFO ] Invariant cache hit.
[2023-03-09 07:39:36] [INFO ] [Real]Absence check using 7 positive place invariants in 3 ms returned sat
[2023-03-09 07:39:36] [INFO ] After 85ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:4
[2023-03-09 07:39:36] [INFO ] [Nat]Absence check using 7 positive place invariants in 2 ms returned sat
[2023-03-09 07:39:36] [INFO ] After 28ms SMT Verify possible using state equation in natural domain returned unsat :0 sat :4
[2023-03-09 07:39:36] [INFO ] After 62ms SMT Verify possible using trap constraints in natural domain returned unsat :0 sat :4
Attempting to minimize the solution found.
Minimization took 44 ms.
[2023-03-09 07:39:36] [INFO ] After 153ms SMT Verify possible using all constraints in natural domain returned unsat :0 sat :4
Fused 4 Parikh solutions to 3 different solutions.
Finished Parikh walk after 125 steps, including 0 resets, run visited all 4 properties in 4 ms. (steps per millisecond=31 )
Parikh walk visited 4 properties in 4 ms.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 5 place count 36 transition count 63
Applied a total of 5 rules in 10 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 10 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 63 transitions.
Finished random walk after 5478 steps, including 1 resets, run visited all 1 properties in 13 ms. (steps per millisecond=421 )
FORMULA Angiogenesis-PT-20-CTLFireability-00 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 1 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 36 transition count 63
Applied a total of 4 rules in 6 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 7 times.
Drop transitions removed 7 transitions
Iterating global reduction 0 with 7 rules applied. Total rules applied 10 place count 36 transition count 63
Applied a total of 10 rules in 4 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 6 times.
Drop transitions removed 6 transitions
Iterating global reduction 0 with 6 rules applied. Total rules applied 9 place count 36 transition count 63
Applied a total of 9 rules in 4 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 4 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 63 transitions.
Finished random walk after 126 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=126 )
FORMULA Angiogenesis-PT-20-CTLFireability-04 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 3 times.
Drop transitions removed 3 transitions
Iterating global reduction 0 with 3 rules applied. Total rules applied 6 place count 36 transition count 63
Drop transitions removed 1 transitions
Redundant transition composition rules discarded 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 7 place count 36 transition count 62
Applied a total of 7 rules in 5 ms. Remains 36 /38 variables (removed 2) and now considering 62/64 (removed 2) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 36/38 places, 62/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 62 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Input system was already deterministic with 64 transitions.
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:36] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:39:37] [INFO ] Export to MCC of 14 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-09 07:39:37] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 38 places, 64 transitions and 184 arcs took 1 ms.
Total runtime 1941 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Angiogenesis-PT-20
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/380
CTLFireability
FORMULA Angiogenesis-PT-20-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-20-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-20-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-20-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-20-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-20-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-20-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA Angiogenesis-PT-20-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678347712769
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
++ perl -pe 's/.*\.//g'
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/380/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/380/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/380/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 22 (type EXCL) for 21 Angiogenesis-PT-20-CTLFireability-09
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 54 (type FNDP) for 24 Angiogenesis-PT-20-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type EQUN) for 24 Angiogenesis-PT-20-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type SRCH) for 24 Angiogenesis-PT-20-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 54 (type FNDP) for Angiogenesis-PT-20-CTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 55 (type EQUN) for Angiogenesis-PT-20-CTLFireability-10 (obsolete)
lola: CANCELED task # 57 (type SRCH) for Angiogenesis-PT-20-CTLFireability-10 (obsolete)
lola: FINISHED task # 57 (type SRCH) for Angiogenesis-PT-20-CTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 55 (type EQUN) for Angiogenesis-PT-20-CTLFireability-10
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 60 (type FNDP) for 24 Angiogenesis-PT-20-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type EQUN) for 24 Angiogenesis-PT-20-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SRCH) for 24 Angiogenesis-PT-20-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type SRCH) for Angiogenesis-PT-20-CTLFireability-10
lola: result : unknown
lola: markings : 45
lola: fired transitions : 88
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: FINISHED task # 60 (type FNDP) for Angiogenesis-PT-20-CTLFireability-10
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: result : true
lola: fired transitions : 10
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/380/CTLFireability-61.sara.
lola: CANCELED task # 61 (type EQUN) for Angiogenesis-PT-20-CTLFireability-10 (obsolete)
lola: FINISHED task # 61 (type EQUN) for Angiogenesis-PT-20-CTLFireability-10
lola: result : unknown
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
22 CTL EXCL 5/257 17/32 Angiogenesis-PT-20-CTLFireability-09 3913452 m, 782690 m/sec, 6330152 t fired, .
Time elapsed: 5 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 22 (type EXCL) for Angiogenesis-PT-20-CTLFireability-09
lola: result : true
lola: markings : 3913452
lola: fired transitions : 6330152
lola: time used : 5.000000
lola: memory pages used : 17
lola: LAUNCH task # 52 (type EXCL) for 51 Angiogenesis-PT-20-CTLFireability-15
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for Angiogenesis-PT-20-CTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 49 (type EXCL) for 48 Angiogenesis-PT-20-CTLFireability-14
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 49 (type EXCL) for Angiogenesis-PT-20-CTLFireability-14
lola: result : false
lola: markings : 1681090
lola: fired transitions : 4333865
lola: time used : 3.000000
lola: memory pages used : 8
lola: LAUNCH task # 46 (type EXCL) for 45 Angiogenesis-PT-20-CTLFireability-13
lola: time limit : 326 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 2/326 3/32 Angiogenesis-PT-20-CTLFireability-13 654109 m, 130821 m/sec, 2419734 t fired, .
Time elapsed: 10 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 7/326 8/32 Angiogenesis-PT-20-CTLFireability-13 1839462 m, 237070 m/sec, 8952435 t fired, .
Time elapsed: 15 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 12/326 13/32 Angiogenesis-PT-20-CTLFireability-13 3029118 m, 237931 m/sec, 15217685 t fired, .
Time elapsed: 20 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 17/326 17/32 Angiogenesis-PT-20-CTLFireability-13 4114076 m, 216991 m/sec, 21618255 t fired, .
Time elapsed: 25 secs. Pages in use: 17
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 22/326 22/32 Angiogenesis-PT-20-CTLFireability-13 5309018 m, 238988 m/sec, 27793551 t fired, .
Time elapsed: 30 secs. Pages in use: 22
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 27/326 27/32 Angiogenesis-PT-20-CTLFireability-13 6407289 m, 219654 m/sec, 34119497 t fired, .
Time elapsed: 35 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 CTL EXCL 32/326 31/32 Angiogenesis-PT-20-CTLFireability-13 7446063 m, 207754 m/sec, 40575372 t fired, .
Time elapsed: 40 secs. Pages in use: 31
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 46 (type EXCL) for Angiogenesis-PT-20-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 43 (type EXCL) for 42 Angiogenesis-PT-20-CTLFireability-12
lola: time limit : 355 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
43 CTL EXCL 5/355 19/32 Angiogenesis-PT-20-CTLFireability-12 4358605 m, 871721 m/sec, 6979006 t fired, .
Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: FINISHED task # 43 (type EXCL) for Angiogenesis-PT-20-CTLFireability-12
lola: result : true
lola: markings : 5551831
lola: fired transitions : 8985194
lola: time used : 7.000000
lola: memory pages used : 24
lola: LAUNCH task # 40 (type EXCL) for 39 Angiogenesis-PT-20-CTLFireability-11
lola: time limit : 394 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 3/394 10/32 Angiogenesis-PT-20-CTLFireability-11 2146823 m, 429364 m/sec, 3620310 t fired, .
Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 8/394 25/32 Angiogenesis-PT-20-CTLFireability-11 5635570 m, 697749 m/sec, 9577905 t fired, .
Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 13/394 32/32 Angiogenesis-PT-20-CTLFireability-11 7386173 m, 350120 m/sec, 16642395 t fired, .
Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 40 (type EXCL) for Angiogenesis-PT-20-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-10: CONJ 0 1 0 0 10 0 0 3
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 37 (type EXCL) for 24 Angiogenesis-PT-20-CTLFireability-10
lola: time limit : 441 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for Angiogenesis-PT-20-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 Angiogenesis-PT-20-CTLFireability-08
lola: time limit : 504 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 5/504 19/32 Angiogenesis-PT-20-CTLFireability-08 4372978 m, 874595 m/sec, 7001833 t fired, .
Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 19 (type EXCL) for Angiogenesis-PT-20-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 13 (type EXCL) for 12 Angiogenesis-PT-20-CTLFireability-06
lola: time limit : 586 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/586 10/32 Angiogenesis-PT-20-CTLFireability-06 2120238 m, 424047 m/sec, 7249007 t fired, .
Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/586 19/32 Angiogenesis-PT-20-CTLFireability-06 4219247 m, 419801 m/sec, 14481100 t fired, .
Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/586 27/32 Angiogenesis-PT-20-CTLFireability-06 6163118 m, 388774 m/sec, 21270996 t fired, .
Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 13 (type EXCL) for Angiogenesis-PT-20-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-01: EFAG 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 10 (type EXCL) for 9 Angiogenesis-PT-20-CTLFireability-05
lola: time limit : 700 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for Angiogenesis-PT-20-CTLFireability-05
lola: result : true
lola: markings : 1841127
lola: fired transitions : 2995836
lola: time used : 2.000000
lola: memory pages used : 8
lola: LAUNCH task # 7 (type EXCL) for 6 Angiogenesis-PT-20-CTLFireability-03
lola: time limit : 874 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for Angiogenesis-PT-20-CTLFireability-03
lola: result : true
lola: markings : 557707
lola: fired transitions : 927286
lola: time used : 1.000000
lola: memory pages used : 3
lola: LAUNCH task # 58 (type EXCL) for 0 Angiogenesis-PT-20-CTLFireability-01
lola: time limit : 1165 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for Angiogenesis-PT-20-CTLFireability-01
lola: result : false
lola: markings : 95350
lola: fired transitions : 167628
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 Angiogenesis-PT-20-CTLFireability-02
lola: time limit : 1748 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-01: EFAG true tscc_search
Angiogenesis-PT-20-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 2/1748 6/32 Angiogenesis-PT-20-CTLFireability-02 1336475 m, 267295 m/sec, 3484581 t fired, .
Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-01: EFAG true tscc_search
Angiogenesis-PT-20-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 7/1748 20/32 Angiogenesis-PT-20-CTLFireability-02 4463270 m, 625359 m/sec, 11614033 t fired, .
Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-01: EFAG true tscc_search
Angiogenesis-PT-20-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 12/1748 31/32 Angiogenesis-PT-20-CTLFireability-02 7216804 m, 550706 m/sec, 18958988 t fired, .
Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 4 (type EXCL) for Angiogenesis-PT-20-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-01: EFAG true tscc_search
Angiogenesis-PT-20-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: LAUNCH task # 16 (type EXCL) for 15 Angiogenesis-PT-20-CTLFireability-07
lola: time limit : 3480 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-01: EFAG true tscc_search
Angiogenesis-PT-20-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 5/3480 13/32 Angiogenesis-PT-20-CTLFireability-07 2829831 m, 565966 m/sec, 8560379 t fired, .
Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-01: EFAG true tscc_search
Angiogenesis-PT-20-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 10/3480 24/32 Angiogenesis-PT-20-CTLFireability-07 5483811 m, 530796 m/sec, 16521170 t fired, .
Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: CANCELED task # 16 (type EXCL) for Angiogenesis-PT-20-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-01: EFAG true tscc_search
Angiogenesis-PT-20-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-20-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-20-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 14
lola: Portfolio finished: no open tasks 14
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-20-CTLFireability-01: EFAG true tscc_search
Angiogenesis-PT-20-CTLFireability-02: CTL unknown AGGR
Angiogenesis-PT-20-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-05: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-06: CTL unknown AGGR
Angiogenesis-PT-20-CTLFireability-07: CTL unknown AGGR
Angiogenesis-PT-20-CTLFireability-08: CTL unknown AGGR
Angiogenesis-PT-20-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-10: CONJ true CONJ
Angiogenesis-PT-20-CTLFireability-11: CTL unknown AGGR
Angiogenesis-PT-20-CTLFireability-12: CTL true CTL model checker
Angiogenesis-PT-20-CTLFireability-13: CTL unknown AGGR
Angiogenesis-PT-20-CTLFireability-14: CTL false CTL model checker
Angiogenesis-PT-20-CTLFireability-15: CTL true CTL model checker
Time elapsed: 135 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Angiogenesis-PT-20"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Angiogenesis-PT-20, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595400346"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/Angiogenesis-PT-20.tgz
mv Angiogenesis-PT-20 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;