Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595300322.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is Angiogenesis-PT-05, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595300322
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 488K
-rw-r--r-- 1 mcc users 7.8K Feb 26 14:55 CTLCardinality.txt
-rw-r--r-- 1 mcc users 77K Feb 26 14:55 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.2K Feb 26 14:54 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Feb 26 14:54 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 15:31 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:31 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:31 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:31 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 26 14:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 132K Feb 26 14:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.7K Feb 26 14:55 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 56K Feb 26 14:55 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 33K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-00
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-01
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-02
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-03
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-04
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-05
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-06
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-07
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-08
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-09
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-10
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-11
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-12
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-13
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-14
FORMULA_NAME Angiogenesis-PT-05-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678347137103

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Angiogenesis-PT-05
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:32:20] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 07:32:20] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:32:20] [INFO ] Load time of PNML (sax parser for PT used): 45 ms
[2023-03-09 07:32:20] [INFO ] Transformed 39 places.
[2023-03-09 07:32:20] [INFO ] Transformed 64 transitions.
[2023-03-09 07:32:20] [INFO ] Parsed PT model containing 39 places and 64 transitions and 185 arcs in 128 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 8 ms.
Initial state reduction rules removed 1 formulas.
FORMULA Angiogenesis-PT-05-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 38 out of 39 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 39/39 places, 64/64 transitions.
Reduce places removed 1 places and 0 transitions.
Iterating post reduction 0 with 1 rules applied. Total rules applied 1 place count 38 transition count 64
Applied a total of 1 rules in 10 ms. Remains 38 /39 variables (removed 1) and now considering 64/64 (removed 0) transitions.
// Phase 1: matrix 64 rows 38 cols
[2023-03-09 07:32:20] [INFO ] Computed 7 place invariants in 14 ms
[2023-03-09 07:32:20] [INFO ] Implicit Places using invariants in 332 ms returned []
[2023-03-09 07:32:20] [INFO ] Invariant cache hit.
[2023-03-09 07:32:20] [INFO ] Implicit Places using invariants and state equation in 151 ms returned []
Implicit Place search using SMT with State Equation took 511 ms to find 0 implicit places.
[2023-03-09 07:32:20] [INFO ] Invariant cache hit.
[2023-03-09 07:32:21] [INFO ] Dead Transitions using invariants and state equation in 171 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 38/39 places, 64/64 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 701 ms. Remains : 38/39 places, 64/64 transitions.
Support contains 38 out of 38 places after structural reductions.
[2023-03-09 07:32:21] [INFO ] Flatten gal took : 39 ms
[2023-03-09 07:32:21] [INFO ] Flatten gal took : 7 ms
[2023-03-09 07:32:21] [INFO ] Input system was already deterministic with 64 transitions.
Incomplete random walk after 10000 steps, including 2 resets, run finished after 276 ms. (steps per millisecond=36 ) properties (out of 54) seen :49
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 23 ms. (steps per millisecond=434 ) properties (out of 5) seen :3
Finished Best-First random walk after 9026 steps, including 2 resets, run visited all 2 properties in 16 ms. (steps per millisecond=564 )
[2023-03-09 07:32:21] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:32:21] [INFO ] Flatten gal took : 13 ms
[2023-03-09 07:32:21] [INFO ] Input system was already deterministic with 64 transitions.
Computed a total of 0 stabilizing places and 0 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:21] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:32:21] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 10 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Partial Post-agglomeration rule applied 9 times.
Drop transitions removed 9 transitions
Iterating global reduction 0 with 9 rules applied. Total rules applied 9 place count 38 transition count 64
Applied a total of 9 rules in 8 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 8 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 36 transition count 63
Applied a total of 4 rules in 5 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 1 times.
Drop transitions removed 1 transitions
Iterating global reduction 0 with 1 rules applied. Total rules applied 4 place count 36 transition count 63
Applied a total of 4 rules in 3 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 5 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 5 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 6 times.
Drop transitions removed 6 transitions
Iterating global reduction 0 with 6 rules applied. Total rules applied 9 place count 36 transition count 63
Applied a total of 9 rules in 4 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 17 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 63 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 0 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 0 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in LTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Applied a total of 0 rules in 1 ms. Remains 38 /38 variables (removed 0) and now considering 64/64 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 38/38 places, 64/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 2 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 64 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 38/38 places, 64/64 transitions.
Performed 1 Pre agglomeration using Quasi-Persistent + Divergent Free condition..
Pre-agglomeration after 0 with 1 Pre rules applied. Total rules applied 0 place count 38 transition count 63
Deduced a syphon composed of 1 places in 0 ms
Reduce places removed 2 places and 0 transitions.
Iterating global reduction 0 with 3 rules applied. Total rules applied 3 place count 36 transition count 63
Partial Post-agglomeration rule applied 2 times.
Drop transitions removed 2 transitions
Iterating global reduction 0 with 2 rules applied. Total rules applied 5 place count 36 transition count 63
Applied a total of 5 rules in 5 ms. Remains 36 /38 variables (removed 2) and now considering 63/64 (removed 1) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 5 ms. Remains : 36/38 places, 63/64 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:32:22] [INFO ] Input system was already deterministic with 63 transitions.
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 3 ms
[2023-03-09 07:32:22] [INFO ] Flatten gal took : 4 ms
[2023-03-09 07:32:22] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 4 ms.
[2023-03-09 07:32:22] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 38 places, 64 transitions and 184 arcs took 1 ms.
Total runtime 2179 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT Angiogenesis-PT-05
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/374
CTLFireability

FORMULA Angiogenesis-PT-05-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-05-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678347443241

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/374/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/374/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/374/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 10 (type EXCL) for 9 Angiogenesis-PT-05-CTLFireability-03
lola: time limit : 163 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 10 (type EXCL) for Angiogenesis-PT-05-CTLFireability-03
lola: result : true
lola: markings : 17981
lola: fired transitions : 74378
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 44 (type EXCL) for 43 Angiogenesis-PT-05-CTLFireability-13
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for Angiogenesis-PT-05-CTLFireability-13
lola: result : true
lola: markings : 263804
lola: fired transitions : 809876
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 41 (type EXCL) for 40 Angiogenesis-PT-05-CTLFireability-12
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for Angiogenesis-PT-05-CTLFireability-12
lola: result : false
lola: markings : 5571
lola: fired transitions : 11132
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 35 (type EXCL) for 34 Angiogenesis-PT-05-CTLFireability-10
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 35 (type EXCL) for Angiogenesis-PT-05-CTLFireability-10
lola: result : true
lola: markings : 42078
lola: fired transitions : 124223
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 21 Angiogenesis-PT-05-CTLFireability-07
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for Angiogenesis-PT-05-CTLFireability-07
lola: result : true
lola: markings : 41378
lola: fired transitions : 118380
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 Angiogenesis-PT-05-CTLFireability-05
lola: time limit : 327 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 4/327 4/32 Angiogenesis-PT-05-CTLFireability-05 794547 m, 158909 m/sec, 5722047 t fired, .

Time elapsed: 5 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 9/327 8/32 Angiogenesis-PT-05-CTLFireability-05 1679103 m, 176911 m/sec, 12481118 t fired, .

Time elapsed: 10 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 14/327 9/32 Angiogenesis-PT-05-CTLFireability-05 1945758 m, 53331 m/sec, 18871637 t fired, .

Time elapsed: 15 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 19/327 13/32 Angiogenesis-PT-05-CTLFireability-05 2947000 m, 200248 m/sec, 25542497 t fired, .

Time elapsed: 20 secs. Pages in use: 13
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 24/327 14/32 Angiogenesis-PT-05-CTLFireability-05 3135001 m, 37600 m/sec, 32057031 t fired, .

Time elapsed: 25 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 29/327 18/32 Angiogenesis-PT-05-CTLFireability-05 4172407 m, 207481 m/sec, 38893850 t fired, .

Time elapsed: 30 secs. Pages in use: 18
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 34/327 19/32 Angiogenesis-PT-05-CTLFireability-05 4335737 m, 32666 m/sec, 45346372 t fired, .

Time elapsed: 35 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 39/327 23/32 Angiogenesis-PT-05-CTLFireability-05 5374244 m, 207701 m/sec, 52195431 t fired, .

Time elapsed: 40 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 44/327 24/32 Angiogenesis-PT-05-CTLFireability-05 5527703 m, 30691 m/sec, 58191259 t fired, .

Time elapsed: 45 secs. Pages in use: 24
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 49/327 27/32 Angiogenesis-PT-05-CTLFireability-05 6458631 m, 186185 m/sec, 64258002 t fired, .

Time elapsed: 50 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
16 CTL EXCL 54/327 29/32 Angiogenesis-PT-05-CTLFireability-05 6712161 m, 50706 m/sec, 70901306 t fired, .

Time elapsed: 55 secs. Pages in use: 29
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 16 (type EXCL) for Angiogenesis-PT-05-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 13 (type EXCL) for 12 Angiogenesis-PT-05-CTLFireability-04
lola: time limit : 354 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/354 4/32 Angiogenesis-PT-05-CTLFireability-04 939235 m, 187847 m/sec, 6279874 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 10/354 5/32 Angiogenesis-PT-05-CTLFireability-04 1081458 m, 28444 m/sec, 11903660 t fired, .

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 15/354 9/32 Angiogenesis-PT-05-CTLFireability-04 2122136 m, 208135 m/sec, 18162379 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 20/354 9/32 Angiogenesis-PT-05-CTLFireability-04 2138577 m, 3288 m/sec, 24484889 t fired, .

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 25/354 14/32 Angiogenesis-PT-05-CTLFireability-04 3141991 m, 200682 m/sec, 31006023 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 30/354 15/32 Angiogenesis-PT-05-CTLFireability-04 3404329 m, 52467 m/sec, 36496188 t fired, .

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 35/354 15/32 Angiogenesis-PT-05-CTLFireability-04 3415924 m, 2319 m/sec, 42736742 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 40/354 20/32 Angiogenesis-PT-05-CTLFireability-04 4663748 m, 249564 m/sec, 48969871 t fired, .

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 45/354 20/32 Angiogenesis-PT-05-CTLFireability-04 4694837 m, 6217 m/sec, 54324799 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 50/354 21/32 Angiogenesis-PT-05-CTLFireability-04 4918724 m, 44777 m/sec, 60227698 t fired, .

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 55/354 25/32 Angiogenesis-PT-05-CTLFireability-04 5959240 m, 208103 m/sec, 66064876 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 60/354 25/32 Angiogenesis-PT-05-CTLFireability-04 5976014 m, 3354 m/sec, 71068635 t fired, .

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 65/354 27/32 Angiogenesis-PT-05-CTLFireability-04 6265286 m, 57854 m/sec, 76913954 t fired, .

Time elapsed: 125 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 70/354 31/32 Angiogenesis-PT-05-CTLFireability-04 7252592 m, 197461 m/sec, 82863342 t fired, .

Time elapsed: 130 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 75/354 31/32 Angiogenesis-PT-05-CTLFireability-04 7269855 m, 3452 m/sec, 88103511 t fired, .

Time elapsed: 135 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 80/354 32/32 Angiogenesis-PT-05-CTLFireability-04 7644832 m, 74995 m/sec, 93863009 t fired, .

Time elapsed: 140 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 13 (type EXCL) for Angiogenesis-PT-05-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 145 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 7 (type EXCL) for 6 Angiogenesis-PT-05-CTLFireability-02
lola: time limit : 383 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/383 2/32 Angiogenesis-PT-05-CTLFireability-02 461523 m, 92304 m/sec, 3984495 t fired, .

Time elapsed: 150 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: FINISHED task # 7 (type EXCL) for Angiogenesis-PT-05-CTLFireability-02
lola: result : true
lola: markings : 647536
lola: fired transitions : 5627529
lola: time used : 8.000000
lola: memory pages used : 3
lola: LAUNCH task # 4 (type EXCL) for 3 Angiogenesis-PT-05-CTLFireability-01
lola: time limit : 430 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-01: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 2/430 3/32 Angiogenesis-PT-05-CTLFireability-01 670841 m, 134168 m/sec, 2442936 t fired, .

Time elapsed: 155 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: FINISHED task # 4 (type EXCL) for Angiogenesis-PT-05-CTLFireability-01
lola: result : false
lola: markings : 670850
lola: fired transitions : 4578689
lola: time used : 4.000000
lola: memory pages used : 3
lola: LAUNCH task # 1 (type EXCL) for 0 Angiogenesis-PT-05-CTLFireability-00
lola: time limit : 491 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 3/491 4/32 Angiogenesis-PT-05-CTLFireability-00 805734 m, 161146 m/sec, 3986261 t fired, .

Time elapsed: 160 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 8/491 8/32 Angiogenesis-PT-05-CTLFireability-00 1830997 m, 205052 m/sec, 10388929 t fired, .

Time elapsed: 165 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 13/491 10/32 Angiogenesis-PT-05-CTLFireability-00 2274233 m, 88647 m/sec, 16969144 t fired, .

Time elapsed: 170 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 18/491 13/32 Angiogenesis-PT-05-CTLFireability-00 3091572 m, 163467 m/sec, 23197320 t fired, .

Time elapsed: 175 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 23/491 18/32 Angiogenesis-PT-05-CTLFireability-00 4187708 m, 219227 m/sec, 29765682 t fired, .

Time elapsed: 180 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 28/491 19/32 Angiogenesis-PT-05-CTLFireability-00 4368100 m, 36078 m/sec, 36531348 t fired, .

Time elapsed: 185 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 33/491 23/32 Angiogenesis-PT-05-CTLFireability-00 5463023 m, 218984 m/sec, 43085808 t fired, .

Time elapsed: 190 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 38/491 28/32 Angiogenesis-PT-05-CTLFireability-00 6558909 m, 219177 m/sec, 49749452 t fired, .

Time elapsed: 195 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-07: CONJ 0 1 0 0 3 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-15: AFAG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 43/491 29/32 Angiogenesis-PT-05-CTLFireability-00 6749146 m, 38047 m/sec, 56609672 t fired, .

Time elapsed: 200 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: FINISHED task # 1 (type EXCL) for Angiogenesis-PT-05-CTLFireability-00
lola: result : true
lola: markings : 6765306
lola: fired transitions : 57297369
lola: time used : 44.000000
lola: memory pages used : 29
lola: LAUNCH task # 47 (type EXCL) for 46 Angiogenesis-PT-05-CTLFireability-15
lola: time limit : 566 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for Angiogenesis-PT-05-CTLFireability-15
lola: result : false
lola: markings : 4204
lola: fired transitions : 7679
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 21 Angiogenesis-PT-05-CTLFireability-07
lola: time limit : 679 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for Angiogenesis-PT-05-CTLFireability-07
lola: result : false
lola: markings : 3901
lola: fired transitions : 11023
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 32 (type EXCL) for 31 Angiogenesis-PT-05-CTLFireability-09
lola: time limit : 849 sec
lola: memory limit: 32 pages
lola: FINISHED task # 32 (type EXCL) for Angiogenesis-PT-05-CTLFireability-09
lola: result : true
lola: markings : 4219
lola: fired transitions : 10443
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 Angiogenesis-PT-05-CTLFireability-06
lola: time limit : 1133 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 4/1133 4/32 Angiogenesis-PT-05-CTLFireability-06 842349 m, 168469 m/sec, 6470666 t fired, .

Time elapsed: 205 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 9/1133 8/32 Angiogenesis-PT-05-CTLFireability-06 1864033 m, 204336 m/sec, 13546885 t fired, .

Time elapsed: 210 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 14/1133 12/32 Angiogenesis-PT-05-CTLFireability-06 2692506 m, 165694 m/sec, 20548658 t fired, .

Time elapsed: 215 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 19/1133 14/32 Angiogenesis-PT-05-CTLFireability-06 3114288 m, 84356 m/sec, 27241652 t fired, .

Time elapsed: 220 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 24/1133 18/32 Angiogenesis-PT-05-CTLFireability-06 4198206 m, 216783 m/sec, 34430483 t fired, .

Time elapsed: 225 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 30/1133 19/32 Angiogenesis-PT-05-CTLFireability-06 4478061 m, 55971 m/sec, 41362009 t fired, .

Time elapsed: 231 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 35/1133 23/32 Angiogenesis-PT-05-CTLFireability-06 5458641 m, 196116 m/sec, 48199551 t fired, .

Time elapsed: 236 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 40/1133 27/32 Angiogenesis-PT-05-CTLFireability-06 6421125 m, 192496 m/sec, 55365022 t fired, .

Time elapsed: 241 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
19 CTL EXCL 45/1133 29/32 Angiogenesis-PT-05-CTLFireability-06 6726807 m, 61136 m/sec, 62379698 t fired, .

Time elapsed: 246 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 19 (type EXCL) for Angiogenesis-PT-05-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-05-CTLFireability-11: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 251 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: LAUNCH task # 38 (type EXCL) for 37 Angiogenesis-PT-05-CTLFireability-11
lola: time limit : 1674 sec
lola: memory limit: 32 pages
lola: FINISHED task # 38 (type EXCL) for Angiogenesis-PT-05-CTLFireability-11
lola: result : true
lola: markings : 58430
lola: fired transitions : 175362
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 Angiogenesis-PT-05-CTLFireability-08
lola: time limit : 3349 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/3349 4/32 Angiogenesis-PT-05-CTLFireability-08 835116 m, 167023 m/sec, 6379593 t fired, .

Time elapsed: 256 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/3349 8/32 Angiogenesis-PT-05-CTLFireability-08 1839532 m, 200883 m/sec, 12861656 t fired, .

Time elapsed: 261 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 15/3349 9/32 Angiogenesis-PT-05-CTLFireability-08 2049707 m, 42035 m/sec, 18612376 t fired, .

Time elapsed: 266 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 20/3349 13/32 Angiogenesis-PT-05-CTLFireability-08 3066172 m, 203293 m/sec, 25666393 t fired, .

Time elapsed: 271 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 25/3349 18/32 Angiogenesis-PT-05-CTLFireability-08 4087813 m, 204328 m/sec, 32903050 t fired, .

Time elapsed: 276 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 30/3349 19/32 Angiogenesis-PT-05-CTLFireability-08 4338173 m, 50072 m/sec, 39821683 t fired, .

Time elapsed: 281 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 35/3349 23/32 Angiogenesis-PT-05-CTLFireability-08 5417988 m, 215963 m/sec, 46897657 t fired, .

Time elapsed: 286 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 40/3349 25/32 Angiogenesis-PT-05-CTLFireability-08 5981292 m, 112660 m/sec, 53933455 t fired, .

Time elapsed: 291 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 45/3349 28/32 Angiogenesis-PT-05-CTLFireability-08 6685435 m, 140828 m/sec, 61083478 t fired, .

Time elapsed: 296 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: CANCELED task # 29 (type EXCL) for Angiogenesis-PT-05-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-05-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-05-CTLFireability-08: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 301 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 15
lola: Portfolio finished: no open tasks 15

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-05-CTLFireability-00: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-01: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-02: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-03: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-04: CTL unknown AGGR
Angiogenesis-PT-05-CTLFireability-05: CTL unknown AGGR
Angiogenesis-PT-05-CTLFireability-06: CTL unknown AGGR
Angiogenesis-PT-05-CTLFireability-07: CONJ false CTL model checker
Angiogenesis-PT-05-CTLFireability-08: CTL unknown AGGR
Angiogenesis-PT-05-CTLFireability-09: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-10: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-11: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-12: CTL false CTL model checker
Angiogenesis-PT-05-CTLFireability-13: CTL true CTL model checker
Angiogenesis-PT-05-CTLFireability-15: AFAG false CTL model checker


Time elapsed: 301 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Angiogenesis-PT-05"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is Angiogenesis-PT-05, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595300322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Angiogenesis-PT-05.tgz
mv Angiogenesis-PT-05 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;