Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595200274.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AirplaneLD-PT-0200, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595200274
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.1M
-rw-r--r-- 1 mcc users 110K Feb 26 11:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 411K Feb 26 11:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 79K Feb 26 11:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 470K Feb 26 11:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 50K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 143K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 47K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 213K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 224K Feb 26 11:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 807K Feb 26 11:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 87K Feb 26 11:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 507K Feb 26 11:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 31K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 872K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-00
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-01
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-02
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-03
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-04
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-05
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-06
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-07
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-08
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-09
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-10
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-11
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-12
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-13
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-14
FORMULA_NAME AirplaneLD-PT-0200-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678345312493

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-PT-0200
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:01:55] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 07:01:55] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:01:55] [INFO ] Load time of PNML (sax parser for PT used): 151 ms
[2023-03-09 07:01:55] [INFO ] Transformed 1419 places.
[2023-03-09 07:01:55] [INFO ] Transformed 1608 transitions.
[2023-03-09 07:01:55] [INFO ] Parsed PT model containing 1419 places and 1608 transitions and 6128 arcs in 259 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 53 ms.
Reduce places removed 602 places and 0 transitions.
Support contains 814 out of 817 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 817/817 places, 1608/1608 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 814 transition count 1608
Applied a total of 3 rules in 24 ms. Remains 814 /817 variables (removed 3) and now considering 1608/1608 (removed 0) transitions.
// Phase 1: matrix 1608 rows 814 cols
[2023-03-09 07:01:56] [INFO ] Computed 1 place invariants in 91 ms
[2023-03-09 07:01:56] [INFO ] Implicit Places using invariants in 672 ms returned []
[2023-03-09 07:01:56] [INFO ] Invariant cache hit.
[2023-03-09 07:01:57] [INFO ] Implicit Places using invariants and state equation in 744 ms returned []
Implicit Place search using SMT with State Equation took 1452 ms to find 0 implicit places.
[2023-03-09 07:01:57] [INFO ] Invariant cache hit.
[2023-03-09 07:01:58] [INFO ] Dead Transitions using invariants and state equation in 1011 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 814/817 places, 1608/1608 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2490 ms. Remains : 814/817 places, 1608/1608 transitions.
Support contains 814 out of 814 places after structural reductions.
[2023-03-09 07:01:59] [INFO ] Flatten gal took : 193 ms
[2023-03-09 07:01:59] [INFO ] Flatten gal took : 167 ms
[2023-03-09 07:01:59] [INFO ] Input system was already deterministic with 1608 transitions.
Incomplete random walk after 10000 steps, including 1258 resets, run finished after 750 ms. (steps per millisecond=13 ) properties (out of 45) seen :29
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=58 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 21 ms. (steps per millisecond=47 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 6 ms. (steps per millisecond=166 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 1 ms. (steps per millisecond=1001 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 14 ms. (steps per millisecond=71 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 1 ms. (steps per millisecond=1001 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 16) seen :0
Running SMT prover for 16 properties.
[2023-03-09 07:02:00] [INFO ] Invariant cache hit.
[2023-03-09 07:02:02] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 14 ms returned sat
[2023-03-09 07:02:02] [INFO ] After 480ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:16
[2023-03-09 07:02:02] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 07:02:05] [INFO ] After 2064ms SMT Verify possible using state equation in natural domain returned unsat :5 sat :11
[2023-03-09 07:02:06] [INFO ] After 3213ms SMT Verify possible using trap constraints in natural domain returned unsat :5 sat :11
Attempting to minimize the solution found.
Minimization took 728 ms.
[2023-03-09 07:02:07] [INFO ] After 4693ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :11
Fused 16 Parikh solutions to 11 different solutions.
Finished Parikh walk after 6 steps, including 0 resets, run visited all 1 properties in 1 ms. (steps per millisecond=6 )
Parikh walk visited 11 properties in 23 ms.
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
[2023-03-09 07:02:07] [INFO ] Flatten gal took : 63 ms
[2023-03-09 07:02:07] [INFO ] Flatten gal took : 66 ms
[2023-03-09 07:02:07] [INFO ] Input system was already deterministic with 1608 transitions.
Support contains 620 out of 814 places (down from 717) after GAL structural reductions.
Computed a total of 814 stabilizing places and 1608 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 814 transition count 1608
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 4 formulas.
FORMULA AirplaneLD-PT-0200-CTLFireability-06 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-PT-0200-CTLFireability-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in SI_CTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Graph (complete) has 1112 edges and 814 vertex of which 613 are kept as prefixes of interest. Removing 201 places using SCC suffix rule.44 ms
Discarding 201 places :
Also discarding 200 output transitions
Drop transitions removed 200 transitions
Ensure Unique test removed 199 transitions
Reduce isomorphic transitions removed 199 transitions.
Iterating post reduction 0 with 199 rules applied. Total rules applied 200 place count 613 transition count 1209
Discarding 298 places :
Symmetric choice reduction at 1 with 298 rule applications. Total rules 498 place count 315 transition count 911
Iterating global reduction 1 with 298 rules applied. Total rules applied 796 place count 315 transition count 911
Ensure Unique test removed 298 transitions
Reduce isomorphic transitions removed 298 transitions.
Iterating post reduction 1 with 298 rules applied. Total rules applied 1094 place count 315 transition count 613
Applied a total of 1094 rules in 76 ms. Remains 315 /814 variables (removed 499) and now considering 613/1608 (removed 995) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 76 ms. Remains : 315/814 places, 613/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 15 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 17 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 613 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 394 places :
Symmetric choice reduction at 0 with 394 rule applications. Total rules 394 place count 420 transition count 1214
Iterating global reduction 0 with 394 rules applied. Total rules applied 788 place count 420 transition count 1214
Ensure Unique test removed 394 transitions
Reduce isomorphic transitions removed 394 transitions.
Iterating post reduction 0 with 394 rules applied. Total rules applied 1182 place count 420 transition count 820
Applied a total of 1182 rules in 20 ms. Remains 420 /814 variables (removed 394) and now considering 820/1608 (removed 788) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 20 ms. Remains : 420/814 places, 820/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 21 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 27 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 820 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 795 places :
Symmetric choice reduction at 0 with 795 rule applications. Total rules 795 place count 19 transition count 813
Iterating global reduction 0 with 795 rules applied. Total rules applied 1590 place count 19 transition count 813
Ensure Unique test removed 795 transitions
Reduce isomorphic transitions removed 795 transitions.
Iterating post reduction 0 with 795 rules applied. Total rules applied 2385 place count 19 transition count 18
Applied a total of 2385 rules in 28 ms. Remains 19 /814 variables (removed 795) and now considering 18/1608 (removed 1590) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 28 ms. Remains : 19/814 places, 18/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Graph (complete) has 1112 edges and 814 vertex of which 612 are kept as prefixes of interest. Removing 202 places using SCC suffix rule.2 ms
Discarding 202 places :
Also discarding 400 output transitions
Drop transitions removed 400 transitions
Discarding 496 places :
Symmetric choice reduction at 0 with 496 rule applications. Total rules 497 place count 116 transition count 712
Iterating global reduction 0 with 496 rules applied. Total rules applied 993 place count 116 transition count 712
Ensure Unique test removed 496 transitions
Reduce isomorphic transitions removed 496 transitions.
Iterating post reduction 0 with 496 rules applied. Total rules applied 1489 place count 116 transition count 216
Applied a total of 1489 rules in 18 ms. Remains 116 /814 variables (removed 698) and now considering 216/1608 (removed 1392) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 18 ms. Remains : 116/814 places, 216/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 216 transitions.
Finished random walk after 14 steps, including 1 resets, run visited all 1 properties in 1 ms. (steps per millisecond=14 )
FORMULA AirplaneLD-PT-0200-CTLFireability-03 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 597 places :
Symmetric choice reduction at 0 with 597 rule applications. Total rules 597 place count 217 transition count 1011
Iterating global reduction 0 with 597 rules applied. Total rules applied 1194 place count 217 transition count 1011
Ensure Unique test removed 597 transitions
Reduce isomorphic transitions removed 597 transitions.
Iterating post reduction 0 with 597 rules applied. Total rules applied 1791 place count 217 transition count 414
Applied a total of 1791 rules in 12 ms. Remains 217 /814 variables (removed 597) and now considering 414/1608 (removed 1194) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 13 ms. Remains : 217/814 places, 414/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 11 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 15 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 414 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 694 places :
Symmetric choice reduction at 0 with 694 rule applications. Total rules 694 place count 120 transition count 914
Iterating global reduction 0 with 694 rules applied. Total rules applied 1388 place count 120 transition count 914
Ensure Unique test removed 694 transitions
Reduce isomorphic transitions removed 694 transitions.
Iterating post reduction 0 with 694 rules applied. Total rules applied 2082 place count 120 transition count 220
Applied a total of 2082 rules in 27 ms. Remains 120 /814 variables (removed 694) and now considering 220/1608 (removed 1388) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 27 ms. Remains : 120/814 places, 220/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 6 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 220 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 695 places :
Symmetric choice reduction at 0 with 695 rule applications. Total rules 695 place count 119 transition count 913
Iterating global reduction 0 with 695 rules applied. Total rules applied 1390 place count 119 transition count 913
Ensure Unique test removed 695 transitions
Reduce isomorphic transitions removed 695 transitions.
Iterating post reduction 0 with 695 rules applied. Total rules applied 2085 place count 119 transition count 218
Applied a total of 2085 rules in 9 ms. Remains 119 /814 variables (removed 695) and now considering 218/1608 (removed 1390) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 9 ms. Remains : 119/814 places, 218/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 5 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 218 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 793 places :
Symmetric choice reduction at 0 with 793 rule applications. Total rules 793 place count 21 transition count 815
Iterating global reduction 0 with 793 rules applied. Total rules applied 1586 place count 21 transition count 815
Ensure Unique test removed 793 transitions
Reduce isomorphic transitions removed 793 transitions.
Iterating post reduction 0 with 793 rules applied. Total rules applied 2379 place count 21 transition count 22
Applied a total of 2379 rules in 7 ms. Remains 21 /814 variables (removed 793) and now considering 22/1608 (removed 1586) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 21/814 places, 22/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 792 places :
Symmetric choice reduction at 0 with 792 rule applications. Total rules 792 place count 22 transition count 816
Iterating global reduction 0 with 792 rules applied. Total rules applied 1584 place count 22 transition count 816
Ensure Unique test removed 792 transitions
Reduce isomorphic transitions removed 792 transitions.
Iterating post reduction 0 with 792 rules applied. Total rules applied 2376 place count 22 transition count 24
Applied a total of 2376 rules in 6 ms. Remains 22 /814 variables (removed 792) and now considering 24/1608 (removed 1584) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 18 ms. Remains : 22/814 places, 24/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 795 places :
Symmetric choice reduction at 0 with 795 rule applications. Total rules 795 place count 19 transition count 813
Iterating global reduction 0 with 795 rules applied. Total rules applied 1590 place count 19 transition count 813
Ensure Unique test removed 795 transitions
Reduce isomorphic transitions removed 795 transitions.
Iterating post reduction 0 with 795 rules applied. Total rules applied 2385 place count 19 transition count 18
Applied a total of 2385 rules in 7 ms. Remains 19 /814 variables (removed 795) and now considering 18/1608 (removed 1590) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 8 ms. Remains : 19/814 places, 18/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 789 places :
Symmetric choice reduction at 0 with 789 rule applications. Total rules 789 place count 25 transition count 819
Iterating global reduction 0 with 789 rules applied. Total rules applied 1578 place count 25 transition count 819
Ensure Unique test removed 789 transitions
Reduce isomorphic transitions removed 789 transitions.
Iterating post reduction 0 with 789 rules applied. Total rules applied 2367 place count 25 transition count 30
Applied a total of 2367 rules in 7 ms. Remains 25 /814 variables (removed 789) and now considering 30/1608 (removed 1578) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 7 ms. Remains : 25/814 places, 30/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 792 places :
Symmetric choice reduction at 0 with 792 rule applications. Total rules 792 place count 22 transition count 816
Iterating global reduction 0 with 792 rules applied. Total rules applied 1584 place count 22 transition count 816
Ensure Unique test removed 792 transitions
Reduce isomorphic transitions removed 792 transitions.
Iterating post reduction 0 with 792 rules applied. Total rules applied 2376 place count 22 transition count 24
Applied a total of 2376 rules in 6 ms. Remains 22 /814 variables (removed 792) and now considering 24/1608 (removed 1584) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 22/814 places, 24/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 794 places :
Symmetric choice reduction at 0 with 794 rule applications. Total rules 794 place count 20 transition count 814
Iterating global reduction 0 with 794 rules applied. Total rules applied 1588 place count 20 transition count 814
Ensure Unique test removed 794 transitions
Reduce isomorphic transitions removed 794 transitions.
Iterating post reduction 0 with 794 rules applied. Total rules applied 2382 place count 20 transition count 20
Applied a total of 2382 rules in 6 ms. Remains 20 /814 variables (removed 794) and now considering 20/1608 (removed 1588) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 20/814 places, 20/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 814/814 places, 1608/1608 transitions.
Discarding 792 places :
Symmetric choice reduction at 0 with 792 rule applications. Total rules 792 place count 22 transition count 816
Iterating global reduction 0 with 792 rules applied. Total rules applied 1584 place count 22 transition count 816
Ensure Unique test removed 792 transitions
Reduce isomorphic transitions removed 792 transitions.
Iterating post reduction 0 with 792 rules applied. Total rules applied 2376 place count 22 transition count 24
Applied a total of 2376 rules in 6 ms. Remains 22 /814 variables (removed 792) and now considering 24/1608 (removed 1584) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 6 ms. Remains : 22/814 places, 24/1608 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:02:08] [INFO ] Input system was already deterministic with 24 transitions.
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 50 ms
[2023-03-09 07:02:08] [INFO ] Flatten gal took : 51 ms
[2023-03-09 07:02:08] [INFO ] Export to MCC of 13 properties in file /home/mcc/execution/CTLFireability.sr.xml took 12 ms.
[2023-03-09 07:02:08] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 814 places, 1608 transitions and 3520 arcs took 5 ms.
Total runtime 13348 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AirplaneLD-PT-0200
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/377
CTLFireability

FORMULA AirplaneLD-PT-0200-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678345663113

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/377/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/377/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/377/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 47 (type SKEL/SRCH) for 22 AirplaneLD-PT-0200-CTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 47 (type SKEL/SRCH) for AirplaneLD-PT-0200-CTLFireability-08
lola: result : false
lola: markings : 10
lola: fired transitions : 22
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 49 (type SKEL/SRCH) for 38 AirplaneLD-PT-0200-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 49 (type SKEL/SRCH) for AirplaneLD-PT-0200-CTLFireability-12
lola: result : true
lola: markings : 9
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: LAUNCH task # 17 (type EXCL) for 16 AirplaneLD-PT-0200-CTLFireability-05
lola: time limit : 198 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: FINISHED task # 17 (type EXCL) for AirplaneLD-PT-0200-CTLFireability-05
lola: result : false
lola: markings : 10
lola: fired transitions : 16
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 20 (type EXCL) for 19 AirplaneLD-PT-0200-CTLFireability-07
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0200-CTLFireability-05: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-12: F 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 4/255 2/32 AirplaneLD-PT-0200-CTLFireability-07 195765 m, 39153 m/sec, 667151 t fired, .

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AirplaneLD-PT-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
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AirplaneLD-PT-0200-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-12: F 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 9/255 4/32 AirplaneLD-PT-0200-CTLFireability-07 449033 m, 50653 m/sec, 1542171 t fired, .

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AirplaneLD-PT-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
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AirplaneLD-PT-0200-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
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AirplaneLD-PT-0200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-12: F 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 14/255 6/32 AirplaneLD-PT-0200-CTLFireability-07 702606 m, 50714 m/sec, 2415833 t fired, .

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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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AirplaneLD-PT-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-12: F 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 19/255 7/32 AirplaneLD-PT-0200-CTLFireability-07 725388 m, 4556 m/sec, 2768497 t fired, .

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lola: FINISHED task # 20 (type EXCL) for AirplaneLD-PT-0200-CTLFireability-07
lola: result : true
lola: markings : 727622
lola: fired transitions : 3225685
lola: time used : 23.000000
lola: memory pages used : 7
lola: LAUNCH task # 45 (type EXCL) for 44 AirplaneLD-PT-0200-CTLFireability-15
lola: time limit : 273 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for AirplaneLD-PT-0200-CTLFireability-15
lola: result : false
lola: markings : 8174
lola: fired transitions : 11630
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 AirplaneLD-PT-0200-CTLFireability-14
lola: time limit : 296 sec
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lola: FINISHED task # 42 (type EXCL) for AirplaneLD-PT-0200-CTLFireability-14
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 AirplaneLD-PT-0200-CTLFireability-11
lola: time limit : 323 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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AirplaneLD-PT-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
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AirplaneLD-PT-0200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-12: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 1/323 1/32 AirplaneLD-PT-0200-CTLFireability-11 61581 m, 12316 m/sec, 146762 t fired, .

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AirplaneLD-PT-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-02: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-09: DISJ 0 2 0 0 2 0 0 0
AirplaneLD-PT-0200-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
AirplaneLD-PT-0200-CTLFireability-12: F 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 CTL EXCL 6/323 4/32 AirplaneLD-PT-0200-CTLFireability-11 471384 m, 81960 m/sec, 1149068 t fired, .

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AirplaneLD-PT-0200-CTLFireability-05: CTL false CTL model checker
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36 CTL EXCL 11/323 7/32 AirplaneLD-PT-0200-CTLFireability-11 724412 m, 50605 m/sec, 1847961 t fired, .

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4 CTL EXCL 107/1133 28/32 AirplaneLD-PT-0200-CTLFireability-01 3272031 m, 56695 m/sec, 14112208 t fired, .

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AirplaneLD-PT-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-09: DISJ false DISJ
AirplaneLD-PT-0200-CTLFireability-10: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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4 CTL EXCL 112/1133 30/32 AirplaneLD-PT-0200-CTLFireability-01 3471693 m, 39932 m/sec, 14849684 t fired, .

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AirplaneLD-PT-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-09: DISJ false DISJ
AirplaneLD-PT-0200-CTLFireability-10: CTL false CTL model checker
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AirplaneLD-PT-0200-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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4 CTL EXCL 117/1133 30/32 AirplaneLD-PT-0200-CTLFireability-01 3472495 m, 160 m/sec, 15012218 t fired, .

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AirplaneLD-PT-0200-CTLFireability-07: CTL true CTL model checker
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AirplaneLD-PT-0200-CTLFireability-10: CTL false CTL model checker
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AirplaneLD-PT-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-09: DISJ false DISJ
AirplaneLD-PT-0200-CTLFireability-10: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0200-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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AirplaneLD-PT-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-08: CTL false CTL model checker
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AirplaneLD-PT-0200-CTLFireability-01: CTL 0 0 0 0 1 0 1 0
AirplaneLD-PT-0200-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
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lola: LAUNCH task # 50 (type EXCL) for 38 AirplaneLD-PT-0200-CTLFireability-12
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lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for AirplaneLD-PT-0200-CTLFireability-12
lola: result : true
lola: markings : 11
lola: fired transitions : 10
lola: time used : 0.000000
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lola: result : true
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lola: fired transitions : 423
lola: time used : 0.000000
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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0200-CTLFireability-00: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-01: CTL unknown AGGR
AirplaneLD-PT-0200-CTLFireability-02: DISJ true CTL model checker
AirplaneLD-PT-0200-CTLFireability-04: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-05: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-07: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-08: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-09: DISJ false DISJ
AirplaneLD-PT-0200-CTLFireability-10: CTL false CTL model checker
AirplaneLD-PT-0200-CTLFireability-11: CTL unknown AGGR
AirplaneLD-PT-0200-CTLFireability-12: F false state space / EG
AirplaneLD-PT-0200-CTLFireability-14: CTL true CTL model checker
AirplaneLD-PT-0200-CTLFireability-15: CTL false CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0200"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AirplaneLD-PT-0200, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595200274"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0200.tgz
mv AirplaneLD-PT-0200 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;