About the Execution of LoLa+red for AirplaneLD-PT-0200
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
836.995 | 3600000.00 | 276594.00 | 134.70 | FTTFTFFTTTTFFF?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595200273.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AirplaneLD-PT-0200, examination is CTLCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595200273
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.1M
-rw-r--r-- 1 mcc users 110K Feb 26 11:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 411K Feb 26 11:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 79K Feb 26 11:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 470K Feb 26 11:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 50K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 143K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 47K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 213K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 224K Feb 26 11:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 807K Feb 26 11:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 87K Feb 26 11:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 507K Feb 26 11:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 31K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 872K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-00
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-01
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-02
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-03
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-04
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-05
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-06
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-07
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-08
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-09
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-10
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-11
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-12
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-13
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-14
FORMULA_NAME AirplaneLD-PT-0200-CTLCardinality-15
=== Now, execution of the tool begins
BK_START 1678345304596
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLCardinality
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-PT-0200
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 07:01:47] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLCardinality, -timeout, 360, -rebuildPNML]
[2023-03-09 07:01:47] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 07:01:47] [INFO ] Load time of PNML (sax parser for PT used): 126 ms
[2023-03-09 07:01:47] [INFO ] Transformed 1419 places.
[2023-03-09 07:01:47] [INFO ] Transformed 1608 transitions.
[2023-03-09 07:01:47] [INFO ] Parsed PT model containing 1419 places and 1608 transitions and 6128 arcs in 211 ms.
Parsed 16 properties from file /home/mcc/execution/CTLCardinality.xml in 30 ms.
Reduce places removed 602 places and 0 transitions.
FORMULA AirplaneLD-PT-0200-CTLCardinality-08 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Support contains 817 out of 817 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 817/817 places, 1608/1608 transitions.
Applied a total of 0 rules in 29 ms. Remains 817 /817 variables (removed 0) and now considering 1608/1608 (removed 0) transitions.
// Phase 1: matrix 1608 rows 817 cols
[2023-03-09 07:01:47] [INFO ] Computed 3 place invariants in 135 ms
[2023-03-09 07:01:48] [INFO ] Implicit Places using invariants in 521 ms returned []
[2023-03-09 07:01:48] [INFO ] Invariant cache hit.
[2023-03-09 07:01:48] [INFO ] Implicit Places using invariants and state equation in 596 ms returned []
Implicit Place search using SMT with State Equation took 1154 ms to find 0 implicit places.
[2023-03-09 07:01:48] [INFO ] Invariant cache hit.
[2023-03-09 07:01:49] [INFO ] Dead Transitions using invariants and state equation in 638 ms found 0 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1827 ms. Remains : 817/817 places, 1608/1608 transitions.
Support contains 817 out of 817 places after structural reductions.
[2023-03-09 07:01:49] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
[2023-03-09 07:01:49] [INFO ] Flatten gal took : 106 ms
FORMULA AirplaneLD-PT-0200-CTLCardinality-15 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 07:01:49] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA AirplaneLD-PT-0200-CTLCardinality-13 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 07:01:49] [INFO ] Flatten gal took : 72 ms
[2023-03-09 07:01:49] [INFO ] Input system was already deterministic with 1608 transitions.
Incomplete random walk after 10000 steps, including 1256 resets, run finished after 756 ms. (steps per millisecond=13 ) properties (out of 38) seen :15
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 7 ms. (steps per millisecond=143 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 1 ms. (steps per millisecond=1001 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 4 ms. (steps per millisecond=250 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Incomplete Best-First random walk after 1001 steps, including 2 resets, run finished after 2 ms. (steps per millisecond=500 ) properties (out of 23) seen :0
Running SMT prover for 23 properties.
[2023-03-09 07:01:50] [INFO ] Invariant cache hit.
[2023-03-09 07:01:51] [INFO ] [Real]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 07:01:51] [INFO ] [Real]Absence check using 2 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 07:01:52] [INFO ] After 1264ms SMT Verify possible using all constraints in real domain returned unsat :6 sat :0 real:17
[2023-03-09 07:01:52] [INFO ] [Nat]Absence check using 2 positive place invariants in 1 ms returned sat
[2023-03-09 07:01:52] [INFO ] [Nat]Absence check using 2 positive and 1 generalized place invariants in 0 ms returned sat
[2023-03-09 07:01:53] [INFO ] After 1436ms SMT Verify possible using all constraints in natural domain returned unsat :23 sat :0
Fused 23 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 23 atomic propositions for a total of 13 simplifications.
FORMULA AirplaneLD-PT-0200-CTLCardinality-00 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-PT-0200-CTLCardinality-07 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 07:01:53] [INFO ] Initial state reduction rules for CTL removed 2 formulas.
[2023-03-09 07:01:53] [INFO ] Flatten gal took : 78 ms
[2023-03-09 07:01:53] [INFO ] Initial state reduction rules for CTL removed 1 formulas.
FORMULA AirplaneLD-PT-0200-CTLCardinality-06 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-PT-0200-CTLCardinality-03 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-PT-0200-CTLCardinality-01 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 78 ms
[2023-03-09 07:01:54] [INFO ] Input system was already deterministic with 1608 transitions.
Support contains 13 out of 817 places (down from 613) after GAL structural reductions.
FORMULA AirplaneLD-PT-0200-CTLCardinality-02 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-PT-0200-CTLCardinality-04 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
FORMULA AirplaneLD-PT-0200-CTLCardinality-10 TRUE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Computed a total of 817 stabilizing places and 1608 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 817 transition count 1608
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
Starting structural reductions in LTL mode, iteration 0 : 817/817 places, 1608/1608 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 814 transition count 1608
Discarding 795 places :
Symmetric choice reduction at 1 with 795 rule applications. Total rules 798 place count 19 transition count 813
Iterating global reduction 1 with 795 rules applied. Total rules applied 1593 place count 19 transition count 813
Ensure Unique test removed 795 transitions
Reduce isomorphic transitions removed 795 transitions.
Iterating post reduction 1 with 795 rules applied. Total rules applied 2388 place count 19 transition count 18
Applied a total of 2388 rules in 21 ms. Remains 19 /817 variables (removed 798) and now considering 18/1608 (removed 1590) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 21 ms. Remains : 19/817 places, 18/1608 transitions.
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:01:54] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 817/817 places, 1608/1608 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 814 transition count 1608
Discarding 792 places :
Symmetric choice reduction at 1 with 792 rule applications. Total rules 795 place count 22 transition count 816
Iterating global reduction 1 with 792 rules applied. Total rules applied 1587 place count 22 transition count 816
Ensure Unique test removed 792 transitions
Reduce isomorphic transitions removed 792 transitions.
Iterating post reduction 1 with 792 rules applied. Total rules applied 2379 place count 22 transition count 24
Applied a total of 2379 rules in 14 ms. Remains 22 /817 variables (removed 795) and now considering 24/1608 (removed 1584) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 14 ms. Remains : 22/817 places, 24/1608 transitions.
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:01:54] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 817/817 places, 1608/1608 transitions.
Graph (complete) has 2123 edges and 817 vertex of which 410 are kept as prefixes of interest. Removing 407 places using SCC suffix rule.5 ms
Discarding 407 places :
Also discarding 800 output transitions
Drop transitions removed 800 transitions
Discarding 398 places :
Symmetric choice reduction at 0 with 398 rule applications. Total rules 399 place count 12 transition count 410
Iterating global reduction 0 with 398 rules applied. Total rules applied 797 place count 12 transition count 410
Ensure Unique test removed 398 transitions
Reduce isomorphic transitions removed 398 transitions.
Iterating post reduction 0 with 398 rules applied. Total rules applied 1195 place count 12 transition count 12
Applied a total of 1195 rules in 22 ms. Remains 12 /817 variables (removed 805) and now considering 12/1608 (removed 1596) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 22 ms. Remains : 12/817 places, 12/1608 transitions.
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:01:54] [INFO ] Input system was already deterministic with 12 transitions.
Starting structural reductions in LTL mode, iteration 0 : 817/817 places, 1608/1608 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 814 transition count 1608
Discarding 791 places :
Symmetric choice reduction at 1 with 791 rule applications. Total rules 794 place count 23 transition count 817
Iterating global reduction 1 with 791 rules applied. Total rules applied 1585 place count 23 transition count 817
Ensure Unique test removed 791 transitions
Reduce isomorphic transitions removed 791 transitions.
Iterating post reduction 1 with 791 rules applied. Total rules applied 2376 place count 23 transition count 26
Applied a total of 2376 rules in 17 ms. Remains 23 /817 variables (removed 794) and now considering 26/1608 (removed 1582) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 17 ms. Remains : 23/817 places, 26/1608 transitions.
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:01:54] [INFO ] Input system was already deterministic with 26 transitions.
Starting structural reductions in LTL mode, iteration 0 : 817/817 places, 1608/1608 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 814 transition count 1608
Discarding 790 places :
Symmetric choice reduction at 1 with 790 rule applications. Total rules 793 place count 24 transition count 818
Iterating global reduction 1 with 790 rules applied. Total rules applied 1583 place count 24 transition count 818
Ensure Unique test removed 790 transitions
Reduce isomorphic transitions removed 790 transitions.
Iterating post reduction 1 with 790 rules applied. Total rules applied 2373 place count 24 transition count 28
Applied a total of 2373 rules in 11 ms. Remains 24 /817 variables (removed 793) and now considering 28/1608 (removed 1580) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 11 ms. Remains : 24/817 places, 28/1608 transitions.
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 0 ms
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 1 ms
[2023-03-09 07:01:54] [INFO ] Input system was already deterministic with 28 transitions.
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 40 ms
[2023-03-09 07:01:54] [INFO ] Flatten gal took : 39 ms
[2023-03-09 07:01:54] [INFO ] Export to MCC of 5 properties in file /home/mcc/execution/CTLCardinality.sr.xml took 3 ms.
[2023-03-09 07:01:54] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 817 places, 1608 transitions and 4520 arcs took 6 ms.
Total runtime 7132 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AirplaneLD-PT-0200
BK_EXAMINATION: CTLCardinality
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/377
FORMULA AirplaneLD-PT-0200-CTLCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-CTLCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-CTLCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-PT-0200-CTLCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393220 kB
MemFree: 15313784 kB
After kill :
MemTotal: 16393220 kB
MemFree: 16099920 kB
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLCardinality -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/377/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/377/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/377/CTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 20 (type SKEL/SRCH) for 9 AirplaneLD-PT-0200-CTLCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 20 (type SKEL/SRCH) for AirplaneLD-PT-0200-CTLCardinality-12
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 22 (type SKEL/SRCH) for 6 AirplaneLD-PT-0200-CTLCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 23 (type SKEL/SRCH) for 9 AirplaneLD-PT-0200-CTLCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 AirplaneLD-PT-0200-CTLCardinality-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 22 (type SKEL/SRCH) for AirplaneLD-PT-0200-CTLCardinality-11
lola: result : true
lola: markings : 10
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 23 (type SKEL/SRCH) for AirplaneLD-PT-0200-CTLCardinality-12
lola: result : false
lola: markings : 47
lola: fired transitions : 63
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 1 (type CNST) for AirplaneLD-PT-0200-CTLCardinality-05
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 12 (type EXCL) for 9 AirplaneLD-PT-0200-CTLCardinality-12
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 12 (type EXCL) for AirplaneLD-PT-0200-CTLCardinality-12
lola: result : false
lola: markings : 998
lola: fired transitions : 1466
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 17 (type EXCL) for 16 AirplaneLD-PT-0200-CTLCardinality-14
lola: time limit : 1199 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0200-CTLCardinality-05: INITIAL false preprocessing
AirplaneLD-PT-0200-CTLCardinality-12: CONJ false CTL model checker
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17 CTL EXCL 4/1199 1/32 AirplaneLD-PT-0200-CTLCardinality-14 103888 m, 20777 m/sec, 882339 t fired, .
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17 CTL EXCL 9/1199 2/32 AirplaneLD-PT-0200-CTLCardinality-14 213867 m, 21995 m/sec, 1836027 t fired, .
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Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0200"
export BK_EXAMINATION="CTLCardinality"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AirplaneLD-PT-0200, examination is CTLCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595200273"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0200.tgz
mv AirplaneLD-PT-0200 execution
cd execution
if [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "UpperBounds" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] || [ "CTLCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLCardinality" = "ReachabilityDeadlock" ] || [ "CTLCardinality" = "QuasiLiveness" ] || [ "CTLCardinality" = "StableMarking" ] || [ "CTLCardinality" = "Liveness" ] || [ "CTLCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;