Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813595200242.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
....................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is AirplaneLD-PT-0010, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813595200242
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 568K
-rw-r--r-- 1 mcc users 12K Feb 26 11:11 CTLCardinality.txt
-rw-r--r-- 1 mcc users 85K Feb 26 11:11 CTLCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 26 11:09 CTLFireability.txt
-rw-r--r-- 1 mcc users 68K Feb 26 11:09 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 6.2K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 31K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.3K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 11:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 99K Feb 26 11:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 13K Feb 26 11:13 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 89K Feb 26 11:13 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 48K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-00
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-01
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-02
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-03
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-04
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-05
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-06
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-07
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-08
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-09
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-10
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-11
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-12
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-13
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-14
FORMULA_NAME AirplaneLD-PT-0010-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678344971999

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-PT-0010
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 06:56:14] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 06:56:14] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 06:56:14] [INFO ] Load time of PNML (sax parser for PT used): 60 ms
[2023-03-09 06:56:14] [INFO ] Transformed 89 places.
[2023-03-09 06:56:14] [INFO ] Transformed 88 transitions.
[2023-03-09 06:56:14] [INFO ] Parsed PT model containing 89 places and 88 transitions and 333 arcs in 180 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 9 ms.
Reduce places removed 32 places and 0 transitions.
Support contains 54 out of 57 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 57/57 places, 88/88 transitions.
Reduce places removed 3 places and 0 transitions.
Iterating post reduction 0 with 3 rules applied. Total rules applied 3 place count 54 transition count 88
Applied a total of 3 rules in 22 ms. Remains 54 /57 variables (removed 3) and now considering 88/88 (removed 0) transitions.
// Phase 1: matrix 88 rows 54 cols
[2023-03-09 06:56:14] [INFO ] Computed 1 place invariants in 8 ms
[2023-03-09 06:56:14] [INFO ] Implicit Places using invariants in 224 ms returned []
[2023-03-09 06:56:14] [INFO ] Invariant cache hit.
[2023-03-09 06:56:14] [INFO ] Implicit Places using invariants and state equation in 130 ms returned []
Implicit Place search using SMT with State Equation took 404 ms to find 0 implicit places.
[2023-03-09 06:56:14] [INFO ] Invariant cache hit.
[2023-03-09 06:56:15] [INFO ] Dead Transitions using invariants and state equation in 261 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 54/57 places, 88/88 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 689 ms. Remains : 54/57 places, 88/88 transitions.
Support contains 54 out of 54 places after structural reductions.
[2023-03-09 06:56:15] [INFO ] Flatten gal took : 48 ms
[2023-03-09 06:56:15] [INFO ] Flatten gal took : 33 ms
[2023-03-09 06:56:15] [INFO ] Input system was already deterministic with 88 transitions.
Incomplete random walk after 10000 steps, including 1253 resets, run finished after 431 ms. (steps per millisecond=23 ) properties (out of 44) seen :36
Incomplete Best-First random walk after 10001 steps, including 53 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 75 resets, run finished after 26 ms. (steps per millisecond=384 ) properties (out of 8) seen :1
Incomplete Best-First random walk after 10001 steps, including 87 resets, run finished after 31 ms. (steps per millisecond=322 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 86 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 7) seen :0
Incomplete Best-First random walk after 10001 steps, including 74 resets, run finished after 18 ms. (steps per millisecond=555 ) properties (out of 7) seen :1
Incomplete Best-First random walk after 10001 steps, including 76 resets, run finished after 12 ms. (steps per millisecond=833 ) properties (out of 6) seen :1
Incomplete Best-First random walk after 10000 steps, including 95 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 5) seen :0
Incomplete Best-First random walk after 10001 steps, including 87 resets, run finished after 22 ms. (steps per millisecond=454 ) properties (out of 5) seen :0
Running SMT prover for 5 properties.
[2023-03-09 06:56:16] [INFO ] Invariant cache hit.
[2023-03-09 06:56:16] [INFO ] [Real]Absence check using 0 positive and 1 generalized place invariants in 1 ms returned sat
[2023-03-09 06:56:16] [INFO ] After 75ms SMT Verify possible using all constraints in real domain returned unsat :3 sat :0 real:2
[2023-03-09 06:56:16] [INFO ] [Nat]Absence check using 0 positive and 1 generalized place invariants in 6 ms returned sat
[2023-03-09 06:56:16] [INFO ] After 65ms SMT Verify possible using all constraints in natural domain returned unsat :5 sat :0
Fused 5 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 1 ms.
Successfully simplified 5 atomic propositions for a total of 16 simplifications.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 6 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 6 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 88 transitions.
Computed a total of 54 stabilizing places and 88 stable transitions
Complete graph has no SCC; deadlocks are unavoidable. place count 54 transition count 88
Detected that all paths lead to deadlock. Applying this knowledge to assert that all AP eventually converge (and all enablings converge to false).
AF dead knowledge conclusive for 3 formulas.
FORMULA AirplaneLD-PT-0010-CTLFireability-08 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 35 places :
Symmetric choice reduction at 0 with 35 rule applications. Total rules 35 place count 19 transition count 53
Iterating global reduction 0 with 35 rules applied. Total rules applied 70 place count 19 transition count 53
Ensure Unique test removed 35 transitions
Reduce isomorphic transitions removed 35 transitions.
Iterating post reduction 0 with 35 rules applied. Total rules applied 105 place count 19 transition count 18
Applied a total of 105 rules in 3 ms. Remains 19 /54 variables (removed 35) and now considering 18/88 (removed 70) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 19/54 places, 18/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 18 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 29 places :
Symmetric choice reduction at 0 with 29 rule applications. Total rules 29 place count 25 transition count 59
Iterating global reduction 0 with 29 rules applied. Total rules applied 58 place count 25 transition count 59
Ensure Unique test removed 29 transitions
Reduce isomorphic transitions removed 29 transitions.
Iterating post reduction 0 with 29 rules applied. Total rules applied 87 place count 25 transition count 30
Applied a total of 87 rules in 2 ms. Remains 25 /54 variables (removed 29) and now considering 30/88 (removed 58) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/54 places, 30/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 11 places :
Symmetric choice reduction at 0 with 11 rule applications. Total rules 11 place count 43 transition count 77
Iterating global reduction 0 with 11 rules applied. Total rules applied 22 place count 43 transition count 77
Ensure Unique test removed 11 transitions
Reduce isomorphic transitions removed 11 transitions.
Iterating post reduction 0 with 11 rules applied. Total rules applied 33 place count 43 transition count 66
Applied a total of 33 rules in 2 ms. Remains 43 /54 variables (removed 11) and now considering 66/88 (removed 22) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 43/54 places, 66/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 3 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 3 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 66 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 21 places :
Symmetric choice reduction at 0 with 21 rule applications. Total rules 21 place count 33 transition count 67
Iterating global reduction 0 with 21 rules applied. Total rules applied 42 place count 33 transition count 67
Ensure Unique test removed 21 transitions
Reduce isomorphic transitions removed 21 transitions.
Iterating post reduction 0 with 21 rules applied. Total rules applied 63 place count 33 transition count 46
Applied a total of 63 rules in 10 ms. Remains 33 /54 variables (removed 21) and now considering 46/88 (removed 42) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 10 ms. Remains : 33/54 places, 46/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 46 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 29 places :
Symmetric choice reduction at 0 with 29 rule applications. Total rules 29 place count 25 transition count 59
Iterating global reduction 0 with 29 rules applied. Total rules applied 58 place count 25 transition count 59
Ensure Unique test removed 29 transitions
Reduce isomorphic transitions removed 29 transitions.
Iterating post reduction 0 with 29 rules applied. Total rules applied 87 place count 25 transition count 30
Applied a total of 87 rules in 1 ms. Remains 25 /54 variables (removed 29) and now considering 30/88 (removed 58) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 25/54 places, 30/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 30 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 28 places :
Symmetric choice reduction at 0 with 28 rule applications. Total rules 28 place count 26 transition count 60
Iterating global reduction 0 with 28 rules applied. Total rules applied 56 place count 26 transition count 60
Ensure Unique test removed 28 transitions
Reduce isomorphic transitions removed 28 transitions.
Iterating post reduction 0 with 28 rules applied. Total rules applied 84 place count 26 transition count 32
Applied a total of 84 rules in 1 ms. Remains 26 /54 variables (removed 28) and now considering 32/88 (removed 56) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 26/54 places, 32/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 32 transitions.
Support contains 1 out of 26 places (down from 13) after GAL structural reductions.
Starting structural reductions in SI_CTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 31 places :
Symmetric choice reduction at 0 with 31 rule applications. Total rules 31 place count 23 transition count 57
Iterating global reduction 0 with 31 rules applied. Total rules applied 62 place count 23 transition count 57
Ensure Unique test removed 31 transitions
Reduce isomorphic transitions removed 31 transitions.
Iterating post reduction 0 with 31 rules applied. Total rules applied 93 place count 23 transition count 26
Applied a total of 93 rules in 5 ms. Remains 23 /54 variables (removed 31) and now considering 26/88 (removed 62) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 6 ms. Remains : 23/54 places, 26/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 26 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 30 places :
Symmetric choice reduction at 0 with 30 rule applications. Total rules 30 place count 24 transition count 58
Iterating global reduction 0 with 30 rules applied. Total rules applied 60 place count 24 transition count 58
Ensure Unique test removed 30 transitions
Reduce isomorphic transitions removed 30 transitions.
Iterating post reduction 0 with 30 rules applied. Total rules applied 90 place count 24 transition count 28
Applied a total of 90 rules in 2 ms. Remains 24 /54 variables (removed 30) and now considering 28/88 (removed 60) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 24/54 places, 28/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 2 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 28 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 34 places :
Symmetric choice reduction at 0 with 34 rule applications. Total rules 34 place count 20 transition count 54
Iterating global reduction 0 with 34 rules applied. Total rules applied 68 place count 20 transition count 54
Ensure Unique test removed 34 transitions
Reduce isomorphic transitions removed 34 transitions.
Iterating post reduction 0 with 34 rules applied. Total rules applied 102 place count 20 transition count 20
Applied a total of 102 rules in 1 ms. Remains 20 /54 variables (removed 34) and now considering 20/88 (removed 68) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 20/54 places, 20/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 33 places :
Symmetric choice reduction at 0 with 33 rule applications. Total rules 33 place count 21 transition count 55
Iterating global reduction 0 with 33 rules applied. Total rules applied 66 place count 21 transition count 55
Ensure Unique test removed 33 transitions
Reduce isomorphic transitions removed 33 transitions.
Iterating post reduction 0 with 33 rules applied. Total rules applied 99 place count 21 transition count 22
Applied a total of 99 rules in 2 ms. Remains 21 /54 variables (removed 33) and now considering 22/88 (removed 66) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 21/54 places, 22/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 0 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 33 places :
Symmetric choice reduction at 0 with 33 rule applications. Total rules 33 place count 21 transition count 55
Iterating global reduction 0 with 33 rules applied. Total rules applied 66 place count 21 transition count 55
Ensure Unique test removed 33 transitions
Reduce isomorphic transitions removed 33 transitions.
Iterating post reduction 0 with 33 rules applied. Total rules applied 99 place count 21 transition count 22
Applied a total of 99 rules in 2 ms. Remains 21 /54 variables (removed 33) and now considering 22/88 (removed 66) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 3 ms. Remains : 21/54 places, 22/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 22 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 32 places :
Symmetric choice reduction at 0 with 32 rule applications. Total rules 32 place count 22 transition count 56
Iterating global reduction 0 with 32 rules applied. Total rules applied 64 place count 22 transition count 56
Ensure Unique test removed 32 transitions
Reduce isomorphic transitions removed 32 transitions.
Iterating post reduction 0 with 32 rules applied. Total rules applied 96 place count 22 transition count 24
Applied a total of 96 rules in 1 ms. Remains 22 /54 variables (removed 32) and now considering 24/88 (removed 64) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 22/54 places, 24/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 32 places :
Symmetric choice reduction at 0 with 32 rule applications. Total rules 32 place count 22 transition count 56
Iterating global reduction 0 with 32 rules applied. Total rules applied 64 place count 22 transition count 56
Ensure Unique test removed 32 transitions
Reduce isomorphic transitions removed 32 transitions.
Iterating post reduction 0 with 32 rules applied. Total rules applied 96 place count 22 transition count 24
Applied a total of 96 rules in 1 ms. Remains 22 /54 variables (removed 32) and now considering 24/88 (removed 64) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1 ms. Remains : 22/54 places, 24/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 24 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 34 places :
Symmetric choice reduction at 0 with 34 rule applications. Total rules 34 place count 20 transition count 54
Iterating global reduction 0 with 34 rules applied. Total rules applied 68 place count 20 transition count 54
Ensure Unique test removed 34 transitions
Reduce isomorphic transitions removed 34 transitions.
Iterating post reduction 0 with 34 rules applied. Total rules applied 102 place count 20 transition count 20
Applied a total of 102 rules in 2 ms. Remains 20 /54 variables (removed 34) and now considering 20/88 (removed 68) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 20/54 places, 20/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 20 transitions.
Starting structural reductions in LTL mode, iteration 0 : 54/54 places, 88/88 transitions.
Discarding 34 places :
Symmetric choice reduction at 0 with 34 rule applications. Total rules 34 place count 20 transition count 54
Iterating global reduction 0 with 34 rules applied. Total rules applied 68 place count 20 transition count 54
Ensure Unique test removed 34 transitions
Reduce isomorphic transitions removed 34 transitions.
Iterating post reduction 0 with 34 rules applied. Total rules applied 102 place count 20 transition count 20
Applied a total of 102 rules in 2 ms. Remains 20 /54 variables (removed 34) and now considering 20/88 (removed 68) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 20/54 places, 20/88 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 1 ms
[2023-03-09 06:56:16] [INFO ] Input system was already deterministic with 20 transitions.
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 4 ms
[2023-03-09 06:56:16] [INFO ] Flatten gal took : 4 ms
[2023-03-09 06:56:16] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 2 ms.
[2023-03-09 06:56:16] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 54 places, 88 transitions and 195 arcs took 1 ms.
Total runtime 2672 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT AirplaneLD-PT-0010
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/380
CTLFireability

FORMULA AirplaneLD-PT-0010-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0010-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678344978775

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ perl -pe 's/.*\.//g'
++ sed s/.jar//
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/380/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/380/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/380/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: LAUNCH task # 14 (type EXCL) for 13 AirplaneLD-PT-0010-CTLFireability-03
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:715
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:742
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 62 (type FNDP) for 45 AirplaneLD-PT-0010-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 62 (type FNDP) for AirplaneLD-PT-0010-CTLFireability-12
lola: result : true
lola: fired transitions : 7
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 64 (type FNDP) for 0 AirplaneLD-PT-0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 0 AirplaneLD-PT-0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SRCH) for 0 AirplaneLD-PT-0010-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 67 (type SRCH) for AirplaneLD-PT-0010-CTLFireability-00
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 64 (type FNDP) for AirplaneLD-PT-0010-CTLFireability-00
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 65 (type EQUN) for AirplaneLD-PT-0010-CTLFireability-00 (obsolete)
lola: FINISHED task # 65 (type EQUN) for AirplaneLD-PT-0010-CTLFireability-00
lola: result : unknown
lola: FINISHED task # 14 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-03
lola: result : false
lola: markings : 43461
lola: fired transitions : 280751
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 59 (type EXCL) for 58 AirplaneLD-PT-0010-CTLFireability-15
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-15
lola: result : false
lola: markings : 325
lola: fired transitions : 362
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 55 AirplaneLD-PT-0010-CTLFireability-14
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-14
lola: result : true
lola: markings : 43197
lola: fired transitions : 47784
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 53 (type EXCL) for 52 AirplaneLD-PT-0010-CTLFireability-13
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 53 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-13
lola: result : false
lola: markings : 11
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 31 AirplaneLD-PT-0010-CTLFireability-10
lola: time limit : 300 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-10
lola: result : true
lola: markings : 43439
lola: fired transitions : 52600
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 31 AirplaneLD-PT-0010-CTLFireability-10
lola: time limit : 327 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-10
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 29 (type EXCL) for 28 AirplaneLD-PT-0010-CTLFireability-09
lola: time limit : 360 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-09
lola: result : false
lola: markings : 43462
lola: fired transitions : 259140
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 AirplaneLD-PT-0010-CTLFireability-07
lola: time limit : 400 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-07
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 AirplaneLD-PT-0010-CTLFireability-04
lola: time limit : 450 sec
lola: memory limit: 32 pages
lola: FINISHED task # 17 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-04
lola: result : false
lola: markings : 43232
lola: fired transitions : 224557
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 11 (type EXCL) for 10 AirplaneLD-PT-0010-CTLFireability-02
lola: time limit : 514 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-02
lola: result : true
lola: markings : 43462
lola: fired transitions : 227137
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 8 (type EXCL) for 7 AirplaneLD-PT-0010-CTLFireability-01
lola: time limit : 599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 8 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-01
lola: result : true
lola: markings : 43462
lola: fired transitions : 299361
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 3 (type EXCL) for 0 AirplaneLD-PT-0010-CTLFireability-00
lola: time limit : 719 sec
lola: memory limit: 32 pages
lola: FINISHED task # 3 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-00
lola: result : true
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 20 (type EXCL) for 19 AirplaneLD-PT-0010-CTLFireability-05
lola: time limit : 899 sec
lola: memory limit: 32 pages
lola: FINISHED task # 20 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-05
lola: result : true
lola: markings : 11
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 38 AirplaneLD-PT-0010-CTLFireability-11
lola: time limit : 1199 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-11
lola: result : false
lola: markings : 43462
lola: fired transitions : 356563
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 38 AirplaneLD-PT-0010-CTLFireability-11
lola: time limit : 1799 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-11
lola: result : false
lola: markings : 43462
lola: fired transitions : 231077
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 AirplaneLD-PT-0010-CTLFireability-06
lola: time limit : 3599 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for AirplaneLD-PT-0010-CTLFireability-06
lola: result : false
lola: markings : 5390
lola: fired transitions : 19745
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0010-CTLFireability-00: DISJ true state space /EXEG
AirplaneLD-PT-0010-CTLFireability-01: CTL true CTL model checker
AirplaneLD-PT-0010-CTLFireability-02: CTL true CTL model checker
AirplaneLD-PT-0010-CTLFireability-03: CTL false CTL model checker
AirplaneLD-PT-0010-CTLFireability-04: CTL false CTL model checker
AirplaneLD-PT-0010-CTLFireability-05: EFAGEF true tscc_search
AirplaneLD-PT-0010-CTLFireability-06: CTL false CTL model checker
AirplaneLD-PT-0010-CTLFireability-07: CTL false CTL model checker
AirplaneLD-PT-0010-CTLFireability-09: CTL false CTL model checker
AirplaneLD-PT-0010-CTLFireability-10: CONJ true CONJ
AirplaneLD-PT-0010-CTLFireability-11: DISJ false DISJ
AirplaneLD-PT-0010-CTLFireability-12: DISJ true findpath
AirplaneLD-PT-0010-CTLFireability-13: CTL false CTL model checker
AirplaneLD-PT-0010-CTLFireability-14: CTL true CTL model checker
AirplaneLD-PT-0010-CTLFireability-15: CTL false CTL model checker


Time elapsed: 1 secs. Pages in use: 2

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0010"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is AirplaneLD-PT-0010, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813595200242"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0010.tgz
mv AirplaneLD-PT-0010 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;