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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r007-oct2-167813594900007
Last Updated
May 14, 2023

About the Execution of LoLa+red for ARMCacheCoherence-PT-none

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3694.136 66273.00 177021.00 68.80 FTFTTFFFFFFTTTFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813594900007.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...........................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ARMCacheCoherence-PT-none, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813594900007
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 6.6K Feb 25 21:34 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 25 21:34 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 21:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 21:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 21:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 163K Feb 25 21:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 25 21:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 21:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:28 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 14M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-00
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-01
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-02
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-03
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-04
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-05
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-06
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-07
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-08
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-09
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-10
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-11
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-12
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-13
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-14
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-15

=== Now, execution of the tool begins

BK_START 1678334341547

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=ReachabilityFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ARMCacheCoherence-PT-none
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 03:59:04] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, ReachabilityFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 03:59:04] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 03:59:05] [INFO ] Load time of PNML (sax parser for PT used): 844 ms
[2023-03-09 03:59:05] [INFO ] Transformed 87 places.
[2023-03-09 03:59:05] [INFO ] Transformed 33676 transitions.
[2023-03-09 03:59:05] [INFO ] Found NUPN structural information;
[2023-03-09 03:59:05] [INFO ] Parsed PT model containing 87 places and 33676 transitions and 246935 arcs in 1153 ms.
Parsed 16 properties from file /home/mcc/execution/ReachabilityFireability.xml in 20 ms.
Working with output stream class java.io.PrintStream
Ensure Unique test removed 32425 transitions
Reduce redundant transitions removed 32425 transitions.
Incomplete random walk after 10000 steps, including 7 resets, run finished after 674 ms. (steps per millisecond=14 ) properties (out of 16) seen :5
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-14 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-11 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-06 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-02 FALSE TECHNIQUES TOPOLOGICAL RANDOM_WALK
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-01 TRUE TECHNIQUES TOPOLOGICAL RANDOM_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 46 ms. (steps per millisecond=217 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 59 ms. (steps per millisecond=169 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 61 ms. (steps per millisecond=163 ) properties (out of 11) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 27 ms. (steps per millisecond=370 ) properties (out of 11) seen :2
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-13 TRUE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-05 FALSE TECHNIQUES TOPOLOGICAL BESTFIRST_WALK
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 25 ms. (steps per millisecond=400 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 47 ms. (steps per millisecond=212 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 33 ms. (steps per millisecond=303 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 38 ms. (steps per millisecond=263 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 42 ms. (steps per millisecond=238 ) properties (out of 9) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 17 ms. (steps per millisecond=588 ) properties (out of 9) seen :0
Running SMT prover for 9 properties.
[2023-03-09 03:59:06] [INFO ] Flow matrix only has 500 transitions (discarded 751 similar events)
// Phase 1: matrix 500 rows 87 cols
[2023-03-09 03:59:06] [INFO ] Computed 12 place invariants in 12 ms
[2023-03-09 03:59:07] [INFO ] After 392ms SMT Verify possible using all constraints in real domain returned unsat :0 sat :0 real:9
[2023-03-09 03:59:07] [INFO ] [Nat]Absence check using 12 positive place invariants in 6 ms returned sat
[2023-03-09 03:59:07] [INFO ] After 196ms SMT Verify possible using all constraints in natural domain returned unsat :9 sat :0
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-15 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-12 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-10 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-09 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-08 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-07 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-04 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-03 TRUE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-00 FALSE TECHNIQUES STRUCTURAL_REDUCTION TOPOLOGICAL SAT_SMT
Fused 9 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 2 ms.
All properties solved without resorting to model-checking.
Total runtime 3570 ms.
starting LoLA
BK_INPUT ARMCacheCoherence-PT-none
BK_EXAMINATION: ReachabilityFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution
ReachabilityFireability

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678334407820

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination ReachabilityFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 ARMCacheCoherence-PT-none-ReachabilityFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 22 (type CNST) for 21 ARMCacheCoherence-PT-none-ReachabilityFireability-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 25 (type CNST) for 24 ARMCacheCoherence-PT-none-ReachabilityFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 25 (type CNST) for ARMCacheCoherence-PT-none-ReachabilityFireability-08
lola: result : false
lola: FINISHED task # 22 (type CNST) for ARMCacheCoherence-PT-none-ReachabilityFireability-07
lola: result : false
lola: FINISHED task # 1 (type CNST) for ARMCacheCoherence-PT-none-ReachabilityFireability-00
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 46 (type CNST) for 45 ARMCacheCoherence-PT-none-ReachabilityFireability-15
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 46 (type CNST) for ARMCacheCoherence-PT-none-ReachabilityFireability-15
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 76 (type EXCL) for 30 ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 57 (type FNDP) for 42 ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 58 (type EQUN) for 42 ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type SRCH) for 42 ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 72 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: result : true
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 57 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-14 (obsolete)
lola: CANCELED task # 58 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-14 (obsolete)
lola: LAUNCH task # 93 (type FNDP) for 36 ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type EQUN) for 36 ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type SRCH) for 36 ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 57 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: result : true
lola: fired transitions : 6
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-94.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-58.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

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ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
76 EF EXCL 1/324 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-10 7036 m, 1407 m/sec, 29050 t fired, .
93 EF FNDP 1/238 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 26115 t fired, 29 attempts, .
94 EF STEQ 1/238 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 sara is running.
96 EF SRCH 1/255 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 21931 m, 4386 m/sec, 49297 t fired, .

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ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
76 EF EXCL 6/324 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-10 39787 m, 6550 m/sec, 162386 t fired, .
93 EF FNDP 6/237 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 141977 t fired, 44 attempts, .
94 EF STEQ 6/237 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 sara is running.
96 EF SRCH 6/254 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 128516 m, 21317 m/sec, 312684 t fired, .

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lola: CANCELED task # 96 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-12 (obsolete)
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lola: FINISHED task # 93 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-12
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lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-112.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
76 EF EXCL 11/396 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-10 67808 m, 5604 m/sec, 273095 t fired, .
111 EF FNDP 4/297 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 84457 t fired, 4 attempts, .
112 EF STEQ 4/297 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 sara is running.
114 EF SRCH 4/297 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 74129 m, 14825 m/sec, 155708 t fired, .

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ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
76 EF EXCL 16/396 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-10 97126 m, 5863 m/sec, 391323 t fired, .
111 EF FNDP 9/293 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 176427 t fired, 8 attempts, .
112 EF STEQ 9/293 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 sara is running.
114 EF SRCH 9/293 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 158225 m, 16819 m/sec, 350671 t fired, .

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lola: CANCELED task # 114 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-04 (obsolete)
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lola: result : unknown
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lola: tried executions : 10
lola: time used : 11.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
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sara: try reading problem file /home/mcc/execution/ReachabilityFireability-61.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 EF FNDP 3/323 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-03 74675 t fired, 4 attempts, .
61 EF STEQ 3/323 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-03 sara is running.
76 EF EXCL 21/446 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-10 123938 m, 5362 m/sec, 499668 t fired, .
99 EF SRCH 3/355 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-03 64582 m, 12916 m/sec, 155526 t fired, .

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lola: FINISHED task # 52 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-03
lola: result : unknown
lola: fired transitions : 90980
lola: tried executions : 5
lola: time used : 4.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-67.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 58 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-14
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 4/351 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 73048 t fired, 44 attempts, .
67 EF STEQ 4/390 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 sara is running.
70 EF SRCH 4/390 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 61514 m, 12302 m/sec, 126119 t fired, .
76 EF EXCL 26/510 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-10 151879 m, 5588 m/sec, 612681 t fired, .

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ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 9/346 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 188080 t fired, 137 attempts, .
67 EF STEQ 9/385 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 sara is running.
70 EF SRCH 9/385 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 157734 m, 19244 m/sec, 344415 t fired, .
76 EF EXCL 31/510 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-10 187000 m, 7024 m/sec, 757232 t fired, .

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lola: FINISHED task # 48 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-09
lola: result : unknown
lola: fired transitions : 188481
lola: tried executions : 139
lola: time used : 9.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-122.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 122 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-02
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lola: fired transitions : 19
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lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 107 (type EQUN) for 15 ARMCacheCoherence-PT-none-ReachabilityFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type SRCH) for 15 ARMCacheCoherence-PT-none-ReachabilityFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-78.sara.
sara: place or transition ordering is non-deterministic
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-107.sara.

lola: FINISHED task # 118 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-05
lola: result : true
lola: markings : 902
lola: fired transitions : 1857
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 105 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-05 (obsolete)
lola: CANCELED task # 107 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-05 (obsolete)
lola: LAUNCH task # 49 (type FNDP) for 39 ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 39 ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SRCH) for 39 ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 105 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-05
lola: result : unknown
lola: fired transitions : 2195
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 107 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-05
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-60.sara.
lola: FINISHED task # 78 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-01
lola: result : true
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 60 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-06
lola: result : true
lola: FINISHED task # 81 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: result : true
lola: markings : 787
lola: fired transitions : 1676
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 49 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-13 (obsolete)
lola: CANCELED task # 50 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-13 (obsolete)
lola: LAUNCH task # 53 (type FNDP) for 30 ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type EQUN) for 30 ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SRCH) for 30 ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 49 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: result : unknown
lola: fired transitions : 409
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 50 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-54.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 54 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: result : false
lola: CANCELED task # 53 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-10 (obsolete)
lola: CANCELED task # 75 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-10 (obsolete)
lola: CANCELED task # 76 (type EXCL) for ARMCacheCoherence-PT-none-ReachabilityFireability-10 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG false state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG false findpath
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF false state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF false state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lolaxred"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lolaxred"
echo " Input is ARMCacheCoherence-PT-none, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r007-oct2-167813594900007"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;