Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r007-oct2-167813594900002.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lolaxred
Input is ARMCacheCoherence-PT-none, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r007-oct2-167813594900002
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 6.6K Feb 25 21:34 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 25 21:34 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 21:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 21:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 21:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 163K Feb 25 21:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 25 21:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 21:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:28 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 14M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-00
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-01
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-02
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-03
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-04
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-05
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-06
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-07
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-08
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-09
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-10
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-11
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-12
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-13
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-14
FORMULA_NAME ARMCacheCoherence-PT-none-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678334340248

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lolaxred
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ARMCacheCoherence-PT-none
Applying reductions before tool lola
Invoking reducer
Running Version 202303021504
[2023-03-09 03:59:02] [INFO ] Running its-tools with arguments : [-pnfolder, /home/mcc/execution, -examination, CTLFireability, -timeout, 360, -rebuildPNML]
[2023-03-09 03:59:02] [INFO ] Parsing pnml file : /home/mcc/execution/model.pnml
[2023-03-09 03:59:04] [INFO ] Load time of PNML (sax parser for PT used): 1297 ms
[2023-03-09 03:59:04] [INFO ] Transformed 87 places.
[2023-03-09 03:59:04] [INFO ] Transformed 33676 transitions.
[2023-03-09 03:59:04] [INFO ] Found NUPN structural information;
[2023-03-09 03:59:04] [INFO ] Parsed PT model containing 87 places and 33676 transitions and 246935 arcs in 1556 ms.
Parsed 16 properties from file /home/mcc/execution/CTLFireability.xml in 74 ms.
Ensure Unique test removed 32425 transitions
Reduce redundant transitions removed 32425 transitions.
Support contains 23 out of 87 places. Attempting structural reductions.
Starting structural reductions in LTL mode, iteration 0 : 87/87 places, 1251/1251 transitions.
Discarding 8 places :
Symmetric choice reduction at 0 with 8 rule applications. Total rules 8 place count 79 transition count 1243
Iterating global reduction 0 with 8 rules applied. Total rules applied 16 place count 79 transition count 1243
Drop transitions removed 75 transitions
Redundant transition composition rules discarded 75 transitions
Iterating global reduction 0 with 75 rules applied. Total rules applied 91 place count 79 transition count 1168
Applied a total of 91 rules in 31 ms. Remains 79 /87 variables (removed 8) and now considering 1168/1251 (removed 83) transitions.
[2023-03-09 03:59:04] [INFO ] Flow matrix only has 484 transitions (discarded 684 similar events)
// Phase 1: matrix 484 rows 79 cols
[2023-03-09 03:59:04] [INFO ] Computed 12 place invariants in 16 ms
[2023-03-09 03:59:05] [INFO ] Implicit Places using invariants in 559 ms returned []
[2023-03-09 03:59:05] [INFO ] Flow matrix only has 484 transitions (discarded 684 similar events)
[2023-03-09 03:59:05] [INFO ] Invariant cache hit.
[2023-03-09 03:59:05] [INFO ] State equation strengthened by 173 read => feed constraints.
[2023-03-09 03:59:05] [INFO ] Implicit Places using invariants and state equation in 463 ms returned []
Implicit Place search using SMT with State Equation took 1054 ms to find 0 implicit places.
[2023-03-09 03:59:05] [INFO ] Flow matrix only has 484 transitions (discarded 684 similar events)
[2023-03-09 03:59:05] [INFO ] Invariant cache hit.
[2023-03-09 03:59:06] [INFO ] Dead Transitions using invariants and state equation in 761 ms found 0 transitions.
Starting structural reductions in LTL mode, iteration 1 : 79/87 places, 1168/1251 transitions.
Finished structural reductions in LTL mode , in 1 iterations and 1857 ms. Remains : 79/87 places, 1168/1251 transitions.
Support contains 23 out of 79 places after structural reductions.
[2023-03-09 03:59:06] [INFO ] Flatten gal took : 255 ms
[2023-03-09 03:59:07] [INFO ] Flatten gal took : 123 ms
[2023-03-09 03:59:07] [INFO ] Input system was already deterministic with 1168 transitions.
Incomplete random walk after 10000 steps, including 4 resets, run finished after 508 ms. (steps per millisecond=19 ) properties (out of 75) seen :63
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 12) seen :4
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 13 ms. (steps per millisecond=769 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 8 resets, run finished after 30 ms. (steps per millisecond=333 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 20 ms. (steps per millisecond=500 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 11 ms. (steps per millisecond=909 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 2 resets, run finished after 16 ms. (steps per millisecond=625 ) properties (out of 8) seen :0
Incomplete Best-First random walk after 10001 steps, including 3 resets, run finished after 19 ms. (steps per millisecond=526 ) properties (out of 8) seen :0
Running SMT prover for 8 properties.
[2023-03-09 03:59:08] [INFO ] Flow matrix only has 484 transitions (discarded 684 similar events)
[2023-03-09 03:59:08] [INFO ] Invariant cache hit.
[2023-03-09 03:59:08] [INFO ] [Real]Absence check using 12 positive place invariants in 1 ms returned sat
[2023-03-09 03:59:08] [INFO ] After 90ms SMT Verify possible using all constraints in real domain returned unsat :7 sat :0 real:1
[2023-03-09 03:59:08] [INFO ] [Nat]Absence check using 12 positive place invariants in 4 ms returned sat
[2023-03-09 03:59:08] [INFO ] After 48ms SMT Verify possible using all constraints in natural domain returned unsat :8 sat :0
Fused 8 Parikh solutions to 0 different solutions.
Parikh walk visited 0 properties in 0 ms.
Successfully simplified 8 atomic propositions for a total of 16 simplifications.
FORMULA ARMCacheCoherence-PT-none-CTLFireability-14 FALSE TECHNIQUES TOPOLOGICAL INITIAL_STATE
[2023-03-09 03:59:08] [INFO ] Flatten gal took : 71 ms
[2023-03-09 03:59:08] [INFO ] Flatten gal took : 87 ms
[2023-03-09 03:59:08] [INFO ] Input system was already deterministic with 1168 transitions.
Computed a total of 1 stabilizing places and 1 stable transitions
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 3 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:08] [INFO ] Flatten gal took : 56 ms
[2023-03-09 03:59:08] [INFO ] Flatten gal took : 67 ms
[2023-03-09 03:59:08] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 3 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:08] [INFO ] Flatten gal took : 56 ms
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 58 ms
[2023-03-09 03:59:09] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 3 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 47 ms
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 50 ms
[2023-03-09 03:59:09] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 2 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 60 ms
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 60 ms
[2023-03-09 03:59:09] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Graph (trivial) has 31 edges and 79 vertex of which 2 / 79 are part of one of the 1 SCC in 5 ms
Free SCC test removed 1 places
Ensure Unique test removed 2 transitions
Reduce isomorphic transitions removed 2 transitions.
Performed 11 Post agglomeration using F-continuation condition with reduction of 112 identical transitions.
Deduced a syphon composed of 11 places in 0 ms
Reduce places removed 11 places and 0 transitions.
Iterating global reduction 0 with 22 rules applied. Total rules applied 23 place count 67 transition count 1043
Ensure Unique test removed 225 transitions
Reduce isomorphic transitions removed 225 transitions.
Iterating post reduction 0 with 225 rules applied. Total rules applied 248 place count 67 transition count 818
Drop transitions removed 74 transitions
Redundant transition composition rules discarded 74 transitions
Iterating global reduction 1 with 74 rules applied. Total rules applied 322 place count 67 transition count 744
Applied a total of 322 rules in 119 ms. Remains 67 /79 variables (removed 12) and now considering 744/1168 (removed 424) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 129 ms. Remains : 67/79 places, 744/1168 transitions.
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 22 ms
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 24 ms
[2023-03-09 03:59:09] [INFO ] Input system was already deterministic with 744 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 3 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 43 ms
[2023-03-09 03:59:09] [INFO ] Flatten gal took : 42 ms
[2023-03-09 03:59:10] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Performed 10 Post agglomeration using F-continuation condition with reduction of 84 identical transitions.
Deduced a syphon composed of 10 places in 0 ms
Reduce places removed 10 places and 0 transitions.
Iterating global reduction 0 with 20 rules applied. Total rules applied 20 place count 69 transition count 1074
Ensure Unique test removed 257 transitions
Reduce isomorphic transitions removed 257 transitions.
Iterating post reduction 0 with 257 rules applied. Total rules applied 277 place count 69 transition count 817
Drop transitions removed 20 transitions
Redundant transition composition rules discarded 20 transitions
Iterating global reduction 1 with 20 rules applied. Total rules applied 297 place count 69 transition count 797
Applied a total of 297 rules in 108 ms. Remains 69 /79 variables (removed 10) and now considering 797/1168 (removed 371) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 109 ms. Remains : 69/79 places, 797/1168 transitions.
[2023-03-09 03:59:10] [INFO ] Flatten gal took : 23 ms
[2023-03-09 03:59:10] [INFO ] Flatten gal took : 25 ms
[2023-03-09 03:59:10] [INFO ] Input system was already deterministic with 797 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 3 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 4 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:10] [INFO ] Flatten gal took : 42 ms
[2023-03-09 03:59:10] [INFO ] Flatten gal took : 45 ms
[2023-03-09 03:59:10] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 14 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 15 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:10] [INFO ] Flatten gal took : 44 ms
[2023-03-09 03:59:10] [INFO ] Flatten gal took : 48 ms
[2023-03-09 03:59:10] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 3 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:10] [INFO ] Flatten gal took : 40 ms
[2023-03-09 03:59:10] [INFO ] Flatten gal took : 65 ms
[2023-03-09 03:59:10] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 2 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 46 ms
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 46 ms
[2023-03-09 03:59:11] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in SI_CTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Graph (trivial) has 47 edges and 79 vertex of which 4 / 79 are part of one of the 2 SCC in 1 ms
Free SCC test removed 2 places
Ensure Unique test removed 4 transitions
Reduce isomorphic transitions removed 4 transitions.
Reduce places removed 1 places and 1 transitions.
Performed 15 Post agglomeration using F-continuation condition with reduction of 112 identical transitions.
Deduced a syphon composed of 15 places in 1 ms
Reduce places removed 15 places and 0 transitions.
Iterating global reduction 0 with 30 rules applied. Total rules applied 31 place count 61 transition count 1036
Ensure Unique test removed 353 transitions
Reduce isomorphic transitions removed 353 transitions.
Iterating post reduction 0 with 353 rules applied. Total rules applied 384 place count 61 transition count 683
Drop transitions removed 43 transitions
Redundant transition composition rules discarded 43 transitions
Iterating global reduction 1 with 43 rules applied. Total rules applied 427 place count 61 transition count 640
Applied a total of 427 rules in 110 ms. Remains 61 /79 variables (removed 18) and now considering 640/1168 (removed 528) transitions.
Finished structural reductions in SI_CTL mode , in 1 iterations and 110 ms. Remains : 61/79 places, 640/1168 transitions.
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 20 ms
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 20 ms
[2023-03-09 03:59:11] [INFO ] Input system was already deterministic with 640 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 3 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 3 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 47 ms
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 44 ms
[2023-03-09 03:59:11] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 2 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 44 ms
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 46 ms
[2023-03-09 03:59:11] [INFO ] Input system was already deterministic with 1168 transitions.
Starting structural reductions in LTL mode, iteration 0 : 79/79 places, 1168/1168 transitions.
Applied a total of 0 rules in 2 ms. Remains 79 /79 variables (removed 0) and now considering 1168/1168 (removed 0) transitions.
Finished structural reductions in LTL mode , in 1 iterations and 2 ms. Remains : 79/79 places, 1168/1168 transitions.
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 39 ms
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 42 ms
[2023-03-09 03:59:11] [INFO ] Input system was already deterministic with 1168 transitions.
[2023-03-09 03:59:11] [INFO ] Flatten gal took : 44 ms
[2023-03-09 03:59:12] [INFO ] Flatten gal took : 44 ms
[2023-03-09 03:59:12] [INFO ] Export to MCC of 15 properties in file /home/mcc/execution/CTLFireability.sr.xml took 9 ms.
[2023-03-09 03:59:12] [INFO ] Export to PNML in file /home/mcc/execution/model.sr.pnml of net with 79 places, 1168 transitions and 7577 arcs took 6 ms.
Total runtime 9482 ms.
There are residual formulas that ITS could not solve within timeout
starting LoLA
BK_INPUT ARMCacheCoherence-PT-none
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../reducer/bin//../../lola/bin/
current directory: /home/mcc/execution/379
CTLFireability

FORMULA ARMCacheCoherence-PT-none-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393220 kB
MemFree: 7191952 kB
After kill :
MemTotal: 16393220 kB
MemFree: 16089964 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

+ ulimit -s 65536
+ [[ -z '' ]]
+ export LTSMIN_MEM_SIZE=8589934592
+ LTSMIN_MEM_SIZE=8589934592
+ export PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ PYTHONPATH=/home/mcc/BenchKit/itstools/pylibs
+ export LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
+ LD_LIBRARY_PATH=/home/mcc/BenchKit/itstools/pylibs:
++ sed s/.jar//
++ perl -pe 's/.*\.//g'
++ ls /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/plugins/fr.lip6.move.gal.application.pnmcc_1.0.0.202303021504.jar
+ VERSION=202303021504
+ echo 'Running Version 202303021504'
+ /home/mcc/BenchKit/bin//../reducer/bin//../../itstools//itstools/its-tools -pnfolder /home/mcc/execution -examination CTLFireability -timeout 360 -rebuildPNML
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/379/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/379/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/379/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
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ARMCacheCoherence-PT-none-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
ARMCacheCoherence-PT-none-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
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ARMCacheCoherence-PT-none-CTLFireability-11: AGEF 0 1 0 0 1 0 0 0
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ARMCacheCoherence-PT-none-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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23 CTL EXCL 5/239 3/32 ARMCacheCoherence-PT-none-CTLFireability-06 629792 m, 125958 m/sec, 3634571 t fired, .
51 EF DL FNDP 5/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 95303 t fired, 1 attempts, .

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23 CTL EXCL 10/239 6/32 ARMCacheCoherence-PT-none-CTLFireability-06 1188076 m, 111656 m/sec, 7216256 t fired, .
51 EF DL FNDP 10/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 207428 t fired, 1 attempts, .

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23 CTL EXCL 15/239 8/32 ARMCacheCoherence-PT-none-CTLFireability-06 1722511 m, 106887 m/sec, 10870133 t fired, .
51 EF DL FNDP 15/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 316712 t fired, 1 attempts, .

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23 CTL EXCL 20/239 10/32 ARMCacheCoherence-PT-none-CTLFireability-06 2244403 m, 104378 m/sec, 14703630 t fired, .
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ARMCacheCoherence-PT-none-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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23 CTL EXCL 25/239 12/32 ARMCacheCoherence-PT-none-CTLFireability-06 2730816 m, 97282 m/sec, 18631521 t fired, .
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23 CTL EXCL 30/239 14/32 ARMCacheCoherence-PT-none-CTLFireability-06 3189637 m, 91764 m/sec, 22751208 t fired, .
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23 CTL EXCL 35/239 16/32 ARMCacheCoherence-PT-none-CTLFireability-06 3612879 m, 84648 m/sec, 27057787 t fired, .
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23 CTL EXCL 100/239 25/32 ARMCacheCoherence-PT-none-CTLFireability-06 5750525 m, 104532 m/sec, 82852257 t fired, .
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23 CTL EXCL 105/239 27/32 ARMCacheCoherence-PT-none-CTLFireability-06 6385421 m, 126979 m/sec, 86886113 t fired, .
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23 CTL EXCL 110/239 30/32 ARMCacheCoherence-PT-none-CTLFireability-06 6950848 m, 113085 m/sec, 90753750 t fired, .
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23 CTL EXCL 115/239 32/32 ARMCacheCoherence-PT-none-CTLFireability-06 7487722 m, 107374 m/sec, 94720427 t fired, .
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44 CTL EXCL 5/267 3/32 ARMCacheCoherence-PT-none-CTLFireability-13 534111 m, 106822 m/sec, 2751697 t fired, .
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44 CTL EXCL 10/267 5/32 ARMCacheCoherence-PT-none-CTLFireability-13 1008392 m, 94856 m/sec, 5364703 t fired, .
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44 CTL EXCL 15/267 7/32 ARMCacheCoherence-PT-none-CTLFireability-13 1455262 m, 89374 m/sec, 7905364 t fired, .
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44 CTL EXCL 25/267 10/32 ARMCacheCoherence-PT-none-CTLFireability-13 2304715 m, 83765 m/sec, 12902916 t fired, .
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44 CTL EXCL 35/267 13/32 ARMCacheCoherence-PT-none-CTLFireability-13 3114405 m, 80172 m/sec, 17858320 t fired, .
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44 CTL EXCL 40/267 15/32 ARMCacheCoherence-PT-none-CTLFireability-13 3509104 m, 78939 m/sec, 20336607 t fired, .
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44 CTL EXCL 45/267 17/32 ARMCacheCoherence-PT-none-CTLFireability-13 3899323 m, 78043 m/sec, 22851179 t fired, .
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44 CTL EXCL 50/267 18/32 ARMCacheCoherence-PT-none-CTLFireability-13 4282607 m, 76656 m/sec, 25373473 t fired, .
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44 CTL EXCL 55/267 20/32 ARMCacheCoherence-PT-none-CTLFireability-13 4660376 m, 75553 m/sec, 27922765 t fired, .
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44 CTL EXCL 60/267 21/32 ARMCacheCoherence-PT-none-CTLFireability-13 5029734 m, 73871 m/sec, 30493840 t fired, .
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44 CTL EXCL 65/267 23/32 ARMCacheCoherence-PT-none-CTLFireability-13 5391754 m, 72404 m/sec, 33223886 t fired, .
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44 CTL EXCL 80/267 27/32 ARMCacheCoherence-PT-none-CTLFireability-13 6456427 m, 68775 m/sec, 41732183 t fired, .
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41 CTL EXCL 15/281 9/32 ARMCacheCoherence-PT-none-CTLFireability-12 2072445 m, 124578 m/sec, 10543709 t fired, .
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41 CTL EXCL 20/281 11/32 ARMCacheCoherence-PT-none-CTLFireability-12 2663209 m, 118152 m/sec, 13843701 t fired, .
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41 CTL EXCL 25/281 14/32 ARMCacheCoherence-PT-none-CTLFireability-12 3229831 m, 113324 m/sec, 17251712 t fired, .
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41 CTL EXCL 30/281 16/32 ARMCacheCoherence-PT-none-CTLFireability-12 3786037 m, 111241 m/sec, 20921503 t fired, .
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41 CTL EXCL 35/281 18/32 ARMCacheCoherence-PT-none-CTLFireability-12 4339830 m, 110758 m/sec, 24846150 t fired, .
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41 CTL EXCL 40/281 21/32 ARMCacheCoherence-PT-none-CTLFireability-12 4894074 m, 110848 m/sec, 28946540 t fired, .
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41 CTL EXCL 45/281 22/32 ARMCacheCoherence-PT-none-CTLFireability-12 5339329 m, 89051 m/sec, 33160164 t fired, .
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41 CTL EXCL 50/281 23/32 ARMCacheCoherence-PT-none-CTLFireability-12 5430835 m, 18301 m/sec, 36861565 t fired, .
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41 CTL EXCL 80/281 27/32 ARMCacheCoherence-PT-none-CTLFireability-12 6437064 m, 136761 m/sec, 58687476 t fired, .
51 EF DL FNDP 300/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 6703960 t fired, 7 attempts, .

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41 CTL EXCL 85/281 30/32 ARMCacheCoherence-PT-none-CTLFireability-12 7129033 m, 138393 m/sec, 62213034 t fired, .
51 EF DL FNDP 305/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 6816421 t fired, 7 attempts, .

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41 CTL EXCL 90/281 32/32 ARMCacheCoherence-PT-none-CTLFireability-12 7748169 m, 123827 m/sec, 65480883 t fired, .
51 EF DL FNDP 310/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 6928768 t fired, 7 attempts, .

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51 EF DL FNDP 315/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 7040692 t fired, 8 attempts, .

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32 CTL EXCL 5/298 1/32 ARMCacheCoherence-PT-none-CTLFireability-09 19674 m, 3934 m/sec, 60086 t fired, .
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26 CTL EXCL 0/363 1/32 ARMCacheCoherence-PT-none-CTLFireability-07 49827 m, 9965 m/sec, 271298 t fired, .
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26 CTL EXCL 5/363 3/32 ARMCacheCoherence-PT-none-CTLFireability-07 614429 m, 112920 m/sec, 3763772 t fired, .
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26 CTL EXCL 10/363 5/32 ARMCacheCoherence-PT-none-CTLFireability-07 1126895 m, 102493 m/sec, 7098696 t fired, .
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26 CTL EXCL 15/363 7/32 ARMCacheCoherence-PT-none-CTLFireability-07 1608538 m, 96328 m/sec, 10381787 t fired, .
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26 CTL EXCL 20/363 9/32 ARMCacheCoherence-PT-none-CTLFireability-07 2073972 m, 93086 m/sec, 13624615 t fired, .
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26 CTL EXCL 30/363 13/32 ARMCacheCoherence-PT-none-CTLFireability-07 2952942 m, 85985 m/sec, 20035510 t fired, .
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26 CTL EXCL 40/363 16/32 ARMCacheCoherence-PT-none-CTLFireability-07 3794928 m, 82987 m/sec, 26474259 t fired, .
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26 CTL EXCL 45/363 18/32 ARMCacheCoherence-PT-none-CTLFireability-07 4199878 m, 80990 m/sec, 29679882 t fired, .
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26 CTL EXCL 50/363 20/32 ARMCacheCoherence-PT-none-CTLFireability-07 4592660 m, 78556 m/sec, 32874879 t fired, .
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20 CTL EXCL 10/397 5/32 ARMCacheCoherence-PT-none-CTLFireability-05 1082238 m, 101907 m/sec, 4695908 t fired, .
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20 CTL EXCL 15/397 7/32 ARMCacheCoherence-PT-none-CTLFireability-05 1559698 m, 95492 m/sec, 6943850 t fired, .
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20 CTL EXCL 75/397 27/32 ARMCacheCoherence-PT-none-CTLFireability-05 6436554 m, 71991 m/sec, 35138508 t fired, .
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20 CTL EXCL 80/397 29/32 ARMCacheCoherence-PT-none-CTLFireability-05 6799868 m, 72662 m/sec, 37839613 t fired, .
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20 CTL EXCL 85/397 30/32 ARMCacheCoherence-PT-none-CTLFireability-05 7168893 m, 73805 m/sec, 40591939 t fired, .
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20 CTL EXCL 90/397 32/32 ARMCacheCoherence-PT-none-CTLFireability-05 7538229 m, 73867 m/sec, 43363980 t fired, .
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12 CTL EXCL 5/440 3/32 ARMCacheCoherence-PT-none-CTLFireability-03 481869 m, 96373 m/sec, 2949433 t fired, .
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12 CTL EXCL 10/440 4/32 ARMCacheCoherence-PT-none-CTLFireability-03 920326 m, 87691 m/sec, 5794677 t fired, .
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12 CTL EXCL 50/440 17/32 ARMCacheCoherence-PT-none-CTLFireability-03 3945472 m, 70768 m/sec, 27101089 t fired, .
51 EF DL FNDP 565/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 12664203 t fired, 13 attempts, .

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12 CTL EXCL 55/440 18/32 ARMCacheCoherence-PT-none-CTLFireability-03 4295976 m, 70100 m/sec, 29763759 t fired, .
51 EF DL FNDP 570/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 12777052 t fired, 13 attempts, .

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12 CTL EXCL 60/440 20/32 ARMCacheCoherence-PT-none-CTLFireability-03 4644994 m, 69803 m/sec, 32467048 t fired, .
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12 CTL EXCL 65/440 21/32 ARMCacheCoherence-PT-none-CTLFireability-03 4989584 m, 68918 m/sec, 35198913 t fired, .
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12 CTL EXCL 70/440 23/32 ARMCacheCoherence-PT-none-CTLFireability-03 5327306 m, 67544 m/sec, 38036753 t fired, .
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12 CTL EXCL 75/440 24/32 ARMCacheCoherence-PT-none-CTLFireability-03 5658134 m, 66165 m/sec, 41010247 t fired, .
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12 CTL EXCL 80/440 25/32 ARMCacheCoherence-PT-none-CTLFireability-03 5994866 m, 67346 m/sec, 43810657 t fired, .
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12 CTL EXCL 85/440 27/32 ARMCacheCoherence-PT-none-CTLFireability-03 6317395 m, 64505 m/sec, 46756953 t fired, .
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12 CTL EXCL 90/440 28/32 ARMCacheCoherence-PT-none-CTLFireability-03 6637248 m, 63970 m/sec, 49867012 t fired, .
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12 CTL EXCL 95/440 29/32 ARMCacheCoherence-PT-none-CTLFireability-03 6963845 m, 65319 m/sec, 52985625 t fired, .
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1 CTL EXCL 4/594 1/32 ARMCacheCoherence-PT-none-CTLFireability-00 131914 m, 26382 m/sec, 1060986 t fired, .
51 EF DL FNDP 630/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 14108685 t fired, 15 attempts, .

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1 CTL EXCL 9/594 2/32 ARMCacheCoherence-PT-none-CTLFireability-00 270826 m, 27782 m/sec, 2136059 t fired, .
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1 CTL EXCL 14/594 2/32 ARMCacheCoherence-PT-none-CTLFireability-00 406359 m, 27106 m/sec, 3202370 t fired, .
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1 CTL EXCL 19/594 3/32 ARMCacheCoherence-PT-none-CTLFireability-00 539511 m, 26630 m/sec, 4258028 t fired, .
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1 CTL EXCL 34/594 4/32 ARMCacheCoherence-PT-none-CTLFireability-00 935662 m, 26344 m/sec, 7440807 t fired, .
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1 CTL EXCL 69/594 8/32 ARMCacheCoherence-PT-none-CTLFireability-00 1823378 m, 25024 m/sec, 14761210 t fired, .
51 EF DL FNDP 695/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 15553709 t fired, 16 attempts, .

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1 CTL EXCL 74/594 9/32 ARMCacheCoherence-PT-none-CTLFireability-00 1946820 m, 24688 m/sec, 15802457 t fired, .
51 EF DL FNDP 700/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 15664918 t fired, 16 attempts, .

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1 CTL EXCL 79/594 9/32 ARMCacheCoherence-PT-none-CTLFireability-00 2071546 m, 24945 m/sec, 16849662 t fired, .
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1 CTL EXCL 84/594 10/32 ARMCacheCoherence-PT-none-CTLFireability-00 2195132 m, 24717 m/sec, 17897774 t fired, .
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ARMCacheCoherence-PT-none-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 140/594 15/32 ARMCacheCoherence-PT-none-CTLFireability-00 3534863 m, 24362 m/sec, 29485657 t fired, .
51 EF DL FNDP 766/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 17123515 t fired, 18 attempts, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 145/594 16/32 ARMCacheCoherence-PT-none-CTLFireability-00 3655406 m, 24108 m/sec, 30553037 t fired, .
51 EF DL FNDP 771/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 17236393 t fired, 18 attempts, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 150/594 16/32 ARMCacheCoherence-PT-none-CTLFireability-00 3774554 m, 23829 m/sec, 31623297 t fired, .
51 EF DL FNDP 776/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 17348971 t fired, 18 attempts, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 155/594 17/32 ARMCacheCoherence-PT-none-CTLFireability-00 3894230 m, 23935 m/sec, 32698290 t fired, .
51 EF DL FNDP 781/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 17461402 t fired, 18 attempts, .

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 160/594 17/32 ARMCacheCoherence-PT-none-CTLFireability-00 4014269 m, 24007 m/sec, 33773523 t fired, .
51 EF DL FNDP 786/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 17572406 t fired, 18 attempts, .

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1 CTL EXCL 165/594 18/32 ARMCacheCoherence-PT-none-CTLFireability-00 4133857 m, 23917 m/sec, 34858270 t fired, .
51 EF DL FNDP 791/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 17683164 t fired, 18 attempts, .

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1 CTL EXCL 170/594 18/32 ARMCacheCoherence-PT-none-CTLFireability-00 4252534 m, 23735 m/sec, 35937297 t fired, .
51 EF DL FNDP 796/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 17794643 t fired, 18 attempts, .

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1 CTL EXCL 175/594 19/32 ARMCacheCoherence-PT-none-CTLFireability-00 4373004 m, 24094 m/sec, 37040226 t fired, .
51 EF DL FNDP 801/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 17906416 t fired, 18 attempts, .

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1 CTL EXCL 180/594 19/32 ARMCacheCoherence-PT-none-CTLFireability-00 4492633 m, 23925 m/sec, 38139427 t fired, .
51 EF DL FNDP 806/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 18017976 t fired, 19 attempts, .

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1 CTL EXCL 185/594 20/32 ARMCacheCoherence-PT-none-CTLFireability-00 4612659 m, 24005 m/sec, 39249513 t fired, .
51 EF DL FNDP 811/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 18129680 t fired, 19 attempts, .

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1 CTL EXCL 190/594 20/32 ARMCacheCoherence-PT-none-CTLFireability-00 4732693 m, 24006 m/sec, 40360075 t fired, .
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1 CTL EXCL 195/594 21/32 ARMCacheCoherence-PT-none-CTLFireability-00 4851738 m, 23809 m/sec, 41479323 t fired, .
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1 CTL EXCL 200/594 21/32 ARMCacheCoherence-PT-none-CTLFireability-00 4972826 m, 24217 m/sec, 42614101 t fired, .
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1 CTL EXCL 205/594 22/32 ARMCacheCoherence-PT-none-CTLFireability-00 5094093 m, 24253 m/sec, 43775482 t fired, .
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1 CTL EXCL 210/594 22/32 ARMCacheCoherence-PT-none-CTLFireability-00 5213893 m, 23960 m/sec, 44947635 t fired, .
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1 CTL EXCL 215/594 23/32 ARMCacheCoherence-PT-none-CTLFireability-00 5335165 m, 24254 m/sec, 46172733 t fired, .
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1 CTL EXCL 275/594 29/32 ARMCacheCoherence-PT-none-CTLFireability-00 6807622 m, 24233 m/sec, 61656399 t fired, .
51 EF DL FNDP 901/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 20128784 t fired, 21 attempts, .

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1 CTL EXCL 280/594 29/32 ARMCacheCoherence-PT-none-CTLFireability-00 6934844 m, 25444 m/sec, 63034739 t fired, .
51 EF DL FNDP 906/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 20239409 t fired, 21 attempts, .

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1 CTL EXCL 285/594 30/32 ARMCacheCoherence-PT-none-CTLFireability-00 7062388 m, 25508 m/sec, 64401874 t fired, .
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1 CTL EXCL 290/594 30/32 ARMCacheCoherence-PT-none-CTLFireability-00 7190214 m, 25565 m/sec, 65789435 t fired, .
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1 CTL EXCL 295/594 31/32 ARMCacheCoherence-PT-none-CTLFireability-00 7318368 m, 25630 m/sec, 67194237 t fired, .
51 EF DL FNDP 921/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 20571911 t fired, 21 attempts, .

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1 CTL EXCL 300/594 31/32 ARMCacheCoherence-PT-none-CTLFireability-00 7446195 m, 25565 m/sec, 68572069 t fired, .
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1 CTL EXCL 305/594 32/32 ARMCacheCoherence-PT-none-CTLFireability-00 7573826 m, 25526 m/sec, 70018454 t fired, .
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1 CTL EXCL 310/594 32/32 ARMCacheCoherence-PT-none-CTLFireability-00 7701260 m, 25486 m/sec, 71417050 t fired, .
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50 EF DL EXCL 5/664 1/32 ARMCacheCoherence-PT-none-CTLFireability-02 71630 m, 14326 m/sec, 266943 t fired, .
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50 EF DL EXCL 10/664 1/32 ARMCacheCoherence-PT-none-CTLFireability-02 145559 m, 14785 m/sec, 574046 t fired, .
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50 EF DL EXCL 95/664 5/32 ARMCacheCoherence-PT-none-CTLFireability-02 1347806 m, 12290 m/sec, 10880234 t fired, .
51 EF DL FNDP 1036/3599 0/5 ARMCacheCoherence-PT-none-CTLFireability-02 23136676 t fired, 24 attempts, .

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50 EF DL EXCL 100/664 5/32 ARMCacheCoherence-PT-none-CTLFireability-02 1407607 m, 11960 m/sec, 11456152 t fired, .
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50 EF DL EXCL 430/664 20/32 ARMCacheCoherence-PT-none-CTLFireability-02 5595488 m, 12511 m/sec, 46642327 t fired, .
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50 EF DL EXCL 566/664 25/32 ARMCacheCoherence-PT-none-CTLFireability-02 7334981 m, 11275 m/sec, 84996702 t fired, .
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