fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r006-oct2-167813594800762
Last Updated
May 14, 2023

About the Execution of LoLA for BART-PT-005

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
11281.483 728205.00 722917.00 167.70 FFT????TTF??TF?? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813594800762.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is BART-PT-005, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813594800762
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 190K Feb 26 04:07 CTLCardinality.txt
-rw-r--r-- 1 mcc users 721K Feb 26 04:07 CTLCardinality.xml
-rw-r--r-- 1 mcc users 287K Feb 26 03:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 988K Feb 26 03:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 216K Feb 25 15:34 LTLCardinality.txt
-rw-r--r-- 1 mcc users 566K Feb 25 15:34 LTLCardinality.xml
-rw-r--r-- 1 mcc users 97K Feb 25 15:34 LTLFireability.txt
-rw-r--r-- 1 mcc users 268K Feb 25 15:34 LTLFireability.xml
-rw-r--r-- 1 mcc users 1.2M Feb 26 04:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 4.2M Feb 26 04:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 1023K Feb 26 04:18 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 3.4M Feb 26 04:18 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 44K Feb 25 15:34 UpperBounds.txt
-rw-r--r-- 1 mcc users 88K Feb 25 15:34 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 4 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 1.3M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME BART-PT-005-CTLFireability-00
FORMULA_NAME BART-PT-005-CTLFireability-01
FORMULA_NAME BART-PT-005-CTLFireability-02
FORMULA_NAME BART-PT-005-CTLFireability-03
FORMULA_NAME BART-PT-005-CTLFireability-04
FORMULA_NAME BART-PT-005-CTLFireability-05
FORMULA_NAME BART-PT-005-CTLFireability-06
FORMULA_NAME BART-PT-005-CTLFireability-07
FORMULA_NAME BART-PT-005-CTLFireability-08
FORMULA_NAME BART-PT-005-CTLFireability-09
FORMULA_NAME BART-PT-005-CTLFireability-10
FORMULA_NAME BART-PT-005-CTLFireability-11
FORMULA_NAME BART-PT-005-CTLFireability-12
FORMULA_NAME BART-PT-005-CTLFireability-13
FORMULA_NAME BART-PT-005-CTLFireability-14
FORMULA_NAME BART-PT-005-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1678314527604

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=CTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=BART-PT-005
Not applying reductions.
Model is PT
CTLFireability PT
starting LoLA
BK_INPUT BART-PT-005
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
CTLFireability

FORMULA BART-PT-005-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-PT-005-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-PT-005-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-PT-005-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-PT-005-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-PT-005-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-PT-005-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA BART-PT-005-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678315255809

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 45 (type EXCL) for 44 BART-PT-005-CTLFireability-12
lola: time limit : 146 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 45 (type EXCL) for BART-PT-005-CTLFireability-12
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 36 (type EXCL) for 35 BART-PT-005-CTLFireability-09
lola: time limit : 195 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 36 (type EXCL) for BART-PT-005-CTLFireability-09
lola: result : false
lola: markings : 24
lola: fired transitions : 24
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 BART-PT-005-CTLFireability-13
lola: time limit : 206 sec
lola: memory limit: 32 pages
lola: FINISHED task # 48 (type EXCL) for BART-PT-005-CTLFireability-13
lola: result : false
lola: markings : 25
lola: fired transitions : 135
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 54 (type EXCL) for 53 BART-PT-005-CTLFireability-15
lola: time limit : 219 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 4/234 5/32 BART-PT-005-CTLFireability-15 770067 m, 154013 m/sec, 1242710 t fired, .

Time elapsed: 87 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 9/234 10/32 BART-PT-005-CTLFireability-15 1708886 m, 187763 m/sec, 2855431 t fired, .

Time elapsed: 92 secs. Pages in use: 10
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 14/234 14/32 BART-PT-005-CTLFireability-15 2571940 m, 172610 m/sec, 4378343 t fired, .

Time elapsed: 97 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 19/234 19/32 BART-PT-005-CTLFireability-15 3391259 m, 163863 m/sec, 5842905 t fired, .

Time elapsed: 102 secs. Pages in use: 19
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 24/234 23/32 BART-PT-005-CTLFireability-15 4189518 m, 159651 m/sec, 7277930 t fired, .

Time elapsed: 107 secs. Pages in use: 23
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 29/234 28/32 BART-PT-005-CTLFireability-15 4993103 m, 160717 m/sec, 8697634 t fired, .

Time elapsed: 112 secs. Pages in use: 28
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
54 CTL EXCL 34/234 32/32 BART-PT-005-CTLFireability-15 5780863 m, 157552 m/sec, 10102063 t fired, .

Time elapsed: 117 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 54 (type EXCL) for BART-PT-005-CTLFireability-15 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 122 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 51 (type EXCL) for 50 BART-PT-005-CTLFireability-14
lola: time limit : 248 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 5/248 3/32 BART-PT-005-CTLFireability-14 479322 m, 95864 m/sec, 1929743 t fired, .

Time elapsed: 127 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 10/248 5/32 BART-PT-005-CTLFireability-14 909837 m, 86103 m/sec, 3757359 t fired, .

Time elapsed: 132 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 15/248 8/32 BART-PT-005-CTLFireability-14 1319210 m, 81874 m/sec, 5527062 t fired, .

Time elapsed: 137 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 20/248 10/32 BART-PT-005-CTLFireability-14 1707234 m, 77604 m/sec, 7233720 t fired, .

Time elapsed: 142 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 25/248 12/32 BART-PT-005-CTLFireability-14 2088375 m, 76228 m/sec, 8905771 t fired, .

Time elapsed: 147 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 30/248 14/32 BART-PT-005-CTLFireability-14 2455618 m, 73448 m/sec, 10538547 t fired, .

Time elapsed: 152 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 35/248 16/32 BART-PT-005-CTLFireability-14 2817561 m, 72388 m/sec, 12143529 t fired, .

Time elapsed: 157 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 40/248 18/32 BART-PT-005-CTLFireability-14 3172179 m, 70923 m/sec, 13733233 t fired, .

Time elapsed: 162 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 45/248 19/32 BART-PT-005-CTLFireability-14 3519997 m, 69563 m/sec, 15303469 t fired, .

Time elapsed: 167 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 50/248 21/32 BART-PT-005-CTLFireability-14 3862599 m, 68520 m/sec, 16854716 t fired, .

Time elapsed: 172 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 55/248 23/32 BART-PT-005-CTLFireability-14 4202206 m, 67921 m/sec, 18396295 t fired, .

Time elapsed: 177 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 60/248 25/32 BART-PT-005-CTLFireability-14 4540310 m, 67620 m/sec, 19928260 t fired, .

Time elapsed: 182 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 65/248 27/32 BART-PT-005-CTLFireability-14 4872025 m, 66343 m/sec, 21441889 t fired, .

Time elapsed: 187 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 70/248 28/32 BART-PT-005-CTLFireability-14 5199767 m, 65548 m/sec, 22951555 t fired, .

Time elapsed: 192 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 75/248 30/32 BART-PT-005-CTLFireability-14 5527630 m, 65572 m/sec, 24454415 t fired, .

Time elapsed: 197 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
51 CTL EXCL 80/248 32/32 BART-PT-005-CTLFireability-14 5851260 m, 64726 m/sec, 25939465 t fired, .

Time elapsed: 202 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 51 (type EXCL) for BART-PT-005-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 207 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 39 (type EXCL) for 38 BART-PT-005-CTLFireability-10
lola: time limit : 261 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/261 5/32 BART-PT-005-CTLFireability-10 896567 m, 179313 m/sec, 1914638 t fired, .

Time elapsed: 212 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/261 9/32 BART-PT-005-CTLFireability-10 1620448 m, 144776 m/sec, 3627198 t fired, .

Time elapsed: 217 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/261 12/32 BART-PT-005-CTLFireability-10 2266846 m, 129279 m/sec, 5196906 t fired, .

Time elapsed: 222 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 20/261 16/32 BART-PT-005-CTLFireability-10 2880400 m, 122710 m/sec, 6705186 t fired, .

Time elapsed: 227 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 25/261 19/32 BART-PT-005-CTLFireability-10 3464698 m, 116859 m/sec, 8178842 t fired, .

Time elapsed: 232 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 30/261 21/32 BART-PT-005-CTLFireability-10 4006169 m, 108294 m/sec, 9563157 t fired, .

Time elapsed: 237 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 35/261 24/32 BART-PT-005-CTLFireability-10 4427366 m, 84239 m/sec, 10631373 t fired, .

Time elapsed: 242 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 40/261 26/32 BART-PT-005-CTLFireability-10 4837905 m, 82107 m/sec, 11690310 t fired, .

Time elapsed: 247 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 45/261 28/32 BART-PT-005-CTLFireability-10 5339536 m, 100326 m/sec, 13001145 t fired, .

Time elapsed: 252 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 50/261 31/32 BART-PT-005-CTLFireability-10 5864386 m, 104970 m/sec, 14369110 t fired, .

Time elapsed: 257 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 39 (type EXCL) for BART-PT-005-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 262 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 33 (type EXCL) for 32 BART-PT-005-CTLFireability-08
lola: time limit : 278 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for BART-PT-005-CTLFireability-08
lola: result : true
lola: markings : 18
lola: fired transitions : 36
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 BART-PT-005-CTLFireability-07
lola: time limit : 303 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for BART-PT-005-CTLFireability-07
lola: result : true
lola: markings : 498701
lola: fired transitions : 1659209
lola: time used : 3.000000
lola: memory pages used : 3
lola: LAUNCH task # 24 (type EXCL) for 23 BART-PT-005-CTLFireability-05
lola: time limit : 333 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 2/333 2/32 BART-PT-005-CTLFireability-05 239339 m, 47867 m/sec, 715908 t fired, .

Time elapsed: 267 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 7/333 6/32 BART-PT-005-CTLFireability-05 913608 m, 134853 m/sec, 2986546 t fired, .

Time elapsed: 272 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 12/333 10/32 BART-PT-005-CTLFireability-05 1525570 m, 122392 m/sec, 5053393 t fired, .

Time elapsed: 277 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 17/333 14/32 BART-PT-005-CTLFireability-05 2224668 m, 139819 m/sec, 7018306 t fired, .

Time elapsed: 282 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 22/333 19/32 BART-PT-005-CTLFireability-05 2992896 m, 153645 m/sec, 9036336 t fired, .

Time elapsed: 287 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 27/333 22/32 BART-PT-005-CTLFireability-05 3397537 m, 80928 m/sec, 10862157 t fired, .

Time elapsed: 292 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 32/333 25/32 BART-PT-005-CTLFireability-05 3865044 m, 93501 m/sec, 12801690 t fired, .

Time elapsed: 297 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 37/333 28/32 BART-PT-005-CTLFireability-05 4319758 m, 90942 m/sec, 14683958 t fired, .

Time elapsed: 302 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 42/333 31/32 BART-PT-005-CTLFireability-05 4767727 m, 89593 m/sec, 16492784 t fired, .

Time elapsed: 307 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 24 (type EXCL) for BART-PT-005-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 312 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 21 (type EXCL) for 20 BART-PT-005-CTLFireability-04
lola: time limit : 365 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 5/365 2/32 BART-PT-005-CTLFireability-04 219097 m, 43819 m/sec, 1091911 t fired, .

Time elapsed: 317 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 10/365 3/32 BART-PT-005-CTLFireability-04 432345 m, 42649 m/sec, 2231079 t fired, .

Time elapsed: 322 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 15/365 4/32 BART-PT-005-CTLFireability-04 637229 m, 40976 m/sec, 3358674 t fired, .

Time elapsed: 327 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 20/365 5/32 BART-PT-005-CTLFireability-04 836125 m, 39779 m/sec, 4467210 t fired, .

Time elapsed: 332 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 25/365 6/32 BART-PT-005-CTLFireability-04 1032465 m, 39268 m/sec, 5573078 t fired, .

Time elapsed: 337 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 30/365 7/32 BART-PT-005-CTLFireability-04 1226177 m, 38742 m/sec, 6684543 t fired, .

Time elapsed: 342 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 35/365 9/32 BART-PT-005-CTLFireability-04 1415045 m, 37773 m/sec, 7770560 t fired, .

Time elapsed: 347 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 40/365 10/32 BART-PT-005-CTLFireability-04 1603478 m, 37686 m/sec, 8850939 t fired, .

Time elapsed: 352 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 45/365 11/32 BART-PT-005-CTLFireability-04 1791511 m, 37606 m/sec, 9937448 t fired, .

Time elapsed: 357 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 50/365 12/32 BART-PT-005-CTLFireability-04 1976431 m, 36984 m/sec, 11011761 t fired, .

Time elapsed: 362 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 55/365 13/32 BART-PT-005-CTLFireability-04 2158951 m, 36504 m/sec, 12076317 t fired, .

Time elapsed: 367 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 60/365 14/32 BART-PT-005-CTLFireability-04 2337424 m, 35694 m/sec, 13131259 t fired, .

Time elapsed: 372 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 65/365 15/32 BART-PT-005-CTLFireability-04 2517841 m, 36083 m/sec, 14186001 t fired, .

Time elapsed: 377 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 70/365 16/32 BART-PT-005-CTLFireability-04 2696348 m, 35701 m/sec, 15239173 t fired, .

Time elapsed: 382 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 75/365 17/32 BART-PT-005-CTLFireability-04 2874026 m, 35535 m/sec, 16291438 t fired, .

Time elapsed: 387 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 80/365 18/32 BART-PT-005-CTLFireability-04 3049147 m, 35024 m/sec, 17337572 t fired, .

Time elapsed: 392 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 85/365 19/32 BART-PT-005-CTLFireability-04 3225706 m, 35311 m/sec, 18383284 t fired, .

Time elapsed: 397 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 90/365 20/32 BART-PT-005-CTLFireability-04 3401067 m, 35072 m/sec, 19429878 t fired, .

Time elapsed: 402 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 95/365 21/32 BART-PT-005-CTLFireability-04 3575720 m, 34930 m/sec, 20477881 t fired, .

Time elapsed: 407 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 100/365 22/32 BART-PT-005-CTLFireability-04 3752864 m, 35428 m/sec, 21517657 t fired, .

Time elapsed: 412 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 105/365 23/32 BART-PT-005-CTLFireability-04 3924232 m, 34273 m/sec, 22557166 t fired, .

Time elapsed: 417 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 110/365 24/32 BART-PT-005-CTLFireability-04 4096862 m, 34526 m/sec, 23591636 t fired, .

Time elapsed: 422 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 115/365 25/32 BART-PT-005-CTLFireability-04 4269867 m, 34601 m/sec, 24612561 t fired, .

Time elapsed: 427 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 120/365 26/32 BART-PT-005-CTLFireability-04 4443645 m, 34755 m/sec, 25655484 t fired, .

Time elapsed: 432 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 125/365 27/32 BART-PT-005-CTLFireability-04 4613808 m, 34032 m/sec, 26689021 t fired, .

Time elapsed: 437 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 130/365 28/32 BART-PT-005-CTLFireability-04 4783016 m, 33841 m/sec, 27718727 t fired, .

Time elapsed: 442 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 135/365 29/32 BART-PT-005-CTLFireability-04 4951180 m, 33632 m/sec, 28744433 t fired, .

Time elapsed: 447 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 140/365 30/32 BART-PT-005-CTLFireability-04 5116034 m, 32970 m/sec, 29757140 t fired, .

Time elapsed: 452 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 145/365 31/32 BART-PT-005-CTLFireability-04 5284513 m, 33695 m/sec, 30783373 t fired, .

Time elapsed: 457 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 150/365 31/32 BART-PT-005-CTLFireability-04 5452150 m, 33527 m/sec, 31809163 t fired, .

Time elapsed: 462 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 155/365 32/32 BART-PT-005-CTLFireability-04 5619169 m, 33403 m/sec, 32834745 t fired, .

Time elapsed: 467 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 21 (type EXCL) for BART-PT-005-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 472 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 18 (type EXCL) for 17 BART-PT-005-CTLFireability-03
lola: time limit : 391 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 5/391 3/32 BART-PT-005-CTLFireability-03 505370 m, 101074 m/sec, 1778063 t fired, .

Time elapsed: 477 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 10/391 6/32 BART-PT-005-CTLFireability-03 943737 m, 87673 m/sec, 3505243 t fired, .

Time elapsed: 482 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 15/391 8/32 BART-PT-005-CTLFireability-03 1378136 m, 86879 m/sec, 5229603 t fired, .

Time elapsed: 487 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 20/391 11/32 BART-PT-005-CTLFireability-03 1792996 m, 82972 m/sec, 6896286 t fired, .

Time elapsed: 492 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 25/391 13/32 BART-PT-005-CTLFireability-03 2193351 m, 80071 m/sec, 8541945 t fired, .

Time elapsed: 497 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 30/391 15/32 BART-PT-005-CTLFireability-03 2560711 m, 73472 m/sec, 10081723 t fired, .

Time elapsed: 502 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 35/391 17/32 BART-PT-005-CTLFireability-03 2879540 m, 63765 m/sec, 11427729 t fired, .

Time elapsed: 507 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 40/391 19/32 BART-PT-005-CTLFireability-03 3254640 m, 75020 m/sec, 13006000 t fired, .

Time elapsed: 512 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 46/391 21/32 BART-PT-005-CTLFireability-03 3628223 m, 74716 m/sec, 14597599 t fired, .

Time elapsed: 518 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 51/391 24/32 BART-PT-005-CTLFireability-03 4006012 m, 75557 m/sec, 16172871 t fired, .

Time elapsed: 523 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 56/391 26/32 BART-PT-005-CTLFireability-03 4371669 m, 73131 m/sec, 17731755 t fired, .

Time elapsed: 528 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 61/391 28/32 BART-PT-005-CTLFireability-03 4739746 m, 73615 m/sec, 19277217 t fired, .

Time elapsed: 533 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 66/391 30/32 BART-PT-005-CTLFireability-03 5116798 m, 75410 m/sec, 20849851 t fired, .

Time elapsed: 538 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 71/391 32/32 BART-PT-005-CTLFireability-03 5473282 m, 71296 m/sec, 22386567 t fired, .

Time elapsed: 543 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 18 (type EXCL) for BART-PT-005-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-02: DISJ 0 3 0 0 3 0 0 0
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 548 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 15 (type EXCL) for 6 BART-PT-005-CTLFireability-02
lola: time limit : 436 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for BART-PT-005-CTLFireability-02
lola: result : true
lola: markings : 8811
lola: fired transitions : 9068
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 BART-PT-005-CTLFireability-01
lola: time limit : 763 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for BART-PT-005-CTLFireability-01
lola: result : false
lola: markings : 65
lola: fired transitions : 72
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 BART-PT-005-CTLFireability-00
lola: time limit : 1017 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for BART-PT-005-CTLFireability-00
lola: result : false
lola: markings : 8376
lola: fired transitions : 12438
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 BART-PT-005-CTLFireability-11
lola: time limit : 1526 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/1526 4/32 BART-PT-005-CTLFireability-11 602729 m, 120545 m/sec, 1943598 t fired, .

Time elapsed: 553 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 10/1526 7/32 BART-PT-005-CTLFireability-11 1124815 m, 104417 m/sec, 3772863 t fired, .

Time elapsed: 558 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 15/1526 9/32 BART-PT-005-CTLFireability-11 1629013 m, 100839 m/sec, 5556125 t fired, .

Time elapsed: 563 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 20/1526 12/32 BART-PT-005-CTLFireability-11 2105743 m, 95346 m/sec, 7286750 t fired, .

Time elapsed: 568 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 25/1526 14/32 BART-PT-005-CTLFireability-11 2576905 m, 94232 m/sec, 8996151 t fired, .

Time elapsed: 573 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 30/1526 17/32 BART-PT-005-CTLFireability-11 3023078 m, 89234 m/sec, 10655758 t fired, .

Time elapsed: 578 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 35/1526 19/32 BART-PT-005-CTLFireability-11 3458987 m, 87181 m/sec, 12289600 t fired, .

Time elapsed: 583 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 40/1526 21/32 BART-PT-005-CTLFireability-11 3884532 m, 85109 m/sec, 13893480 t fired, .

Time elapsed: 588 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 45/1526 23/32 BART-PT-005-CTLFireability-11 4309431 m, 84979 m/sec, 15488205 t fired, .

Time elapsed: 593 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 50/1526 26/32 BART-PT-005-CTLFireability-11 4725747 m, 83263 m/sec, 17065903 t fired, .

Time elapsed: 598 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 55/1526 28/32 BART-PT-005-CTLFireability-11 5140548 m, 82960 m/sec, 18641394 t fired, .

Time elapsed: 603 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 60/1526 30/32 BART-PT-005-CTLFireability-11 5539013 m, 79693 m/sec, 20182043 t fired, .

Time elapsed: 608 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 65/1526 32/32 BART-PT-005-CTLFireability-11 5921501 m, 76497 m/sec, 21644323 t fired, .

Time elapsed: 613 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 42 (type EXCL) for BART-PT-005-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 618 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 27 (type EXCL) for 26 BART-PT-005-CTLFireability-06
lola: time limit : 2982 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 5/2982 2/32 BART-PT-005-CTLFireability-06 324662 m, 64932 m/sec, 1584462 t fired, .

Time elapsed: 623 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 10/2982 4/32 BART-PT-005-CTLFireability-06 623806 m, 59828 m/sec, 3149767 t fired, .

Time elapsed: 628 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 15/2982 6/32 BART-PT-005-CTLFireability-06 912029 m, 57644 m/sec, 4688031 t fired, .

Time elapsed: 633 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 20/2982 7/32 BART-PT-005-CTLFireability-06 1194620 m, 56518 m/sec, 6221725 t fired, .

Time elapsed: 638 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 25/2982 9/32 BART-PT-005-CTLFireability-06 1473167 m, 55709 m/sec, 7740567 t fired, .

Time elapsed: 643 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 30/2982 11/32 BART-PT-005-CTLFireability-06 1744288 m, 54224 m/sec, 9233286 t fired, .

Time elapsed: 648 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 35/2982 12/32 BART-PT-005-CTLFireability-06 2012254 m, 53593 m/sec, 10721748 t fired, .

Time elapsed: 653 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 40/2982 14/32 BART-PT-005-CTLFireability-06 2275080 m, 52565 m/sec, 12193723 t fired, .

Time elapsed: 658 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 45/2982 15/32 BART-PT-005-CTLFireability-06 2536054 m, 52194 m/sec, 13655222 t fired, .

Time elapsed: 663 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 50/2982 17/32 BART-PT-005-CTLFireability-06 2792546 m, 51298 m/sec, 15101513 t fired, .

Time elapsed: 668 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 55/2982 18/32 BART-PT-005-CTLFireability-06 3046637 m, 50818 m/sec, 16547184 t fired, .

Time elapsed: 673 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 60/2982 19/32 BART-PT-005-CTLFireability-06 3299410 m, 50554 m/sec, 17980102 t fired, .

Time elapsed: 678 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 65/2982 21/32 BART-PT-005-CTLFireability-06 3550184 m, 50154 m/sec, 19410898 t fired, .

Time elapsed: 683 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 70/2982 22/32 BART-PT-005-CTLFireability-06 3800947 m, 50152 m/sec, 20830189 t fired, .

Time elapsed: 688 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 75/2982 24/32 BART-PT-005-CTLFireability-06 4047404 m, 49291 m/sec, 22243602 t fired, .

Time elapsed: 693 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 80/2982 25/32 BART-PT-005-CTLFireability-06 4296095 m, 49738 m/sec, 23657500 t fired, .

Time elapsed: 698 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 85/2982 27/32 BART-PT-005-CTLFireability-06 4543703 m, 49521 m/sec, 25072421 t fired, .

Time elapsed: 703 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 90/2982 28/32 BART-PT-005-CTLFireability-06 4786807 m, 48620 m/sec, 26484403 t fired, .

Time elapsed: 708 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 95/2982 29/32 BART-PT-005-CTLFireability-06 5028798 m, 48398 m/sec, 27893427 t fired, .

Time elapsed: 713 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 100/2982 31/32 BART-PT-005-CTLFireability-06 5269304 m, 48101 m/sec, 29294763 t fired, .

Time elapsed: 718 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
27 CTL EXCL 105/2982 32/32 BART-PT-005-CTLFireability-06 5507548 m, 47648 m/sec, 30687333 t fired, .

Time elapsed: 723 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 27 (type EXCL) for BART-PT-005-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
BART-PT-005-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
BART-PT-005-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 728 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
BART-PT-005-CTLFireability-00: CTL false CTL model checker
BART-PT-005-CTLFireability-01: CTL false CTL model checker
BART-PT-005-CTLFireability-02: DISJ true CTL model checker
BART-PT-005-CTLFireability-03: CTL unknown AGGR
BART-PT-005-CTLFireability-04: CTL unknown AGGR
BART-PT-005-CTLFireability-05: CTL unknown AGGR
BART-PT-005-CTLFireability-06: CTL unknown AGGR
BART-PT-005-CTLFireability-07: CTL true CTL model checker
BART-PT-005-CTLFireability-08: CTL true CTL model checker
BART-PT-005-CTLFireability-09: CTL false CTL model checker
BART-PT-005-CTLFireability-10: CTL unknown AGGR
BART-PT-005-CTLFireability-11: CTL unknown AGGR
BART-PT-005-CTLFireability-12: EG true state space / EG
BART-PT-005-CTLFireability-13: CTL false CTL model checker
BART-PT-005-CTLFireability-14: CTL unknown AGGR
BART-PT-005-CTLFireability-15: CTL unknown AGGR


Time elapsed: 728 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="BART-PT-005"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is BART-PT-005, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813594800762"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/BART-PT-005.tgz
mv BART-PT-005 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;