Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813594200364.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is Angiogenesis-PT-50, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813594200364
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 520K
-rw-r--r-- 1 mcc users 12K Feb 26 14:53 CTLCardinality.txt
-rw-r--r-- 1 mcc users 122K Feb 26 14:53 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.0K Feb 26 14:52 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K Feb 26 14:52 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Feb 25 15:31 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K Feb 25 15:31 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K Feb 25 15:31 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 15:31 LTLFireability.xml
-rw-r--r-- 1 mcc users 10K Feb 26 14:54 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 92K Feb 26 14:54 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.0K Feb 26 14:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 72K Feb 26 14:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:31 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Feb 25 15:31 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 3 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 33K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-00
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-01
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-02
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-03
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-04
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-05
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-06
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-07
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-08
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-09
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-10
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-11
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-12
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-13
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-14
FORMULA_NAME Angiogenesis-PT-50-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678296713875

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=Angiogenesis-PT-50
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT Angiogenesis-PT-50
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA Angiogenesis-PT-50-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA Angiogenesis-PT-50-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678296734410

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:184
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:499
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:518
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 60 (type EXCL) for 12 Angiogenesis-PT-50-LTLFireability-04
lola: time limit : 120 sec
lola: memory limit: 32 pages
lola: FINISHED task # 60 (type EXCL) for Angiogenesis-PT-50-LTLFireability-04
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 37 (type EXCL) for 30 Angiogenesis-PT-50-LTLFireability-10
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 37 (type EXCL) for Angiogenesis-PT-50-LTLFireability-10
lola: result : false
lola: markings : 36938
lola: fired transitions : 78930
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 58 (type EXCL) for 53 Angiogenesis-PT-50-LTLFireability-15
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for Angiogenesis-PT-50-LTLFireability-15
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 47 Angiogenesis-PT-50-LTLFireability-13
lola: time limit : 257 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-50-LTLFireability-04: F true state space / EG
Angiogenesis-PT-50-LTLFireability-10: CONJ false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-13: LTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 LTL EXCL 5/257 25/32 Angiogenesis-PT-50-LTLFireability-13 3632678 m, 726535 m/sec, 7285573 t fired, .

Time elapsed: 5 secs. Pages in use: 25
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 48 (type EXCL) for Angiogenesis-PT-50-LTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-50-LTLFireability-04: F true state space / EG
Angiogenesis-PT-50-LTLFireability-10: CONJ false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-08: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-12: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-50-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 10 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 45 (type EXCL) for 44 Angiogenesis-PT-50-LTLFireability-12
lola: time limit : 276 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for Angiogenesis-PT-50-LTLFireability-12
lola: result : false
lola: markings : 5
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 25 (type EXCL) for 24 Angiogenesis-PT-50-LTLFireability-08
lola: time limit : 299 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-50-LTLFireability-04: F true state space / EG
Angiogenesis-PT-50-LTLFireability-10: CONJ false LTL model checker
Angiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-08: LTL 0 0 1 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-50-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
25 LTL EXCL 5/299 20/32 Angiogenesis-PT-50-LTLFireability-08 2982146 m, 596429 m/sec, 7708440 t fired, .

Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 25 (type EXCL) for Angiogenesis-PT-50-LTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-50-LTLFireability-04: F true state space / EG
Angiogenesis-PT-50-LTLFireability-10: CONJ false LTL model checker
Angiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
Angiogenesis-PT-50-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-06: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-07: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-08: LTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-50-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-11: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-13: LTL 0 0 0 0 1 0 1 0
Angiogenesis-PT-50-LTLFireability-14: LTL 0 1 0 0 1 0 0 0
Angiogenesis-PT-50-LTLFireability-15: CONJ 0 1 0 0 3 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 22 (type EXCL) for 21 Angiogenesis-PT-50-LTLFireability-07
lola: time limit : 325 sec
lola: memory limit: 32 pages
lola: FINISHED task # 22 (type EXCL) for Angiogenesis-PT-50-LTLFireability-07
lola: result : false
lola: markings : 51055
lola: fired transitions : 100365
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 19 (type EXCL) for 18 Angiogenesis-PT-50-LTLFireability-06
lola: time limit : 358 sec
lola: memory limit: 32 pages
lola: FINISHED task # 19 (type EXCL) for Angiogenesis-PT-50-LTLFireability-06
lola: result : false
lola: markings : 36737
lola: fired transitions : 78480
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 16 (type EXCL) for 15 Angiogenesis-PT-50-LTLFireability-05
lola: time limit : 397 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for Angiogenesis-PT-50-LTLFireability-05
lola: result : false
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 Angiogenesis-PT-50-LTLFireability-03
lola: time limit : 447 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for Angiogenesis-PT-50-LTLFireability-03
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 Angiogenesis-PT-50-LTLFireability-02
lola: time limit : 511 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for Angiogenesis-PT-50-LTLFireability-02
lola: result : false
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 Angiogenesis-PT-50-LTLFireability-00
lola: time limit : 596 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for Angiogenesis-PT-50-LTLFireability-00
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 61 (type EXCL) for 53 Angiogenesis-PT-50-LTLFireability-15
lola: time limit : 716 sec
lola: memory limit: 32 pages
lola: FINISHED task # 61 (type EXCL) for Angiogenesis-PT-50-LTLFireability-15
lola: result : true
lola: markings : 2
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 Angiogenesis-PT-50-LTLFireability-11
lola: time limit : 895 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for Angiogenesis-PT-50-LTLFireability-11
lola: result : false
lola: markings : 7072
lola: fired transitions : 14197
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 Angiogenesis-PT-50-LTLFireability-14
lola: time limit : 1193 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for Angiogenesis-PT-50-LTLFireability-14
lola: result : false
lola: markings : 3
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 Angiogenesis-PT-50-LTLFireability-01
lola: time limit : 1790 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for Angiogenesis-PT-50-LTLFireability-01
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 28 (type EXCL) for 27 Angiogenesis-PT-50-LTLFireability-09
lola: time limit : 3580 sec
lola: memory limit: 32 pages
lola: FINISHED task # 28 (type EXCL) for Angiogenesis-PT-50-LTLFireability-09
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
Angiogenesis-PT-50-LTLFireability-00: LTL true LTL model checker
Angiogenesis-PT-50-LTLFireability-01: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-02: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-03: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-04: F true state space / EG
Angiogenesis-PT-50-LTLFireability-05: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-06: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-07: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-08: LTL unknown AGGR
Angiogenesis-PT-50-LTLFireability-09: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-10: CONJ false LTL model checker
Angiogenesis-PT-50-LTLFireability-11: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-12: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-13: LTL unknown AGGR
Angiogenesis-PT-50-LTLFireability-14: LTL false LTL model checker
Angiogenesis-PT-50-LTLFireability-15: CONJ false state space / EG


Time elapsed: 20 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="Angiogenesis-PT-50"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is Angiogenesis-PT-50, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813594200364"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/Angiogenesis-PT-50.tgz
mv Angiogenesis-PT-50 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;