fond
Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r006-oct2-167813594100276
Last Updated
May 14, 2023

About the Execution of LoLA for AirplaneLD-PT-0200

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
5784.915 3600000.00 475071.00 100.10 FF?FF?F?FFF?F?FT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813594100276.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is AirplaneLD-PT-0200, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813594100276
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 4.1M
-rw-r--r-- 1 mcc users 110K Feb 26 11:32 CTLCardinality.txt
-rw-r--r-- 1 mcc users 411K Feb 26 11:32 CTLCardinality.xml
-rw-r--r-- 1 mcc users 79K Feb 26 11:27 CTLFireability.txt
-rw-r--r-- 1 mcc users 470K Feb 26 11:27 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 50K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 143K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 47K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 213K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 224K Feb 26 11:47 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 807K Feb 26 11:47 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 87K Feb 26 11:40 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 507K Feb 26 11:40 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 31K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 872K Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-00
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-01
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-02
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-03
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-04
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-05
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-06
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-07
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-08
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-09
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-10
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-11
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-12
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-13
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-14
FORMULA_NAME AirplaneLD-PT-0200-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678290811622

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-PT-0200
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT AirplaneLD-PT-0200
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA AirplaneLD-PT-0200-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA AirplaneLD-PT-0200-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
TIME LIMIT: Killed by timeout after 3600 seconds
MemTotal: 16393220 kB
MemFree: 10429644 kB
After kill :
MemTotal: 16393220 kB
MemFree: 16164904 kB

BK_TIME_CONFINEMENT_REACHED

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:524
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 74 (type SKEL/FNDP) for 3 AirplaneLD-PT-0200-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type SKEL/EQUN) for 3 AirplaneLD-PT-0200-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 76 (type SKEL/SRCH) for 3 AirplaneLD-PT-0200-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type SKEL/SRCH) for 3 AirplaneLD-PT-0200-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 77 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-01
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 74 (type FNDP) for AirplaneLD-PT-0200-LTLFireability-01 (obsolete)
lola: CANCELED task # 75 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-01 (obsolete)
lola: CANCELED task # 76 (type SRCH) for AirplaneLD-PT-0200-LTLFireability-01 (obsolete)
lola: FINISHED task # 74 (type SKEL/FNDP) for AirplaneLD-PT-0200-LTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
sara: try reading problem file /home/mcc/execution/LTLFireability-75.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 75 (type SKEL/EQUN) for AirplaneLD-PT-0200-LTLFireability-01
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 80 (type SKEL/FNDP) for 32 AirplaneLD-PT-0200-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type SKEL/EQUN) for 32 AirplaneLD-PT-0200-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 82 (type SKEL/SRCH) for 32 AirplaneLD-PT-0200-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 83 (type SKEL/SRCH) for 32 AirplaneLD-PT-0200-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 83 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH INITIAL
lola: LAUNCH task # 55 (type CNST) for 52 AirplaneLD-PT-0200-LTLFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: CANCELED task # 80 (type FNDP) for AirplaneLD-PT-0200-LTLFireability-08 (obsolete)
lola: CANCELED task # 81 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-08 (obsolete)
lola: CANCELED task # 82 (type SRCH) for AirplaneLD-PT-0200-LTLFireability-08 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 55 (type CNST) for AirplaneLD-PT-0200-LTLFireability-12
lola: result : false
lola: FINISHED task # 82 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 80 (type SKEL/FNDP) for AirplaneLD-PT-0200-LTLFireability-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/LTLFireability-81.sara.
sara: place or transition ordering is non-deterministic

lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: FINISHED task # 81 (type SKEL/EQUN) for AirplaneLD-PT-0200-LTLFireability-08
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 84 (type SKEL/SRCH) for 45 AirplaneLD-PT-0200-LTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 84 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-11
lola: result : true
lola: markings : 848
lola: fired transitions : 1227
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 85 (type SKEL/SRCH) for 45 AirplaneLD-PT-0200-LTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 85 (type SKEL/SRCH) for AirplaneLD-PT-0200-LTLFireability-11
lola: result : false
lola: markings : 492
lola: fired transitions : 1606
lola: time used : 0.000000
lola: memory pages used : 1
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 89 (type EXCL) for 32 AirplaneLD-PT-0200-LTLFireability-08
lola: time limit : 184 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 87 (type FNDP) for 32 AirplaneLD-PT-0200-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 32 AirplaneLD-PT-0200-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type SRCH) for 32 AirplaneLD-PT-0200-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 89 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-08
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 87 (type FNDP) for AirplaneLD-PT-0200-LTLFireability-08 (obsolete)
lola: CANCELED task # 88 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-08 (obsolete)
lola: CANCELED task # 90 (type SRCH) for AirplaneLD-PT-0200-LTLFireability-08 (obsolete)
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 94 (type EXCL) for 3 AirplaneLD-PT-0200-LTLFireability-01
lola: time limit : 194 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 92 (type FNDP) for 3 AirplaneLD-PT-0200-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 93 (type EQUN) for 3 AirplaneLD-PT-0200-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 95 (type SRCH) for 3 AirplaneLD-PT-0200-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 87 (type FNDP) for AirplaneLD-PT-0200-LTLFireability-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/LTLFireability-88.sara.

lola: FINISHED task # 95 (type SRCH) for AirplaneLD-PT-0200-LTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 94 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-01
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 92 (type FNDP) for AirplaneLD-PT-0200-LTLFireability-01 (obsolete)
lola: CANCELED task # 93 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-01 (obsolete)
lola: FINISHED task # 88 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-08
lola: result : true
sara: try reading problem file /home/mcc/execution/LTLFireability-93.sara.

lola: FINISHED task # 93 (type EQUN) for AirplaneLD-PT-0200-LTLFireability-01
lola: result : true
lola: FINISHED task # 92 (type FNDP) for AirplaneLD-PT-0200-LTLFireability-01
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 70 (type EXCL) for 69 AirplaneLD-PT-0200-LTLFireability-15
lola: time limit : 205 sec
lola: memory limit: 32 pages
lola: FINISHED task # 70 (type EXCL) for AirplaneLD-PT-0200-LTLFireability-15
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 45 AirplaneLD-PT-0200-LTLFireability-11
lola: time limit : 218 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-PT-0200-LTLFireability-01: AG false state space
AirplaneLD-PT-0200-LTLFireability-08: AG false state space
AirplaneLD-PT-0200-LTLFireability-12: CONJ false preprocessing
AirplaneLD-PT-0200-LTLFireability-15: LTL true LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-PT-0200-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0200"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is AirplaneLD-PT-0200, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813594100276"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0200.tgz
mv AirplaneLD-PT-0200 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;