About the Execution of LoLA for AirplaneLD-COL-0100
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 2268.848 | 55973.00 | 63390.00 | 49.80 | FFFFFFTFTFTFTTFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813594000196.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is AirplaneLD-COL-0100, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813594000196
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 564K
-rw-r--r-- 1 mcc users 7.3K Feb 26 11:14 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 26 11:14 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.9K Feb 26 11:11 CTLFireability.txt
-rw-r--r-- 1 mcc users 66K Feb 26 11:11 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 17K Feb 26 11:26 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 156K Feb 26 11:26 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 8.9K Feb 26 11:22 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 76K Feb 26 11:22 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 52K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-00
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-01
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-02
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-03
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-04
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-05
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-06
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-07
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-08
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-09
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-10
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-11
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-12
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-13
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-14
FORMULA_NAME AirplaneLD-COL-0100-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678286857702
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-COL-0100
Not applying reductions.
Model is COL
LTLFireability PT
[2023-03-08 14:47:39] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, LTLFireability, --reduce-single, STATESPACE]
[2023-03-08 14:47:40] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-08 14:47:40] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-08 14:47:40] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-08 14:47:40] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 579 ms
[2023-03-08 14:47:40] [INFO ] Detected 3 constant HL places corresponding to 302 PT places.
[2023-03-08 14:47:40] [INFO ] Imported 20 HL places and 15 HL transitions for a total of 719 PT places and 1212.0 transition bindings in 37 ms.
Parsed 16 properties from file ./LTLFireability.xml in 9 ms.
[2023-03-08 14:47:40] [INFO ] Unfolded HLPN to a Petri net with 719 places and 808 transitions 2270 arcs in 43 ms.
[2023-03-08 14:47:40] [INFO ] Unfolded 16 HLPN properties in 1 ms.
Initial state reduction rules removed 4 formulas.
[2023-03-08 14:47:40] [INFO ] Reduced 99 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 99 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 99 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 99 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 199 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 99 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:47:40] [INFO ] Export to MCC of 16 properties in file ./LTLFireability.STATESPACE.xml took 19 ms.
[2023-03-08 14:47:40] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 719 places, 808 transitions and 2270 arcs took 12 ms.
Total runtime 977 ms.
starting LoLA
BK_INPUT AirplaneLD-COL-0100
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfLTLFireability
LTLCardinality
FORMULA AirplaneLD-COL-0100-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0100-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678286913675
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfLTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfLTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfLTLFireability/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 56 (type SKEL/SRCH) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : false
lola: markings : 8
lola: fired transitions : 8
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Rule S: 0 transitions removed,0 places removed
lola: LAUNCH task # 58 (type SKEL/SRCH) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 58 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : true
lola: markings : 7
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH INITIAL
lola: LAUNCH task # 48 (type CNST) for 47 AirplaneLD-COL-0100-LTLFireability-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: NOTDEADLOCKFREE
lola: LAUNCH INITIAL
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 30 (type CNST) for 29 AirplaneLD-COL-0100-LTLFireability-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 48 (type CNST) for AirplaneLD-COL-0100-LTLFireability-13
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 30 (type CNST) for AirplaneLD-COL-0100-LTLFireability-07
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 45 (type CNST) for 44 AirplaneLD-COL-0100-LTLFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 59 (type SKEL/SRCH) for 3 AirplaneLD-COL-0100-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 59 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-01
lola: result : false
lola: markings : 9
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 45 (type CNST) for AirplaneLD-COL-0100-LTLFireability-12
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 62 (type SKEL/FNDP) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type SKEL/EQUN) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 32000000 sec
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SKEL/SRCH) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type SKEL/SRCH) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 65 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 62 (type FNDP) for AirplaneLD-COL-0100-LTLFireability-02 (obsolete)
lola: CANCELED task # 63 (type EQUN) for AirplaneLD-COL-0100-LTLFireability-02 (obsolete)
lola: CANCELED task # 64 (type SRCH) for AirplaneLD-COL-0100-LTLFireability-02 (obsolete)
lola: FINISHED task # 64 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 62 (type SKEL/FNDP) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : true
lola: fired transitions : 2
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH INITIAL
lola: LAUNCH task # 21 (type CNST) for 20 AirplaneLD-COL-0100-LTLFireability-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 69 (type EXCL) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 149 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 67 (type FNDP) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type EQUN) for 6 AirplaneLD-COL-0100-LTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 69 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : true
lola: markings : 3
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 67 (type FNDP) for AirplaneLD-COL-0100-LTLFireability-02 (obsolete)
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lola: FINISHED task # 21 (type CNST) for AirplaneLD-COL-0100-LTLFireability-04
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/unfLTLFireability/LTLCardinality-63.sara.
lola: FINISHED task # 67 (type FNDP) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 63 (type SKEL/EQUN) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : true
sara: try reading problem file /home/mcc/execution/unfLTLFireability/LTLCardinality-68.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 68 (type EQUN) for AirplaneLD-COL-0100-LTLFireability-02
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 73 (type SKEL/SRCH) for 32 AirplaneLD-COL-0100-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: NOTDEADLOCKFREE
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lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 73 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-08
lola: result : false
lola: markings : 55
lola: fired transitions : 54
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 74 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-03
lola: result : false
lola: markings : 207
lola: fired transitions : 207
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-COL-0100-LTLFireability-00
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-00
lola: result : false
lola: markings : 10
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 27 (type EXCL) for 26 AirplaneLD-COL-0100-LTLFireability-06
lola: time limit : 239 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 75 (type SKEL/SRCH) for 23 AirplaneLD-COL-0100-LTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 75 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-05
lola: result : false
lola: markings : 10
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: FINISHED task # 27 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-06
lola: result : true
lola: markings : 405
lola: fired transitions : 404
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 39 (type EXCL) for 38 AirplaneLD-COL-0100-LTLFireability-10
lola: time limit : 359 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 77 (type SKEL/SRCH) for 35 AirplaneLD-COL-0100-LTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 77 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-09
lola: result : false
lola: markings : 962
lola: fired transitions : 1590
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 78 (type SKEL/SRCH) for 38 AirplaneLD-COL-0100-LTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 79 (type SKEL/SRCH) for 41 AirplaneLD-COL-0100-LTLFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 79 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-11
lola: result : false
lola: markings : 12
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 81 (type SKEL/SRCH) for 53 AirplaneLD-COL-0100-LTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 81 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-15
lola: result : true
lola: markings : 8542
lola: fired transitions : 32411
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 78 (type SKEL/SRCH) for AirplaneLD-COL-0100-LTLFireability-10
lola: result : true
lola: markings : 22847
lola: fired transitions : 75902
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 39 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-10 (obsolete)
lola: LAUNCH task # 51 (type EXCL) for 50 AirplaneLD-COL-0100-LTLFireability-14
lola: time limit : 598 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-14
lola: result : false
lola: markings : 55
lola: fired transitions : 65
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 AirplaneLD-COL-0100-LTLFireability-11
lola: time limit : 718 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-11
lola: result : false
lola: markings : 13
lola: fired transitions : 14
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 AirplaneLD-COL-0100-LTLFireability-09
lola: time limit : 897 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0100-LTLFireability-00: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-02: CONJ false state space
AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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AirplaneLD-COL-0100-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 LTL EXCL 4/897 6/32 AirplaneLD-COL-0100-LTLFireability-09 699882 m, 139976 m/sec, 1039882 t fired, .
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AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
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AirplaneLD-COL-0100-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 LTL EXCL 9/897 12/32 AirplaneLD-COL-0100-LTLFireability-09 1507187 m, 161461 m/sec, 2237186 t fired, .
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AirplaneLD-COL-0100-LTLFireability-00: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-02: CONJ false state space
AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 LTL EXCL 14/897 18/32 AirplaneLD-COL-0100-LTLFireability-09 2308712 m, 160305 m/sec, 3438711 t fired, .
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AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
AirplaneLD-COL-0100-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
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AirplaneLD-COL-0100-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 LTL EXCL 19/897 24/32 AirplaneLD-COL-0100-LTLFireability-09 3116113 m, 161480 m/sec, 4636112 t fired, .
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AirplaneLD-COL-0100-LTLFireability-00: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-02: CONJ false state space
AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 LTL EXCL 24/897 30/32 AirplaneLD-COL-0100-LTLFireability-09 3919468 m, 160671 m/sec, 5839467 t fired, .
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AirplaneLD-COL-0100-LTLFireability-00: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-02: CONJ false state space
AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 LTL EXCL 29/897 31/32 AirplaneLD-COL-0100-LTLFireability-09 4083855 m, 32877 m/sec, 6429181 t fired, .
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AirplaneLD-COL-0100-LTLFireability-00: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-02: CONJ false state space
AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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36 LTL EXCL 34/897 31/32 AirplaneLD-COL-0100-LTLFireability-09 4088517 m, 932 m/sec, 6900026 t fired, .
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AirplaneLD-COL-0100-LTLFireability-00: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-02: CONJ false state space
AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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AirplaneLD-COL-0100-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
36 LTL EXCL 39/897 31/32 AirplaneLD-COL-0100-LTLFireability-09 4094649 m, 1226 m/sec, 7519303 t fired, .
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# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 36 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-09
lola: result : false
lola: markings : 4100810
lola: fired transitions : 8150810
lola: time used : 42.000000
lola: memory pages used : 32
lola: LAUNCH task # 24 (type EXCL) for 23 AirplaneLD-COL-0100-LTLFireability-05
lola: time limit : 1182 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-05
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 18 (type EXCL) for 17 AirplaneLD-COL-0100-LTLFireability-03
lola: time limit : 1774 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-03
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 AirplaneLD-COL-0100-LTLFireability-01
lola: time limit : 3548 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for AirplaneLD-COL-0100-LTLFireability-01
lola: result : false
lola: markings : 9
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0100-LTLFireability-00: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-01: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-02: CONJ false state space
AirplaneLD-COL-0100-LTLFireability-03: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-04: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-05: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-06: LTL true LTL model checker
AirplaneLD-COL-0100-LTLFireability-07: INITIAL false preprocessing
AirplaneLD-COL-0100-LTLFireability-08: F true skeleton: state space / EG
AirplaneLD-COL-0100-LTLFireability-09: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-10: LTL true skeleton: LTL model checker
AirplaneLD-COL-0100-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-12: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-13: INITIAL true preprocessing
AirplaneLD-COL-0100-LTLFireability-14: LTL false LTL model checker
AirplaneLD-COL-0100-LTLFireability-15: LTL true skeleton: LTL model checker
Time elapsed: 52 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0100"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0100, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813594000196"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0100.tgz
mv AirplaneLD-COL-0100 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;