About the Execution of LoLA for AirplaneLD-COL-0010
Execution Summary | |||||
Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
184.308 | 3250.00 | 6173.00 | 17.60 | FFTTTFFFTFFFFFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813593900172.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is AirplaneLD-COL-0010, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813593900172
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 444K
-rw-r--r-- 1 mcc users 7.7K Feb 26 11:10 CTLCardinality.txt
-rw-r--r-- 1 mcc users 74K Feb 26 11:10 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.6K Feb 26 11:08 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K Feb 26 11:08 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Feb 25 15:30 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Feb 25 15:30 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:30 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:30 LTLFireability.xml
-rw-r--r-- 1 mcc users 11K Feb 26 11:13 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 93K Feb 26 11:13 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Feb 26 11:12 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 54K Feb 26 11:12 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Feb 25 15:30 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:30 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 equiv_pt
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 40K Mar 5 18:22 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-00
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-01
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-02
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-03
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-04
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-05
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-06
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-07
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-08
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-09
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-10
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-11
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-12
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-13
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-14
FORMULA_NAME AirplaneLD-COL-0010-LTLFireability-15
=== Now, execution of the tool begins
BK_START 1678286453746
bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=AirplaneLD-COL-0010
Not applying reductions.
Model is COL
LTLFireability PT
[2023-03-08 14:40:55] [INFO ] Running its-tools with arguments : [-pnfolder, ., -examination, LTLFireability, --reduce-single, STATESPACE]
[2023-03-08 14:40:55] [INFO ] Parsing pnml file : /home/mcc/execution/./model.pnml
[2023-03-08 14:40:55] [INFO ] Detected file is not PT type :http://www.pnml.org/version-2009/grammar/symmetricnet
log4j:WARN No appenders could be found for logger (org.apache.axiom.locator.DefaultOMMetaFactoryLocator).
log4j:WARN Please initialize the log4j system properly.
log4j:WARN See http://logging.apache.org/log4j/1.2/faq.html#noconfig for more info.
[2023-03-08 14:40:56] [WARNING] Using fallBack plugin, rng conformance not checked
[2023-03-08 14:40:56] [INFO ] Load time of PNML (colored model parsed with PNMLFW) : 516 ms
[2023-03-08 14:40:56] [INFO ] Detected 3 constant HL places corresponding to 32 PT places.
[2023-03-08 14:40:56] [INFO ] Imported 20 HL places and 15 HL transitions for a total of 89 PT places and 132.0 transition bindings in 26 ms.
Parsed 16 properties from file ./LTLFireability.xml in 10 ms.
[2023-03-08 14:40:56] [INFO ] Unfolded HLPN to a Petri net with 89 places and 88 transitions 245 arcs in 22 ms.
[2023-03-08 14:40:56] [INFO ] Unfolded 16 HLPN properties in 0 ms.
Initial state reduction rules removed 6 formulas.
[2023-03-08 14:40:56] [INFO ] Reduced 9 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 9 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 19 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 9 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 9 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 9 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Reduced 1 identical enabling conditions.
[2023-03-08 14:40:56] [INFO ] Export to MCC of 16 properties in file ./LTLFireability.STATESPACE.xml took 6 ms.
[2023-03-08 14:40:56] [INFO ] Export to PNML in file ./model.STATESPACE.pnml of net with 89 places, 88 transitions and 245 arcs took 11 ms.
Total runtime 744 ms.
starting LoLA
BK_INPUT AirplaneLD-COL-0010
BK_EXAMINATION: LTLCardinality
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution/unfLTLFireability
LTLCardinality
FORMULA AirplaneLD-COL-0010-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA AirplaneLD-COL-0010-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1678286456996
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/unfLTLFireability/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/unfLTLFireability/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/unfLTLFireability/LTLCardinality.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:373
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:349
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 68 (type SKEL/SRCH) for 3 AirplaneLD-COL-0010-LTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 68 (type SKEL/SRCH) for AirplaneLD-COL-0010-LTLFireability-01
lola: result : false
lola: markings : 13
lola: fired transitions : 13
lola: time used : 0.000000
lola: memory pages used : 1
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH INITIAL
lola: LAUNCH task # 15 (type CNST) for 14 AirplaneLD-COL-0010-LTLFireability-02
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH task # 51 (type EXCL) for 44 AirplaneLD-COL-0010-LTLFireability-12
lola: time limit : 105 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type CNST) for AirplaneLD-COL-0010-LTLFireability-02
lola: result : true
lola: LAUNCH INITIAL
lola: LAUNCH task # 33 (type CNST) for 32 AirplaneLD-COL-0010-LTLFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 18 (type CNST) for 17 AirplaneLD-COL-0010-LTLFireability-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 51 (type EXCL) for AirplaneLD-COL-0010-LTLFireability-12
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 AirplaneLD-COL-0010-LTLFireability-11
lola: time limit : 144 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type CNST) for AirplaneLD-COL-0010-LTLFireability-03
lola: result : true
lola: FINISHED task # 42 (type EXCL) for AirplaneLD-COL-0010-LTLFireability-11
lola: result : false
lola: markings : 9
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: NOTDEADLOCKFREE
lola: NOTDEADLOCKFREE
lola: planning for (null) stopped (result already fixed).
lola: planning for (null) stopped (result already fixed).
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: FINISHED task # 33 (type CNST) for AirplaneLD-COL-0010-LTLFireability-08
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 36 (type EXCL) for 35 AirplaneLD-COL-0010-LTLFireability-09
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 72 (type SKEL/SRCH) for 20 AirplaneLD-COL-0010-LTLFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 63 (type CNST) for 62 AirplaneLD-COL-0010-LTLFireability-14
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 70 (type FNDP) for 55 AirplaneLD-COL-0010-LTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 72 (type SKEL/SRCH) for AirplaneLD-COL-0010-LTLFireability-04
lola: result : true
lola: markings : 317
lola: fired transitions : 644
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 71 (type EQUN) for 55 AirplaneLD-COL-0010-LTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type CNST) for AirplaneLD-COL-0010-LTLFireability-14
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 75 (type SRCH) for 55 AirplaneLD-COL-0010-LTLFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: planning for (null) stopped (result already fixed).
lola: LAUNCH INITIAL
lola: LAUNCH task # 27 (type CNST) for 26 AirplaneLD-COL-0010-LTLFireability-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 36 (type EXCL) for AirplaneLD-COL-0010-LTLFireability-09
lola: result : false
lola: markings : 12
lola: fired transitions : 12
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH INITIAL
lola: LAUNCH task # 39 (type CNST) for 38 AirplaneLD-COL-0010-LTLFireability-10
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 70 (type FNDP) for AirplaneLD-COL-0010-LTLFireability-13
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: planning for (null) stopped (result already fixed).
lola: planning for AirplaneLD-COL-0010-LTLFireability-04 stopped (result already fixed).
lola: FINISHED task # 75 (type SRCH) for AirplaneLD-COL-0010-LTLFireability-13
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 27 (type CNST) for AirplaneLD-COL-0010-LTLFireability-06
lola: result : false
lola: FINISHED task # 39 (type CNST) for AirplaneLD-COL-0010-LTLFireability-10
lola: result : false
lola: CANCELED task # 71 (type EQUN) for AirplaneLD-COL-0010-LTLFireability-13 (obsolete)
lola: LAUNCH task # 66 (type EXCL) for 65 AirplaneLD-COL-0010-LTLFireability-15
lola: time limit : 600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 66 (type EXCL) for AirplaneLD-COL-0010-LTLFireability-15
lola: result : false
lola: markings : 21
lola: fired transitions : 21
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 AirplaneLD-COL-0010-LTLFireability-00
lola: time limit : 900 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 71 (type EQUN) for AirplaneLD-COL-0010-LTLFireability-13
lola: result : unknown
lola: FINISHED task # 1 (type EXCL) for AirplaneLD-COL-0010-LTLFireability-00
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 AirplaneLD-COL-0010-LTLFireability-07
lola: time limit : 1800 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for AirplaneLD-COL-0010-LTLFireability-07
lola: result : false
lola: markings : 9
lola: fired transitions : 9
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
lola: LAUNCH task # 24 (type EXCL) for 23 AirplaneLD-COL-0010-LTLFireability-05
lola: time limit : 3600 sec
lola: memory limit: 32 pages
lola: FINISHED task # 24 (type EXCL) for AirplaneLD-COL-0010-LTLFireability-05
lola: result : false
lola: markings : 11
lola: fired transitions : 11
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
AirplaneLD-COL-0010-LTLFireability-00: LTL false LTL model checker
AirplaneLD-COL-0010-LTLFireability-01: CONJ false skeleton: LTL model checker
AirplaneLD-COL-0010-LTLFireability-02: INITIAL true preprocessing
AirplaneLD-COL-0010-LTLFireability-03: INITIAL true preprocessing
AirplaneLD-COL-0010-LTLFireability-04: LTL true skeleton: LTL model checker
AirplaneLD-COL-0010-LTLFireability-05: LTL false LTL model checker
AirplaneLD-COL-0010-LTLFireability-06: INITIAL false preprocessing
AirplaneLD-COL-0010-LTLFireability-07: LTL false LTL model checker
AirplaneLD-COL-0010-LTLFireability-08: INITIAL true preprocessing
AirplaneLD-COL-0010-LTLFireability-09: LTL false LTL model checker
AirplaneLD-COL-0010-LTLFireability-10: INITIAL false preprocessing
AirplaneLD-COL-0010-LTLFireability-11: LTL false LTL model checker
AirplaneLD-COL-0010-LTLFireability-12: CONJ false LTL model checker
AirplaneLD-COL-0010-LTLFireability-13: CONJ false findpath
AirplaneLD-COL-0010-LTLFireability-14: INITIAL true preprocessing
AirplaneLD-COL-0010-LTLFireability-15: LTL false LTL model checker
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lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-COL-0010"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is AirplaneLD-COL-0010, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813593900172"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-COL-0010.tgz
mv AirplaneLD-COL-0010 execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;