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Model Checking Contest 2023
13th edition, Paris, France, April 26, 2023 (at TOOLympics II)
Execution of r006-oct2-167813593700007
Last Updated
May 14, 2023

About the Execution of LoLA for ARMCacheCoherence-PT-none

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3690.176 54953.00 151858.00 12.60 FTFTTFFFFFFTTTFF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813593700007.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.........................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ARMCacheCoherence-PT-none, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813593700007
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 6.6K Feb 25 21:34 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 25 21:34 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 21:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 21:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 21:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 163K Feb 25 21:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 25 21:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 21:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:28 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 14M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-00
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-01
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-02
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-03
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-04
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-05
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-06
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-07
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-08
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-09
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-10
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-11
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-12
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-13
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-14
FORMULA_NAME ARMCacheCoherence-PT-none-ReachabilityFireability-15

=== Now, execution of the tool begins

BK_START 1678267764504

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=ReachabilityFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ARMCacheCoherence-PT-none
Not applying reductions.
Model is PT
ReachabilityFireability PT
starting LoLA
BK_INPUT ARMCacheCoherence-PT-none
BK_EXAMINATION: ReachabilityFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
ReachabilityFireability

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-ReachabilityFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678267819457

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 ARMCacheCoherence-PT-none-ReachabilityFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 25 (type CNST) for 24 ARMCacheCoherence-PT-none-ReachabilityFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 39 ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: time limit : 178 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 39 ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 1 (type CNST) for ARMCacheCoherence-PT-none-ReachabilityFireability-00
lola: result : false
lola: LAUNCH task # 49 (type EQUN) for 39 ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 25 (type CNST) for ARMCacheCoherence-PT-none-ReachabilityFireability-08
lola: result : false
lola: LAUNCH task # 51 (type SRCH) for 39 ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 51 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: result : true
lola: markings : 787
lola: fired transitions : 1676
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 48 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-13 (obsolete)
lola: CANCELED task # 49 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-13 (obsolete)
lola: CANCELED task # 52 (type EXCL) for ARMCacheCoherence-PT-none-ReachabilityFireability-13 (obsolete)
lola: FINISHED task # 48 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: result : unknown
lola: fired transitions : 368
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-49.sara.
lola: Created skeleton in 0.000000 secs.
sara: place or transition ordering is non-deterministic
lola: LAUNCH INITIAL
lola: LAUNCH task # 46 (type CNST) for 45 ARMCacheCoherence-PT-none-ReachabilityFireability-15
lola: time limit : 0 sec
lola: memory limit: 0 pages

lola: FINISHED task # 46 (type CNST) for ARMCacheCoherence-PT-none-ReachabilityFireability-15
lola: result : false
lola: FINISHED task # 49 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-13
lola: result : true
lola: Created skeleton in 1.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 60 (type EXCL) for 36 ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: time limit : 447 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 36 ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 57 (type EQUN) for 36 ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 59 (type SRCH) for 36 ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH INITIAL
lola: LAUNCH task # 22 (type CNST) for 21 ARMCacheCoherence-PT-none-ReachabilityFireability-07
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 22 (type CNST) for ARMCacheCoherence-PT-none-ReachabilityFireability-07
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-57.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG 0 1 4 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 2/238 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 60200 t fired, 15 attempts, .
57 EF STEQ 2/238 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 sara is running.
59 EF SRCH 2/255 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-12 55333 m, 11066 m/sec, 131296 t fired, .
60 EF EXCL 2/325 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-12 8720 m, 1744 m/sec, 36317 t fired, .

Time elapsed: 26 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16

lola: FINISHED task # 57 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: result : false
lola: CANCELED task # 55 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-12 (obsolete)
lola: CANCELED task # 59 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-12 (obsolete)
lola: CANCELED task # 60 (type EXCL) for ARMCacheCoherence-PT-none-ReachabilityFireability-12 (obsolete)
lola: LAUNCH task # 109 (type EXCL) for 15 ARMCacheCoherence-PT-none-ReachabilityFireability-05
lola: time limit : 357 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 98 (type FNDP) for 42 ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 101 (type EQUN) for 42 ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 103 (type SRCH) for 42 ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-12
lola: result : unknown
lola: fired transitions : 146972
lola: tried executions : 25
lola: time used : 5.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 98 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: result : true
lola: fired transitions : 6
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 101 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-14 (obsolete)
lola: CANCELED task # 103 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-14 (obsolete)
lola: LAUNCH task # 56 (type FNDP) for 33 ARMCacheCoherence-PT-none-ReachabilityFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 61 (type EQUN) for 33 ARMCacheCoherence-PT-none-ReachabilityFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SRCH) for 33 ARMCacheCoherence-PT-none-ReachabilityFireability-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 103 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-14
lola: result : true
lola: markings : 8
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 85 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-11
lola: result : true
lola: markings : 676
lola: fired transitions : 1479
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 56 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-11 (obsolete)
lola: CANCELED task # 61 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-11 (obsolete)
lola: LAUNCH task # 99 (type FNDP) for 12 ARMCacheCoherence-PT-none-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 111 (type EQUN) for 12 ARMCacheCoherence-PT-none-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 122 (type SRCH) for 12 ARMCacheCoherence-PT-none-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-11
lola: result : unknown
lola: fired transitions : 286
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-111.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-101.sara.
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false findpath
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
99 EF FNDP 2/324 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 33667 t fired, 2 attempts, .
109 EF EXCL 2/446 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-05 12126 m, 2425 m/sec, 43824 t fired, .
111 EF STEQ 2/324 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 sara is running.
122 EF SRCH 2/357 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 29266 m, 5853 m/sec, 59603 t fired, .

Time elapsed: 31 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false findpath
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
99 EF FNDP 7/322 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 113033 t fired, 5 attempts, .
109 EF EXCL 7/446 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-05 47747 m, 7124 m/sec, 175853 t fired, .
111 EF STEQ 7/322 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 sara is running.
122 EF SRCH 7/355 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-04 112309 m, 16608 m/sec, 237539 t fired, .

Time elapsed: 36 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 109 (type EXCL) for ARMCacheCoherence-PT-none-ReachabilityFireability-05
lola: result : true
lola: markings : 70283
lola: fired transitions : 260742
lola: time used : 10.000000
lola: memory pages used : 1
lola: LAUNCH task # 83 (type EXCL) for 18 ARMCacheCoherence-PT-none-ReachabilityFireability-06
lola: time limit : 508 sec
lola: memory limit: 32 pages

lola: FINISHED task # 111 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-04
lola: result : false
lola: CANCELED task # 99 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-04 (obsolete)
lola: CANCELED task # 122 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-04 (obsolete)
lola: LAUNCH task # 87 (type FNDP) for 9 ARMCacheCoherence-PT-none-ReachabilityFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 9 ARMCacheCoherence-PT-none-ReachabilityFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 106 (type SRCH) for 9 ARMCacheCoherence-PT-none-ReachabilityFireability-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 99 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-04
lola: result : unknown
lola: fired transitions : 170284
lola: tried executions : 6
lola: time used : 10.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-88.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 83 (type EXCL) for ARMCacheCoherence-PT-none-ReachabilityFireability-06
lola: result : true
lola: markings : 10440
lola: fired transitions : 42725
lola: time used : 2.000000
lola: memory pages used : 1
lola: LAUNCH task # 76 (type EXCL) for 3 ARMCacheCoherence-PT-none-ReachabilityFireability-01
lola: time limit : 711 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG false tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG false tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false findpath
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
76 EF EXCL 0/711 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-01 1461 m, 292 m/sec, 6632 t fired, .
87 EF FNDP 2/506 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-03 32864 t fired, 2 attempts, .
88 EF STEQ 2/506 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-03 sara is running.
106 EF SRCH 2/591 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-03 19764 m, 3952 m/sec, 43976 t fired, .

Time elapsed: 41 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16

lola: FINISHED task # 88 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-03
lola: result : false
lola: CANCELED task # 87 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-03 (obsolete)
lola: CANCELED task # 106 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-03 (obsolete)
lola: LAUNCH task # 64 (type FNDP) for 27 ARMCacheCoherence-PT-none-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type EQUN) for 27 ARMCacheCoherence-PT-none-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type SRCH) for 27 ARMCacheCoherence-PT-none-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 87 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-03
lola: result : unknown
lola: fired transitions : 92599
lola: tried executions : 3
lola: time used : 5.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-66.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG false tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG false tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false findpath
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF 0 4 1 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EF FNDP 2/592 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 25467 t fired, 5 attempts, .
66 EF STEQ 2/711 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 sara is running.
70 EF SRCH 2/711 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 28259 m, 5651 m/sec, 54067 t fired, .
76 EF EXCL 5/889 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-01 29823 m, 5672 m/sec, 135814 t fired, .

Time elapsed: 46 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 76 (type EXCL) for ARMCacheCoherence-PT-none-ReachabilityFireability-01
lola: result : true
lola: markings : 50699
lola: fired transitions : 231470
lola: time used : 9.000000
lola: memory pages used : 1
lola: LAUNCH task # 115 (type EXCL) for 30 ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: time limit : 1183 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF true tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG false tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG false tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false findpath
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF 0 2 3 0 1 0 0 0
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF 0 4 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 EF FNDP 7/883 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 123066 t fired, 59 attempts, .
66 EF STEQ 7/883 0/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 sara is running.
70 EF SRCH 7/883 1/5 ARMCacheCoherence-PT-none-ReachabilityFireability-09 106384 m, 15625 m/sec, 221418 t fired, .
115 EF EXCL 1/1183 1/32 ARMCacheCoherence-PT-none-ReachabilityFireability-10 5002 m, 1000 m/sec, 20934 t fired, .

Time elapsed: 51 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 61 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-11
lola: result : unknown

lola: FINISHED task # 66 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-09
lola: result : false
lola: CANCELED task # 64 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-09 (obsolete)
lola: CANCELED task # 70 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-09 (obsolete)
lola: LAUNCH task # 100 (type FNDP) for 6 ARMCacheCoherence-PT-none-ReachabilityFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 116 (type EQUN) for 6 ARMCacheCoherence-PT-none-ReachabilityFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 118 (type SRCH) for 6 ARMCacheCoherence-PT-none-ReachabilityFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-09
lola: result : unknown
lola: fired transitions : 186434
lola: tried executions : 87
lola: time used : 10.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-116.sara.
lola: FINISHED task # 100 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-02
lola: result : true
lola: fired transitions : 2056
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 116 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-02 (obsolete)
lola: CANCELED task # 118 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-02 (obsolete)
lola: LAUNCH task # 65 (type FNDP) for 30 ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 90 (type EQUN) for 30 ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 114 (type SRCH) for 30 ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 116 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-02
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-90.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 90 (type EQUN) for ARMCacheCoherence-PT-none-ReachabilityFireability-10
lola: result : false
lola: CANCELED task # 65 (type FNDP) for ARMCacheCoherence-PT-none-ReachabilityFireability-10 (obsolete)
lola: CANCELED task # 114 (type SRCH) for ARMCacheCoherence-PT-none-ReachabilityFireability-10 (obsolete)
lola: CANCELED task # 115 (type EXCL) for ARMCacheCoherence-PT-none-ReachabilityFireability-10 (obsolete)
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-ReachabilityFireability-00: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-01: EF true tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-02: AG false findpath
ARMCacheCoherence-PT-none-ReachabilityFireability-03: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-04: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-05: AG false tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-06: AG false tandem / relaxed
ARMCacheCoherence-PT-none-ReachabilityFireability-07: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-08: INITIAL false preprocessing
ARMCacheCoherence-PT-none-ReachabilityFireability-09: EF false state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-10: EF false state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-11: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-12: AG true state equation
ARMCacheCoherence-PT-none-ReachabilityFireability-13: EF true tandem / insertion
ARMCacheCoherence-PT-none-ReachabilityFireability-14: AG false findpath
ARMCacheCoherence-PT-none-ReachabilityFireability-15: INITIAL false preprocessing


Time elapsed: 55 secs. Pages in use: 3

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ARMCacheCoherence-PT-none, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813593700007"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;