Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2023-input.r006-oct2-167813593700004.qcow2', fmt=qcow2 cluster_size=65536 extended_l2=off compression_type=zlib size=4294967296 backing_file=/data/fkordon/mcc2023-input.qcow2 backing_fmt=qcow2 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
......................
=====================================================================
Generated by BenchKit 2-5348
Executing tool lola
Input is ARMCacheCoherence-PT-none, examination is LTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r006-oct2-167813593700004
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 6.6K Feb 25 21:34 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Feb 25 21:34 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.7K Feb 25 21:22 CTLFireability.txt
-rw-r--r-- 1 mcc users 52K Feb 25 21:22 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Jan 29 11:40 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.3K Jan 29 11:40 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.6K Feb 25 15:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Feb 25 15:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K Feb 25 15:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Feb 25 15:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 14K Feb 25 21:56 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 163K Feb 25 21:56 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 9.0K Feb 25 21:46 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 74K Feb 25 21:46 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.7K Feb 25 15:28 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Feb 25 15:28 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 equiv_col
-rw-r--r-- 1 mcc users 5 Mar 5 18:22 instance
-rw-r--r-- 1 mcc users 6 Mar 5 18:22 iscolored
-rw-r--r-- 1 mcc users 14M Mar 5 18:22 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-00
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-01
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-02
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-03
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-04
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-05
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-06
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-07
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-08
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-09
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-10
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-11
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-12
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-13
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-14
FORMULA_NAME ARMCacheCoherence-PT-none-LTLFireability-15

=== Now, execution of the tool begins

BK_START 1678267764263

bash -c /home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n "BK_STOP " ; date -u +%s%3N
Invoking MCC driver with
BK_TOOL=lola
BK_EXAMINATION=LTLFireability
BK_BIN_PATH=/home/mcc/BenchKit/bin/
BK_TIME_CONFINEMENT=3600
BK_INPUT=ARMCacheCoherence-PT-none
Not applying reductions.
Model is PT
LTLFireability PT
starting LoLA
BK_INPUT ARMCacheCoherence-PT-none
BK_EXAMINATION: LTLFireability
bin directory: /home/mcc/BenchKit/bin//../lola/bin/
current directory: /home/mcc/execution
LTLFireability

FORMULA ARMCacheCoherence-PT-none-LTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ARMCacheCoherence-PT-none-LTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1678267790402

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/LTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:370
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:527
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:436
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:376
lola: rewrite Frontend/Parser/formula_rewrite.k:521
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:535
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:430
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:433
lola: rewrite Frontend/Parser/formula_rewrite.k:355
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:409
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:352
lola: rewrite Frontend/Parser/formula_rewrite.k:421
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:379
lola: rewrite Frontend/Parser/formula_rewrite.k:346
lola: rewrite Frontend/Parser/formula_rewrite.k:427
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 39 (type EXCL) for 38 ARMCacheCoherence-PT-none-LTLFireability-10
lola: time limit : 171 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:735
lola: rewrite Frontend/Parser/formula_rewrite.k:695
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 59 (type FNDP) for 28 ARMCacheCoherence-PT-none-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 60 (type EQUN) for 28 ARMCacheCoherence-PT-none-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type SRCH) for 28 ARMCacheCoherence-PT-none-LTLFireability-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 62 (type SRCH) for ARMCacheCoherence-PT-none-LTLFireability-08
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 59 (type FNDP) for ARMCacheCoherence-PT-none-LTLFireability-08
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 60 (type EQUN) for ARMCacheCoherence-PT-none-LTLFireability-08 (obsolete)
lola: FINISHED task # 39 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-10
lola: result : false
lola: markings : 13647
lola: fired transitions : 32321
lola: time used : 1.000000
lola: memory pages used : 1
lola: LAUNCH task # 51 (type EXCL) for 50 ARMCacheCoherence-PT-none-LTLFireability-14
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 51 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-14
lola: result : false
lola: markings : 4
lola: fired transitions : 4
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 ARMCacheCoherence-PT-none-LTLFireability-12
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-12
lola: result : false
lola: markings : 6
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 42 (type EXCL) for 41 ARMCacheCoherence-PT-none-LTLFireability-11
lola: time limit : 239 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/LTLFireability-60.sara.
lola: Created skeleton in 1.000000 secs.
sara: place or transition ordering is non-deterministic
lola: Created skeleton in 0.000000 secs.

lola: FINISHED task # 60 (type EQUN) for ARMCacheCoherence-PT-none-LTLFireability-08
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 42 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-11
lola: result : false
lola: markings : 297204
lola: fired transitions : 915468
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 26 (type EXCL) for 25 ARMCacheCoherence-PT-none-LTLFireability-07
lola: time limit : 299 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-07
lola: result : false
lola: markings : 41123
lola: fired transitions : 108003
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 18 ARMCacheCoherence-PT-none-LTLFireability-06
lola: time limit : 326 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-LTLFireability-07: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-08: CONJ false findpath
ARMCacheCoherence-PT-none-LTLFireability-10: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-11: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-12: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-14: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-LTLFireability-00: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-01: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-02: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-04: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-05: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-06: CONJ 0 1 1 0 2 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-09: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-13: AU 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-15: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 LTL EXCL 0/326 1/32 ARMCacheCoherence-PT-none-LTLFireability-06 4683 m, 936 m/sec, 7520 t fired, .

Time elapsed: 5 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 23 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-06
lola: result : false
lola: markings : 251874
lola: fired transitions : 551617
lola: time used : 2.000000
lola: memory pages used : 2
lola: LAUNCH task # 16 (type EXCL) for 15 ARMCacheCoherence-PT-none-LTLFireability-05
lola: time limit : 399 sec
lola: memory limit: 32 pages
lola: FINISHED task # 16 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-05
lola: result : false
lola: markings : 7
lola: fired transitions : 7
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 7 (type EXCL) for 6 ARMCacheCoherence-PT-none-LTLFireability-02
lola: time limit : 449 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-02
lola: result : false
lola: markings : 7
lola: fired transitions : 10
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 ARMCacheCoherence-PT-none-LTLFireability-01
lola: time limit : 513 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-01
lola: result : false
lola: markings : 265341
lola: fired transitions : 1101646
lola: time used : 1.000000
lola: memory pages used : 2
lola: LAUNCH task # 57 (type EXCL) for 47 ARMCacheCoherence-PT-none-LTLFireability-13
lola: time limit : 598 sec
lola: memory limit: 32 pages
lola: FINISHED task # 57 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-13
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 ARMCacheCoherence-PT-none-LTLFireability-00
lola: time limit : 718 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-00
lola: result : false
lola: markings : 2975
lola: fired transitions : 11907
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 54 (type EXCL) for 53 ARMCacheCoherence-PT-none-LTLFireability-15
lola: time limit : 898 sec
lola: memory limit: 32 pages
lola: FINISHED task # 54 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-15
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 ARMCacheCoherence-PT-none-LTLFireability-04
lola: time limit : 1197 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-LTLFireability-00: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-01: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-02: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-05: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-06: CONJ false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-07: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-08: CONJ false findpath
ARMCacheCoherence-PT-none-LTLFireability-10: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-11: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-12: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-13: AU false state space /ER
ARMCacheCoherence-PT-none-LTLFireability-14: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-09: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 LTL EXCL 3/1197 1/32 ARMCacheCoherence-PT-none-LTLFireability-04 33194 m, 6638 m/sec, 111500 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-LTLFireability-00: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-01: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-02: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-05: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-06: CONJ false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-07: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-08: CONJ false findpath
ARMCacheCoherence-PT-none-LTLFireability-10: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-11: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-12: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-13: AU false state space /ER
ARMCacheCoherence-PT-none-LTLFireability-14: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-09: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 LTL EXCL 8/1197 1/32 ARMCacheCoherence-PT-none-LTLFireability-04 111229 m, 15607 m/sec, 392638 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-LTLFireability-00: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-01: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-02: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-05: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-06: CONJ false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-07: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-08: CONJ false findpath
ARMCacheCoherence-PT-none-LTLFireability-10: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-11: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-12: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-13: AU false state space /ER
ARMCacheCoherence-PT-none-LTLFireability-14: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-09: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 LTL EXCL 13/1197 2/32 ARMCacheCoherence-PT-none-LTLFireability-04 189294 m, 15613 m/sec, 690452 t fired, .

Time elapsed: 21 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-LTLFireability-00: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-01: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-02: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-05: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-06: CONJ false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-07: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-08: CONJ false findpath
ARMCacheCoherence-PT-none-LTLFireability-10: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-11: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-12: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-13: AU false state space /ER
ARMCacheCoherence-PT-none-LTLFireability-14: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-15: LTL false LTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ARMCacheCoherence-PT-none-LTLFireability-03: LTL 0 1 0 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-04: LTL 0 0 1 0 1 0 0 0
ARMCacheCoherence-PT-none-LTLFireability-09: LTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 LTL EXCL 18/1197 2/32 ARMCacheCoherence-PT-none-LTLFireability-04 267300 m, 15601 m/sec, 994964 t fired, .

Time elapsed: 26 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 13 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-04
lola: result : false
lola: markings : 270618
lola: fired transitions : 1006028
lola: time used : 18.000000
lola: memory pages used : 2
lola: LAUNCH task # 36 (type EXCL) for 35 ARMCacheCoherence-PT-none-LTLFireability-09
lola: time limit : 1787 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-09
lola: result : false
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 10 (type EXCL) for 9 ARMCacheCoherence-PT-none-LTLFireability-03
lola: time limit : 3574 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for ARMCacheCoherence-PT-none-LTLFireability-03
lola: result : false
lola: markings : 4
lola: fired transitions : 5
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open formulas

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ARMCacheCoherence-PT-none-LTLFireability-00: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-01: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-02: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-03: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-04: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-05: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-06: CONJ false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-07: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-08: CONJ false findpath
ARMCacheCoherence-PT-none-LTLFireability-09: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-10: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-11: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-12: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-13: AU false state space /ER
ARMCacheCoherence-PT-none-LTLFireability-14: LTL false LTL model checker
ARMCacheCoherence-PT-none-LTLFireability-15: LTL false LTL model checker


Time elapsed: 26 secs. Pages in use: 2

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ARMCacheCoherence-PT-none"
export BK_EXAMINATION="LTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-5348"
echo " Executing tool lola"
echo " Input is ARMCacheCoherence-PT-none, examination is LTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r006-oct2-167813593700004"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ARMCacheCoherence-PT-none.tgz
mv ARMCacheCoherence-PT-none execution
cd execution
if [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "UpperBounds" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] || [ "LTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "LTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "LTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "LTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property LTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "LTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' LTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "LTLFireability" = "ReachabilityDeadlock" ] || [ "LTLFireability" = "QuasiLiveness" ] || [ "LTLFireability" = "StableMarking" ] || [ "LTLFireability" = "Liveness" ] || [ "LTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME LTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;