Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2022-input.r255-tall-165303543000874.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2022-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-4028
Executing tool tapaal
Input is TwoPhaseLocking-PT-nC10000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r255-tall-165303543000874
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 248K
-rw-r--r-- 1 mcc users 8.6K Apr 30 10:43 CTLCardinality.txt
-rw-r--r-- 1 mcc users 89K Apr 30 10:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 5.4K Apr 30 10:41 CTLFireability.txt
-rw-r--r-- 1 mcc users 47K Apr 30 10:41 CTLFireability.xml
-rw-r--r-- 1 mcc users 6 May 10 09:34 equiv_col
-rw-r--r-- 1 mcc users 10 May 10 09:34 instance
-rw-r--r-- 1 mcc users 6 May 10 09:34 iscolored
-rw-r--r-- 1 mcc users 4.1K May 9 09:19 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 9 09:19 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 9 09:19 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 9 09:19 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.6K May 10 09:34 model.pnml
-rw-r--r-- 1 mcc users 1.8K May 9 09:19 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 9 09:19 UpperBounds.xml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC10000vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1653358112635

tapaal
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> tapaal --- TAPAAL v5
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590

*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya
MF=/home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)
/home/mcc/BenchKit/bin/verifypn -n -c -q 718 -l 29 -d 299 -z 4 -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
CPN OverApproximation is only usable on colored models
Time left: 3590
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3590 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING STRUCTURAL_REDUCTION QUERY_REDUCTION SAT_SMT LP_APPROX
Query index 1 was solved

Query is satisfied.
Solution found by parallel simplification (step 0)
Time left: 3590

---------------------------------------------------
Step 1: Parallel processing
---------------------------------------------------
Doing parallel verification of individual queries (15 in total)
Each query is verified by 4 parallel strategies for 299 seconds
------------------- QUERY 1 ----------------------
No solution found
Command terminated by signal 9
@@@119.40,8076136@@@
Command terminated by signal 9
@@@271.98,14245948@@@


Time left: 3288
------------------- QUERY 2 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.102752 on verification
@@@0.12,60228@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 2 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3288
------------------- QUERY 3 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.10737 on verification
@@@0.11,150280@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 3 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3287
------------------- QUERY 4 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 36.3249 on verification
@@@36.37,1553080@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 4 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3251
------------------- QUERY 5 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.137167 on verification
@@@0.14,64140@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 5 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3250
------------------- QUERY 6 ----------------------
No solution found
Command terminated by signal 9
@@@42.79,8266848@@@
Command terminated by signal 9
@@@93.90,8233508@@@
Command terminated by signal 9
@@@199.98,15585440@@@


Time left: 2949
------------------- QUERY 7 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.068001 on verification
@@@0.08,59144@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 7 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2949
------------------- QUERY 8 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.081536 on verification
@@@0.08,59588@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 8 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2948
------------------- QUERY 9 ----------------------
No solution found
Command terminated by signal 9
@@@94.50,8141212@@@
Command terminated by signal 9
@@@199.14,14345708@@@


Time left: 2647
------------------- QUERY 10 ----------------------
No solution found
Command terminated by signal 9
@@@81.98,7637320@@@
Command terminated by signal 9
@@@173.17,13874300@@@


Time left: 2346
------------------- QUERY 11 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.501052 on verification
@@@0.50,76988@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 11 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2345
------------------- QUERY 12 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 37.1727 on verification
@@@37.21,1547712@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 12 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2308
------------------- QUERY 13 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.082888 on verification
@@@0.08,59224@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 13 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2307
------------------- QUERY 14 ----------------------
Solution found by parallel processing (step 1)
Command terminated by signal 9
@@@26.68,4089084@@@
Command terminated by signal 9
@@@36.19,5432112@@@
Command terminated by signal 9
@@@53.81,8102792@@@


Query index 0 was solved
Query is satisfied.

Spent 186.948 on verification
@@@187.39,13743644@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 14 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2120
------------------- QUERY 15 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.114702 on verification
@@@0.11,61240@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.5EUU3gWGNi /home/mcc/BenchKit/bin/tmp/tmp.b8kKJFQzya --binary-query-io 1 -x 15 -n

FORMULA TwoPhaseLocking-PT-nC10000vD-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 2119
---------------------------------------------------
Step 2: Sequential processing
---------------------------------------------------
Remaining 4 queries are verified sequentially.
Each query is verified for a dynamic timeout (at least 598 seconds)
Time left: 2119
------------------- QUERY 1 ----------------------
Running query 1 for 598 seconds. Remaining: 4 queries and 2119 seconds
No solution found
Command terminated by signal 9
@@@137.14,8526024@@@
Command terminated by signal 9
@@@298.54,16146612@@@


Time left: 1821
------------------- QUERY 6 ----------------------
Running query 6 for 607 seconds. Remaining: 3 queries and 1821 seconds
No solution found
Command terminated by signal 9
@@@55.76,10907436@@@
Command terminated by signal 9
@@@183.48,16146460@@@


Time left: 1637
------------------- QUERY 9 ----------------------
Running query 9 for 818 seconds. Remaining: 2 queries and 1637 seconds
No solution found
Command terminated by signal 9
@@@104.61,9151048@@@
Command terminated by signal 9
@@@248.31,16145832@@@


Time left: 1388
------------------- QUERY 10 ----------------------
Running query 10 for 1388 seconds. Remaining: 1 queries and 1388 seconds
No solution found
Command terminated by signal 9
@@@88.29,8151984@@@
Command terminated by signal 9
@@@184.18,16145736@@@


Time left: 1204
Time left: 1204
---------------------------------------------------
Step 4: Random Parallel processing
---------------------------------------------------
Doing random parallel verification of individual queries (4 in total)
Each query is verified by 4 parallel strategies for 301 seconds
------------------- QUERY 1 ----------------------
No solution found
Command terminated by signal 9
@@@56.38,4620276@@@
Command terminated by signal 9
@@@83.50,5397836@@@
Command terminated by signal 9
@@@139.36,8151696@@@
Command terminated by signal 9
@@@279.78,16144476@@@


Time left: 924
------------------- QUERY 6 ----------------------
No solution found
Command terminated by signal 9
@@@21.13,4098660@@@
Command terminated by signal 9
@@@28.25,5428448@@@
Command terminated by signal 9
@@@42.21,8136372@@@
terminate called after throwing an instance of 'std::bad_alloc'
what(): std::bad_alloc
Command terminated by signal 6
@@@80.79,15651400@@@


Time left: 843
------------------- QUERY 9 ----------------------
No solution found
Command terminated by signal 9
@@@55.97,4154128@@@
Command terminated by signal 9
@@@76.85,5618016@@@
Command terminated by signal 9
@@@117.81,8180512@@@
Command terminated by signal 9
@@@218.94,16146548@@@


Time left: 623
------------------- QUERY 10 ----------------------
No solution found
Command terminated by signal 9
@@@37.75,4229832@@@
Command terminated by signal 9
@@@51.47,5551592@@@
Command terminated by signal 9
@@@80.27,8089912@@@
Command terminated by signal 9
@@@165.06,16144380@@@


Time left: 458
Time left: 458
---------------------------------------------------
Step 4: Random Parallel processing
---------------------------------------------------
Doing random parallel verification of individual queries (4 in total)
Each query is verified by 4 parallel strategies for 114 seconds
------------------- QUERY 1 ----------------------
No solution found
Command terminated by signal 9
@@@57.63,4301868@@@
Command terminated by signal 9
@@@83.67,5517796@@@


Time left: 341
------------------- QUERY 6 ----------------------
No solution found
Command terminated by signal 9
@@@20.27,4126568@@@
Command terminated by signal 9
@@@27.32,5503564@@@
Command terminated by signal 9
@@@41.83,8136004@@@
terminate called after throwing an instance of 'std::bad_alloc'
what(): std::bad_alloc
Command terminated by signal 6
@@@80.11,15651332@@@


Time left: 261
------------------- QUERY 9 ----------------------
No solution found
Command terminated by signal 9
@@@59.97,4484844@@@
Command terminated by signal 9
@@@80.45,6111776@@@


Time left: 144
------------------- QUERY 10 ----------------------
No solution found
Command terminated by signal 9
@@@42.84,4360920@@@
Command terminated by signal 9
@@@56.83,5672564@@@
Command terminated by signal 9
@@@85.06,8134428@@@


Time left: 27
Time left: 27
---------------------------------------------------
Step 4: Random Parallel processing
---------------------------------------------------
Doing random parallel verification of individual queries (4 in total)
Each query is verified by 4 parallel strategies for 6 seconds
------------------- QUERY 1 ----------------------
No solution found



Time left: 19
------------------- QUERY 6 ----------------------
No solution found



Time left: 11
------------------- QUERY 9 ----------------------
No solution found



Time left: 3
------------------- QUERY 10 ----------------------
No solution found



Time left: -1
Out of time, terminating!
terminated-with-cleanup

BK_STOP 1653361703588

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC10000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="tapaal"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool tapaal"
echo " Input is TwoPhaseLocking-PT-nC10000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r255-tall-165303543000874"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC10000vD.tgz
mv TwoPhaseLocking-PT-nC10000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;