Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2022-input.r255-tall-165303542800762.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2022-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
.....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool tapaal
Input is TwoPhaseLocking-PT-nC00050vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r255-tall-165303542800762
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 244K
-rw-r--r-- 1 mcc users 7.0K Apr 30 10:39 CTLCardinality.txt
-rw-r--r-- 1 mcc users 70K Apr 30 10:39 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.8K Apr 30 10:37 CTLFireability.txt
-rw-r--r-- 1 mcc users 65K Apr 30 10:37 CTLFireability.xml
-rw-r--r-- 1 mcc users 6 May 10 09:34 equiv_col
-rw-r--r-- 1 mcc users 10 May 10 09:34 instance
-rw-r--r-- 1 mcc users 6 May 10 09:34 iscolored
-rw-r--r-- 1 mcc users 4.2K May 9 09:17 LTLCardinality.txt
-rw-r--r-- 1 mcc users 27K May 9 09:17 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 9 09:18 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 9 09:18 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.6K May 10 09:34 model.pnml
-rw-r--r-- 1 mcc users 1.8K May 9 09:18 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K May 9 09:18 UpperBounds.xml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC00050vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1653339645697

tapaal
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> tapaal --- TAPAAL v5
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590

*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM
MF=/home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)
/home/mcc/BenchKit/bin/verifypn -n -c -q 718 -l 29 -d 299 -z 4 -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
CPN OverApproximation is only usable on colored models
Time left: 3590
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3590 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml

Time left: 3590

---------------------------------------------------
Step 1: Parallel processing
---------------------------------------------------
Doing parallel verification of individual queries (16 in total)
Each query is verified by 4 parallel strategies for 299 seconds
------------------- QUERY 1 ----------------------
Solution found by parallel processing (step 1)
Query index 0 was solved

Query is NOT satisfied.

Spent 0.002993 on verification
@@@0.00,7088@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 1 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING STRUCTURAL_REDUCTION QUERY_REDUCTION SAT_SMT EXPLICIT STATE_COMPRESSION STUBBORN_SETS
Time left: 3589
------------------- QUERY 2 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 1.10377 on verification
@@@1.12,116976@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 2 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3588
------------------- QUERY 3 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.065103 on verification
@@@0.07,59352@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 3 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3588
------------------- QUERY 4 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.048389 on verification
@@@0.05,59464@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 4 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3587
------------------- QUERY 5 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.060299 on verification
@@@0.06,59344@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 5 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3587
------------------- QUERY 6 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.047811 on verification
@@@0.05,59224@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 6 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3587
------------------- QUERY 7 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.072146 on verification
@@@0.07,59332@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BestFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 7 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3587
------------------- QUERY 8 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.052904 on verification
@@@0.05,59260@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 8 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3586
------------------- QUERY 9 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 1.93723 on verification


Query index 0 was solved
Query is NOT satisfied.

Spent 1.92268 on verification
@@@1.92,161752@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 9 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3584
------------------- QUERY 10 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.192509 on verification
@@@0.19,63172@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 10 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3584
------------------- QUERY 11 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 4.931 on verification
@@@4.94,345832@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 11 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3579
------------------- QUERY 12 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.051877 on verification
@@@0.05,59396@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 12 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3578
------------------- QUERY 13 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.053765 on verification
@@@0.05,59428@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 13 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3578
------------------- QUERY 14 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.052438 on verification
@@@0.05,59308@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 14 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3578
------------------- QUERY 15 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.054529 on verification
@@@0.05,59256@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 15 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3577
------------------- QUERY 16 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.073543 on verification
@@@0.07,59308@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.XWBjaGU6up /home/mcc/BenchKit/bin/tmp/tmp.oP6N1KEwrM --binary-query-io 1 -x 16 -n

FORMULA TwoPhaseLocking-PT-nC00050vD-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3577
All queries are solved
Time left: 3577
terminated-with-cleanup

BK_STOP 1653339658339

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC00050vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="tapaal"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool tapaal"
echo " Input is TwoPhaseLocking-PT-nC00050vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r255-tall-165303542800762"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC00050vD.tgz
mv TwoPhaseLocking-PT-nC00050vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;