Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2022-input.r003-tajo-165245682700258.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2022-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool tapaal
Input is AirplaneLD-PT-0050, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r003-tajo-165245682700258
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 980K
-rw-r--r-- 1 mcc users 46K Apr 29 20:52 CTLCardinality.txt
-rw-r--r-- 1 mcc users 222K Apr 29 20:52 CTLCardinality.xml
-rw-r--r-- 1 mcc users 29K Apr 29 20:50 CTLFireability.txt
-rw-r--r-- 1 mcc users 192K Apr 29 20:50 CTLFireability.xml
-rw-r--r-- 1 mcc users 5 May 10 09:33 equiv_col
-rw-r--r-- 1 mcc users 4.2K May 10 09:33 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.5K May 10 09:33 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 5 May 10 09:33 instance
-rw-r--r-- 1 mcc users 6 May 10 09:33 iscolored
-rw-r--r-- 1 mcc users 32K May 9 07:01 LTLCardinality.txt
-rw-r--r-- 1 mcc users 96K May 9 07:01 LTLCardinality.xml
-rw-r--r-- 1 mcc users 14K May 9 07:01 LTLFireability.txt
-rw-r--r-- 1 mcc users 65K May 9 07:01 LTLFireability.xml
-rw-r--r-- 1 mcc users 219K May 10 09:33 model.pnml
-rw-r--r-- 1 mcc users 6.3K May 9 07:01 UpperBounds.txt
-rw-r--r-- 1 mcc users 13K May 9 07:01 UpperBounds.xml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-00
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-01
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-02
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-03
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-04
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-05
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-06
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-07
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-08
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-09
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-10
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-11
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-12
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-13
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-14
FORMULA_NAME AirplaneLD-PT-0050-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1652550390888

tapaal
Got BK_BIN_PATH=/home/mcc/BenchKit/bin/
---> tapaal --- TAPAAL v5
Setting MODEL_PATH=.
Setting VERIFYPN=/home/mcc/BenchKit/bin/verifypn
Got BK_TIME_CONFINEMENT=3600
Setting TEMPDIR=/home/mcc/BenchKit/bin/tmp
Got BK_MEMORY_CONFINEMENT=16384
Limiting to 16265216 kB
Total timeout: 3590
Time left: 3590

*************************************
* TAPAAL verifying CTLFireability *
*************************************
TEMPDIR=/home/mcc/BenchKit/bin/tmp
QF=/home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa
MF=/home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE
Time left: 3590
---------------------------------------------------
Step -1: Stripping Colors
---------------------------------------------------
Verifying stripped models (16 in total)
/home/mcc/BenchKit/bin/verifypn -n -c -q 718 -l 29 -d 299 -z 4 -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml
CPN OverApproximation is only usable on colored models
Time left: 3589
---------------------------------------------------
Step 0: Parallel Simplification
---------------------------------------------------
Doing parallel simplification (16 in total)
Total simplification timout is 718 -- reduction timeout is 299
timeout 3589 /home/mcc/BenchKit/bin/verifypn -n -q 718 -l 29 -d 299 -z 4 -s OverApprox --binary-query-io 2 --write-simplified /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --write-reduced /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE -x 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 ./model.pnml ./CTLFireability.xml

Time left: 3588

---------------------------------------------------
Step 1: Parallel processing
---------------------------------------------------
Doing parallel verification of individual queries (16 in total)
Each query is verified by 4 parallel strategies for 299 seconds
------------------- QUERY 1 ----------------------
Solution found by parallel processing (step 1)
Search strategy option was ignored as the TAR engine is called.
Query index 0 was solved

Query is satisfied.


Solved using Trace Abstraction Refinement

Spent 0.002108 on verification
@@@0.01,6632@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 1 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-04 TRUE TECHNIQUES COLLATERAL_PROCESSING STRUCTURAL_REDUCTION QUERY_REDUCTION SAT_SMT TRACE_ABSTRACTION_REFINEMENT
Time left: 3588
------------------- QUERY 2 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.117319 on verification
@@@0.13,60412@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 2 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3587
------------------- QUERY 3 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 56.9209 on verification
@@@56.94,826792@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 3 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3530
------------------- QUERY 4 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.52465 on verification
@@@0.53,64064@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 4 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3529
------------------- QUERY 5 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 2.8561 on verification
@@@2.87,127288@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 5 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3526
------------------- QUERY 6 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.127823 on verification
@@@0.15,60384@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 6 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3526
------------------- QUERY 7 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.052395 on verification
@@@0.06,60464@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 7 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3526
------------------- QUERY 8 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 22.6015 on verification
@@@22.63,742728@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 8 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3503
------------------- QUERY 9 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.088807 on verification
@@@0.10,60424@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 9 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3503
------------------- QUERY 10 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 0.058657 on verification
@@@0.08,60380@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ DFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 10 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3502
------------------- QUERY 11 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 1.0002 on verification
@@@1.01,101808@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -s\ BFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 11 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3501
------------------- QUERY 12 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is satisfied.

Spent 21.4723 on verification
@@@21.50,745680@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 12 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3479
------------------- QUERY 13 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 0.114761 on verification
@@@0.12,59908@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 13 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3479
------------------- QUERY 14 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 27.5218 on verification
@@@27.55,579572@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 14 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3451
------------------- QUERY 15 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 23.0865 on verification
@@@23.12,650088@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 15 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3428
------------------- QUERY 16 ----------------------
Solution found by parallel processing (step 1)


Query index 0 was solved
Query is NOT satisfied.

Spent 13.6298 on verification
@@@13.65,330996@@@
parallel: This job succeeded:
eval /usr/bin/time -f "@@@%e,%M@@@" /home/mcc/BenchKit/bin/verifypn -n -tar\ -s\ RDFS\ -q\ 0\ -l\ 0\ -d\ 119 /home/mcc/BenchKit/bin/tmp/tmp.lovrQkrmwE /home/mcc/BenchKit/bin/tmp/tmp.CqQ71tRwZa --binary-query-io 1 -x 16 -n

FORMULA AirplaneLD-PT-0050-CTLFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT STATE_COMPRESSION SAT_SMT STUBBORN_SETS CTL_CZERO
Time left: 3414
All queries are solved
Time left: 3414
terminated-with-cleanup

BK_STOP 1652550566738

--------------------
content from stderr:

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="AirplaneLD-PT-0050"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="tapaal"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool tapaal"
echo " Input is AirplaneLD-PT-0050, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r003-tajo-165245682700258"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/AirplaneLD-PT-0050.tgz
mv AirplaneLD-PT-0050 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;