fond

jQuery Multi Level CSS Menu Css3Menu.com

Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r308-tall-162132104700378
Last Updated
Jun 28, 2021

About the Execution of LoLA for TwoPhaseLocking-PT-nC10000vN

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
4630.163 120227.00 110128.00 287.30 F?F????TT???T?TF normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r308-tall-162132104700378.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is TwoPhaseLocking-PT-nC10000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r308-tall-162132104700378
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 340K
-rw-r--r-- 1 mcc users 14K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 115K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.1K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.9K May 12 08:04 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K May 12 08:04 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.2K May 12 08:04 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 12 08:04 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 4.0K May 12 04:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 21K May 12 04:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.9K May 11 18:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K May 11 18:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 12 04:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 12 04:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 10 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 4.6K May 12 08:13 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC10000vN-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1621378476127

starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC10000vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC10000vN-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621378596354

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 10 (type EXCL) for 9 TwoPhaseLocking-PT-nC10000vN-CTLFireability-03
lola: time limit : 120 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:665
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:734
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 69 (type FNDP) for 54 TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type EQUN) for 54 TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 72 (type SRCH) for 54 TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 72 (type SRCH) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 74 (type FNDP) for 54 TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/CTLFireability-70.sara.

lola: FINISHED task # 70 (type EQUN) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: result : false
lola: CANCELED task # 69 (type FNDP) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-14 (obsolete)
lola: CANCELED task # 74 (type FNDP) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-14 (obsolete)
lola: FINISHED task # 74 (type FNDP) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: result : unknown
lola: fired transitions : 16468
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 69 (type FNDP) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-14
lola: result : unknown
lola: fired transitions : 44251
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 5/200 14/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-03 3170327 m, 634065 m/sec, 9482084 t fired, .

Time elapsed: 5 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
10 CTL EXCL 10/200 26/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-03 6126302 m, 591195 m/sec, 18357635 t fired, .

Time elapsed: 10 secs. Pages in use: 26
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 10 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 15 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 62 (type EXCL) for 61 TwoPhaseLocking-PT-nC10000vN-CTLFireability-15
lola: time limit : 210 sec
lola: memory limit: 32 pages
lola: FINISHED task # 62 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-15
lola: result : false
lola: markings : 20004
lola: fired transitions : 40005
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 44 TwoPhaseLocking-PT-nC10000vN-CTLFireability-12
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 47 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-12
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 TwoPhaseLocking-PT-nC10000vN-CTLFireability-10
lola: time limit : 239 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 5/239 10/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-10 2257939 m, 451587 m/sec, 8574484 t fired, .

Time elapsed: 20 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 10/239 19/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-10 4387392 m, 425890 m/sec, 16629159 t fired, .

Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
39 CTL EXCL 15/239 27/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-10 6444779 m, 411477 m/sec, 24404002 t fired, .

Time elapsed: 30 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 39 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 35 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 31 (type EXCL) for 28 TwoPhaseLocking-PT-nC10000vN-CTLFireability-08
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: FINISHED task # 31 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-08
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 26 (type EXCL) for 25 TwoPhaseLocking-PT-nC10000vN-CTLFireability-07
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 26 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-07
lola: result : true
lola: markings : 20006
lola: fired transitions : 85018
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 23 (type EXCL) for 22 TwoPhaseLocking-PT-nC10000vN-CTLFireability-06
lola: time limit : 297 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/297 7/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-06 1718557 m, 343711 m/sec, 7328082 t fired, .

Time elapsed: 40 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/297 14/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-06 3402232 m, 336735 m/sec, 14915894 t fired, .

Time elapsed: 45 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 15/297 21/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-06 5031467 m, 325847 m/sec, 22374886 t fired, .

Time elapsed: 50 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 20/297 27/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-06 6561668 m, 306040 m/sec, 29522850 t fired, .

Time elapsed: 55 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 60 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 18 (type EXCL) for 15 TwoPhaseLocking-PT-nC10000vN-CTLFireability-05
lola: time limit : 321 sec
lola: memory limit: 32 pages
lola: FINISHED task # 18 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-05
lola: result : false
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 13 (type EXCL) for 12 TwoPhaseLocking-PT-nC10000vN-CTLFireability-04
lola: time limit : 354 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
13 CTL EXCL 5/354 19/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-04 4386420 m, 877284 m/sec, 6567744 t fired, .

Time elapsed: 65 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 13 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 70 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC10000vN-CTLFireability-02
lola: time limit : 392 sec
lola: memory limit: 32 pages
lola: FINISHED task # 7 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-02
lola: result : false
lola: markings : 30003
lola: fired transitions : 50003
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC10000vN-CTLFireability-00
lola: time limit : 441 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-00
lola: result : false
lola: markings : 10001
lola: fired transitions : 15001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 67 (type EXCL) for 28 TwoPhaseLocking-PT-nC10000vN-CTLFireability-08
lola: time limit : 504 sec
lola: memory limit: 32 pages
lola: FINISHED task # 67 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-08
lola: result : false
lola: markings : 60003
lola: fired transitions : 60003
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 65 (type EXCL) for 44 TwoPhaseLocking-PT-nC10000vN-CTLFireability-12
lola: time limit : 588 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-12
lola: result : false
lola: markings : 50001
lola: fired transitions : 60000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC10000vN-CTLFireability-01
lola: time limit : 706 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
4 CTL EXCL 5/706 19/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-01 4454301 m, 890860 m/sec, 8882621 t fired, .

Time elapsed: 75 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 80 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 64 (type EXCL) for 35 TwoPhaseLocking-PT-nC10000vN-CTLFireability-09
lola: time limit : 880 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 LTL EXCL 5/880 30/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-09 4515004 m, 903000 m/sec, 6765385 t fired, .

Time elapsed: 85 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 64 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 1 0 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 15 TwoPhaseLocking-PT-nC10000vN-CTLFireability-05
lola: time limit : 1170 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 0 1 0 3 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/1170 19/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-05 4305960 m, 861192 m/sec, 8572986 t fired, .

Time elapsed: 95 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 20 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 0 0 0 3 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 100 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 42 (type EXCL) for 41 TwoPhaseLocking-PT-nC10000vN-CTLFireability-11
lola: time limit : 1750 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 0 0 0 3 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
42 CTL EXCL 5/1750 18/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-11 4333170 m, 866634 m/sec, 8639758 t fired, .

Time elapsed: 105 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 42 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 0 0 0 3 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 110 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 52 (type EXCL) for 51 TwoPhaseLocking-PT-nC10000vN-CTLFireability-13
lola: time limit : 3490 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 0 0 0 3 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
52 CTL EXCL 5/3490 18/32 TwoPhaseLocking-PT-nC10000vN-CTLFireability-13 4226458 m, 845291 m/sec, 8426110 t fired, .

Time elapsed: 115 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 52 (type EXCL) for TwoPhaseLocking-PT-nC10000vN-CTLFireability-13 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ 0 0 0 0 3 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 120 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC10000vN-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-01: AFAG unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-04: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-05: DISJ unknown DISJ
TwoPhaseLocking-PT-nC10000vN-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-07: CTL true CTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-08: DISJ true LTL model checker
TwoPhaseLocking-PT-nC10000vN-CTLFireability-09: SP ACTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-10: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-11: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-12: DISJ true state space /EFEG
TwoPhaseLocking-PT-nC10000vN-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC10000vN-CTLFireability-14: DISJ true state equation
TwoPhaseLocking-PT-nC10000vN-CTLFireability-15: CTL false CTL model checker


Time elapsed: 120 secs. Pages in use: 32

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC10000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC10000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-162132104700378"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC10000vN.tgz
mv TwoPhaseLocking-PT-nC10000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;