About the Execution of LoLA for TwoPhaseLocking-PT-nC02000vD
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 1703.915 | 51682.00 | 55001.00 | 94.90 | FTT?FTFTT?TTTFTF | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r308-tall-162132104600338.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is TwoPhaseLocking-PT-nC02000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r308-tall-162132104600338
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 300K
-rw-r--r-- 1 mcc users 11K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 87K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 12 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 12 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 12 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 17K May 12 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 3.8K May 12 04:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K May 12 04:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.4K May 11 18:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K May 11 18:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 12 04:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K May 12 04:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 10 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 4.6K May 12 08:13 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC02000vD-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1621374687292
starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC02000vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TwoPhaseLocking-PT-nC02000vD-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621374738974
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: LAUNCH task # 27 (type EXCL) for 26 TwoPhaseLocking-PT-nC02000vD-CTLFireability-06
lola: time limit : 112 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 27 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-06
lola: result : false
lola: markings : 5000
lola: fired transitions : 12001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 48 (type EXCL) for 45 TwoPhaseLocking-PT-nC02000vD-CTLFireability-11
lola: time limit : 133 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type FNDP) for 19 TwoPhaseLocking-PT-nC02000vD-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 65 (type EQUN) for 19 TwoPhaseLocking-PT-nC02000vD-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 67 (type SRCH) for 19 TwoPhaseLocking-PT-nC02000vD-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 48 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-11
lola: result : true
lola: markings : 4005
lola: fired transitions : 12014
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 67 (type SRCH) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-05
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 17 (type EXCL) for 16 TwoPhaseLocking-PT-nC02000vD-CTLFireability-04
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 73 (type FNDP) for 61 TwoPhaseLocking-PT-nC02000vD-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
sara: try reading problem file /home/mcc/execution/CTLFireability-65.sara.
lola: FINISHED task # 17 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-04
lola: result : false
lola: markings : 10996
lola: fired transitions : 32993
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 43 (type EXCL) for 42 TwoPhaseLocking-PT-nC02000vD-CTLFireability-10
lola: time limit : 225 sec
lola: memory limit: 32 pages
lola: FINISHED task # 43 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-10
lola: result : true
lola: markings : 2001
lola: fired transitions : 3002
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 40 (type EXCL) for 39 TwoPhaseLocking-PT-nC02000vD-CTLFireability-09
lola: time limit : 240 sec
lola: memory limit: 32 pages
lola: FINISHED task # 65 (type EQUN) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-05
lola: result : true
lola: CANCELED task # 64 (type FNDP) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-05 (obsolete)
lola: LAUNCH task # 68 (type FNDP) for 52 TwoPhaseLocking-PT-nC02000vD-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type EQUN) for 52 TwoPhaseLocking-PT-nC02000vD-CTLFireability-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type FNDP) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-05
lola: result : unknown
lola: fired transitions : 498118
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 68 (type FNDP) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-12
lola: result : true
lola: fired transitions : 1999
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 70 (type EQUN) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-12 (obsolete)
lola: LAUNCH task # 74 (type EQUN) for 61 TwoPhaseLocking-PT-nC02000vD-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 76 (type SRCH) for 61 TwoPhaseLocking-PT-nC02000vD-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 70 (type EQUN) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-12
lola: result : unknown
lola: FINISHED task # 76 (type SRCH) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-15
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-74.sara.
lola: FINISHED task # 74 (type EQUN) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-15
lola: result : true
lola: CANCELED task # 73 (type FNDP) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-15 (obsolete)
lola: FINISHED task # 73 (type FNDP) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-15
lola: result : unknown
lola: fired transitions : 4371183
lola: tried executions : 6
lola: time used : 1.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 5/327 8/32 TwoPhaseLocking-PT-nC02000vD-CTLFireability-09 1762969 m, 352593 m/sec, 8065416 t fired, .
Time elapsed: 5 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 10/327 14/32 TwoPhaseLocking-PT-nC02000vD-CTLFireability-09 3459647 m, 339335 m/sec, 16124435 t fired, .
Time elapsed: 10 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 15/327 21/32 TwoPhaseLocking-PT-nC02000vD-CTLFireability-09 5028263 m, 313723 m/sec, 23726495 t fired, .
Time elapsed: 15 secs. Pages in use: 21
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
40 CTL EXCL 20/327 27/32 TwoPhaseLocking-PT-nC02000vD-CTLFireability-09 6529890 m, 300325 m/sec, 31035650 t fired, .
Time elapsed: 20 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 40 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 25 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 37 (type EXCL) for 36 TwoPhaseLocking-PT-nC02000vD-CTLFireability-08
lola: time limit : 357 sec
lola: memory limit: 32 pages
lola: FINISHED task # 37 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-08
lola: result : true
lola: markings : 4003
lola: fired transitions : 8006
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 14 (type EXCL) for 13 TwoPhaseLocking-PT-nC02000vD-CTLFireability-03
lola: time limit : 397 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/397 8/32 TwoPhaseLocking-PT-nC02000vD-CTLFireability-03 1813213 m, 362642 m/sec, 8306135 t fired, .
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TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/397 15/32 TwoPhaseLocking-PT-nC02000vD-CTLFireability-03 3503965 m, 338150 m/sec, 16331153 t fired, .
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TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 15/397 21/32 TwoPhaseLocking-PT-nC02000vD-CTLFireability-03 5062994 m, 311805 m/sec, 23894500 t fired, .
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TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 20/397 27/32 TwoPhaseLocking-PT-nC02000vD-CTLFireability-03 6553683 m, 298137 m/sec, 31153123 t fired, .
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lola: CANCELED task # 14 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-03 (memory limit exceeded)
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TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
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lola: LAUNCH task # 11 (type EXCL) for 6 TwoPhaseLocking-PT-nC02000vD-CTLFireability-02
lola: time limit : 443 sec
lola: memory limit: 32 pages
lola: FINISHED task # 11 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-02
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 9 (type EXCL) for 6 TwoPhaseLocking-PT-nC02000vD-CTLFireability-02
lola: time limit : 507 sec
lola: memory limit: 32 pages
lola: FINISHED task # 9 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-02
lola: result : true
lola: markings : 4001
lola: fired transitions : 4000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 TwoPhaseLocking-PT-nC02000vD-CTLFireability-01
lola: time limit : 591 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-01
lola: result : true
lola: markings : 4004
lola: fired transitions : 16011
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC02000vD-CTLFireability-00
lola: time limit : 710 sec
lola: memory limit: 32 pages
lola: FINISHED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-00
lola: result : false
lola: markings : 4001
lola: fired transitions : 4001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 56 (type EXCL) for 55 TwoPhaseLocking-PT-nC02000vD-CTLFireability-13
lola: time limit : 887 sec
lola: memory limit: 32 pages
lola: FINISHED task # 56 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-13
lola: result : false
lola: markings : 1001
lola: fired transitions : 1000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 34 (type EXCL) for 29 TwoPhaseLocking-PT-nC02000vD-CTLFireability-07
lola: time limit : 1183 sec
lola: memory limit: 32 pages
lola: FINISHED task # 34 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-07
lola: result : true
lola: markings : 2006996
lola: fired transitions : 3007994
lola: time used : 1.000000
lola: memory pages used : 8
lola: LAUNCH task # 59 (type EXCL) for 58 TwoPhaseLocking-PT-nC02000vD-CTLFireability-14
lola: time limit : 3549 sec
lola: memory limit: 32 pages
lola: FINISHED task # 59 (type EXCL) for TwoPhaseLocking-PT-nC02000vD-CTLFireability-14
lola: result : true
lola: markings : 4001
lola: fired transitions : 4000
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC02000vD-CTLFireability-00: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-01: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-02: CONJ true CONJ
TwoPhaseLocking-PT-nC02000vD-CTLFireability-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-05: DISJ true state equation
TwoPhaseLocking-PT-nC02000vD-CTLFireability-06: CTL false CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-07: DISJ true tscc_search
TwoPhaseLocking-PT-nC02000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-09: CTL unknown AGGR
TwoPhaseLocking-PT-nC02000vD-CTLFireability-10: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-11: DISJ true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-12: EF true findpath
TwoPhaseLocking-PT-nC02000vD-CTLFireability-13: EG false state space / EG
TwoPhaseLocking-PT-nC02000vD-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC02000vD-CTLFireability-15: AG false state equation
Time elapsed: 51 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC02000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC02000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-162132104600338"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC02000vD.tgz
mv TwoPhaseLocking-PT-nC02000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;