Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r308-tall-162132104600330.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is TwoPhaseLocking-PT-nC01000vN, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r308-tall-162132104600330
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 300K
-rw-r--r-- 1 mcc users 12K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 94K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.6K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 53K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.3K May 12 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 22K May 12 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.0K May 12 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 14K May 12 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 3.6K May 12 04:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K May 12 04:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.8K May 11 18:05 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K May 11 18:05 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 12 04:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 12 04:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 10 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 4.6K May 12 08:13 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC01000vN-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1621371633134

starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC01000vN
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vN-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621371938472

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: LAUNCH task # 7 (type EXCL) for 6 TwoPhaseLocking-PT-nC01000vN-CTLFireability-02
lola: time limit : 124 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 61 (type FNDP) for 31 TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 31 TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type SRCH) for 31 TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 64 (type SRCH) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 61 (type FNDP) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-09 (obsolete)
lola: CANCELED task # 62 (type EQUN) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-09 (obsolete)
sara: try reading problem file /home/mcc/execution/CTLFireability-62.sara.

lola: FINISHED task # 61 (type FNDP) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: FINISHED task # 62 (type EQUN) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-09
lola: result : true
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:663
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:674
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: DISJ 0 1 0 0 6 0 0 5
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 5/211 10/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-02 2405428 m, 481085 m/sec, 8852919 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: EFEG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: DISJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: DISJ 0 1 0 0 6 0 0 5
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 10/211 17/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-02 4022387 m, 323391 m/sec, 15486335 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

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7 CTL EXCL 15/211 22/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-02 5413345 m, 278191 m/sec, 21261755 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 1 0 1 0 0 0

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58 CTL EXCL 5/223 10/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-15 2432533 m, 486506 m/sec, 8965474 t fired, .

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58 CTL EXCL 10/223 17/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-15 4066112 m, 326715 m/sec, 15668614 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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58 CTL EXCL 15/223 22/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-15 5418126 m, 270402 m/sec, 21282515 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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58 CTL EXCL 20/223 28/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-15 6766432 m, 269661 m/sec, 26909230 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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52 CTL EXCL 15/253 21/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-13 5132827 m, 278806 m/sec, 20099358 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: DISJ 0 1 0 0 6 0 0 5
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
12 CTL EXCL 10/480 16/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-03 3767185 m, 295983 m/sec, 14441416 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: DISJ 0 0 1 0 3 0 0 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: DISJ 0 1 0 0 6 0 0 5
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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12 CTL EXCL 15/480 21/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-03 5160352 m, 278633 m/sec, 20211580 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: DISJ 0 1 0 0 6 0 0 5
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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12 CTL EXCL 20/480 27/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-03 6493925 m, 266714 m/sec, 25766000 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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12 CTL EXCL 25/480 32/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-03 7810476 m, 263310 m/sec, 31276983 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: DISJ 0 0 0 0 3 0 1 0
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: DISJ 0 1 0 0 6 0 0 5
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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lola: FINISHED task # 43 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-10
lola: result : false
lola: markings : 501
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lola: result : true
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: FINISHED task # 4 (type EXCL) for TwoPhaseLocking-PT-nC01000vN-CTLFireability-01
lola: result : false
lola: markings : 2004
lola: fired transitions : 6011
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CTL false CTL model checker
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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20 CTL EXCL 10/3325 14/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-05 3311990 m, 268757 m/sec, 15873202 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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20 CTL EXCL 15/3325 19/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-05 4555287 m, 248659 m/sec, 22248131 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG false state space / EG
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TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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20 CTL EXCL 20/3325 24/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-05 5744850 m, 237912 m/sec, 28384281 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

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20 CTL EXCL 25/3325 28/32 TwoPhaseLocking-PT-nC01000vN-CTLFireability-05 6923731 m, 235776 m/sec, 34492112 t fired, .

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vN-CTLFireability-00: EFEG false state space /EFEG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-01: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-02: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-03: DISJ unknown DISJ
TwoPhaseLocking-PT-nC01000vN-CTLFireability-04: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-06: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-07: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-08: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-09: DISJ false DISJ
TwoPhaseLocking-PT-nC01000vN-CTLFireability-10: EG false state space / EG
TwoPhaseLocking-PT-nC01000vN-CTLFireability-11: SP ECTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-12: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-13: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vN-CTLFireability-14: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vN-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC01000vN"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC01000vN, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-162132104600330"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC01000vN.tgz
mv TwoPhaseLocking-PT-nC01000vN execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;