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Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r308-tall-162132104600322
Last Updated
Jun 28, 2021

About the Execution of LoLA for TwoPhaseLocking-PT-nC01000vD

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3294.168 135194.00 132756.00 294.70 ?TF?F?TFTFFFTFTT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r308-tall-162132104600322.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is TwoPhaseLocking-PT-nC01000vD, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r308-tall-162132104600322
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 308K
-rw-r--r-- 1 mcc users 12K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 96K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.6K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 62K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 3.6K May 12 08:03 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K May 12 08:03 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K May 12 08:03 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K May 12 08:03 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 3.5K May 12 04:14 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K May 12 04:14 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 2.7K May 11 18:04 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K May 11 18:04 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K May 12 04:43 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K May 12 04:43 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 10 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 4.6K May 12 08:13 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-00
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-02
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-03
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-04
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-05
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-06
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-07
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-08
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-09
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-10
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-11
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-12
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-13
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
FORMULA_NAME TwoPhaseLocking-PT-nC01000vD-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1621371414149

starting LoLA
BK_INPUT TwoPhaseLocking-PT-nC01000vD
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-14 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-06 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TwoPhaseLocking-PT-nC01000vD-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621371549343

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 1 (type EXCL) for 0 TwoPhaseLocking-PT-nC01000vD-CTLFireability-00
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 63 (type FNDP) for 3 TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 64 (type EQUN) for 3 TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 66 (type SRCH) for 3 TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 66 (type SRCH) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 60 (type FNDP) for 54 TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/CTLFireability-64.sara.

lola: FINISHED task # 64 (type EQUN) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
lola: result : true
lola: CANCELED task # 63 (type FNDP) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-01 (obsolete)
lola: LAUNCH task # 61 (type EQUN) for 54 TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 67 (type SRCH) for 54 TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type FNDP) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-01
lola: result : unknown
lola: fired transitions : 334218
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 67 (type SRCH) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
sara: try reading problem file /home/mcc/execution/CTLFireability-61.sara.

lola: FINISHED task # 61 (type EQUN) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
lola: result : true
lola: CANCELED task # 60 (type FNDP) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-14 (obsolete)
lola: FINISHED task # 60 (type FNDP) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-14
lola: result : unknown
lola: fired transitions : 1348470
lola: tried executions : 3
lola: time used : 0.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/240 7/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-00 1695874 m, 339174 m/sec, 7911176 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/240 13/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-00 3227318 m, 306288 m/sec, 15373674 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 15/240 19/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-00 4574275 m, 269391 m/sec, 22017697 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 20/240 24/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-00 5891147 m, 263374 m/sec, 28565865 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 25/240 29/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-00 7200181 m, 261806 m/sec, 35068314 t fired, .

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lola: CANCELED task # 1 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ 0 2 0 0 2 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 58 (type EXCL) for 57 TwoPhaseLocking-PT-nC01000vD-CTLFireability-15
lola: time limit : 255 sec
lola: memory limit: 32 pages
lola: FINISHED task # 58 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-15
lola: result : true
lola: markings : 6991
lola: fired transitions : 18000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 52 (type EXCL) for 47 TwoPhaseLocking-PT-nC01000vD-CTLFireability-13
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-13
lola: result : false
lola: markings : 2002
lola: fired transitions : 4001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 45 (type EXCL) for 44 TwoPhaseLocking-PT-nC01000vD-CTLFireability-12
lola: time limit : 324 sec
lola: memory limit: 32 pages
lola: FINISHED task # 45 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-12
lola: result : true
lola: markings : 500506
lola: fired transitions : 630756
lola: time used : 0.000000
lola: memory pages used : 3
lola: LAUNCH task # 42 (type EXCL) for 41 TwoPhaseLocking-PT-nC01000vD-CTLFireability-11
lola: time limit : 357 sec
lola: memory limit: 32 pages
lola: FINISHED task # 42 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-11
lola: result : false
lola: markings : 2001
lola: fired transitions : 4503
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 33 (type EXCL) for 32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-08
lola: time limit : 396 sec
lola: memory limit: 32 pages
lola: FINISHED task # 33 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-08
lola: result : true
lola: markings : 2535
lola: fired transitions : 2546
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 30 (type EXCL) for 29 TwoPhaseLocking-PT-nC01000vD-CTLFireability-07
lola: time limit : 446 sec
lola: memory limit: 32 pages
lola: FINISHED task # 30 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-07
lola: result : false
lola: markings : 2000
lola: fired transitions : 6997
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 27 (type EXCL) for 26 TwoPhaseLocking-PT-nC01000vD-CTLFireability-06
lola: time limit : 510 sec
lola: memory limit: 32 pages
lola: FINISHED task # 27 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-06
lola: result : true
lola: markings : 2004
lola: fired transitions : 8011
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 24 (type EXCL) for 23 TwoPhaseLocking-PT-nC01000vD-CTLFireability-05
lola: time limit : 595 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 5/595 10/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-05 2326599 m, 465319 m/sec, 8642878 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 10/595 18/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-05 4235772 m, 381834 m/sec, 16116998 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 15/595 25/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-05 5975852 m, 348016 m/sec, 23013343 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
24 CTL EXCL 20/595 31/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-05 7571871 m, 319203 m/sec, 29351198 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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18 CTL EXCL 5/886 3/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 651188 m, 130237 m/sec, 6795889 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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18 CTL EXCL 10/886 5/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 1225546 m, 114871 m/sec, 13687388 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

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18 CTL EXCL 15/886 8/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 1802788 m, 115448 m/sec, 20447996 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

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18 CTL EXCL 20/886 10/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 2351881 m, 109818 m/sec, 27158624 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

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18 CTL EXCL 25/886 12/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 2878742 m, 105372 m/sec, 33810698 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
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18 CTL EXCL 30/886 14/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 3370850 m, 98421 m/sec, 40363752 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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18 CTL EXCL 35/886 16/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 3861006 m, 98031 m/sec, 46892715 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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18 CTL EXCL 40/886 18/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 4348992 m, 97597 m/sec, 53412290 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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18 CTL EXCL 45/886 20/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 4809069 m, 92015 m/sec, 59868893 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

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18 CTL EXCL 50/886 22/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 5293446 m, 96875 m/sec, 66242661 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 55/886 24/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 5753289 m, 91968 m/sec, 72617905 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 60/886 26/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 6235090 m, 96360 m/sec, 78957049 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 65/886 27/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 6695914 m, 92164 m/sec, 85266592 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 70/886 29/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 7144537 m, 89724 m/sec, 91536363 t fired, .

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TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
18 CTL EXCL 75/886 31/32 TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 7592455 m, 89583 m/sec, 97833733 t fired, .

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lola: CANCELED task # 18 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: LAUNCH task # 15 (type EXCL) for 14 TwoPhaseLocking-PT-nC01000vD-CTLFireability-02
lola: time limit : 1155 sec
lola: memory limit: 32 pages
lola: FINISHED task # 15 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-02
lola: result : false
lola: markings : 2001
lola: fired transitions : 4001
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 39 (type EXCL) for 38 TwoPhaseLocking-PT-nC01000vD-CTLFireability-10
lola: time limit : 1732 sec
lola: memory limit: 32 pages
lola: FINISHED task # 39 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-10
lola: result : false
lola: markings : 1001
lola: fired transitions : 1000
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 36 (type EXCL) for 35 TwoPhaseLocking-PT-nC01000vD-CTLFireability-09
lola: time limit : 3465 sec
lola: memory limit: 32 pages
lola: FINISHED task # 36 (type EXCL) for TwoPhaseLocking-PT-nC01000vD-CTLFireability-09
lola: result : false
lola: markings : 2001
lola: fired transitions : 7995
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TwoPhaseLocking-PT-nC01000vD-CTLFireability-00: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vD-CTLFireability-01: DISJ true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-02: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-03: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vD-CTLFireability-04: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-05: CTL unknown AGGR
TwoPhaseLocking-PT-nC01000vD-CTLFireability-06: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-07: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-08: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-09: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-10: EG false state space / EG
TwoPhaseLocking-PT-nC01000vD-CTLFireability-11: CTL false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-12: CTL true CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-13: CONJ false CTL model checker
TwoPhaseLocking-PT-nC01000vD-CTLFireability-14: EF true state equation
TwoPhaseLocking-PT-nC01000vD-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TwoPhaseLocking-PT-nC01000vD"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is TwoPhaseLocking-PT-nC01000vD, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r308-tall-162132104600322"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TwoPhaseLocking-PT-nC01000vD.tgz
mv TwoPhaseLocking-PT-nC01000vD execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;