About the Execution of LoLA for MultiCrashLeafsetExtension-PT-S16C07
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16218.275 | 3600000.00 | 14125247.00 | 849.40 | FFFTFTFFFFF??TFT | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r289-tall-162124152700615.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is MultiCrashLeafsetExtension-PT-S16C07, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r289-tall-162124152700615
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 12M
-rw-r--r-- 1 mcc users 52K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 179K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 37K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 120K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 6.6K May 12 07:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 12 07:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K May 12 07:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 12 07:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 6.4K May 11 18:53 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 23K May 11 18:53 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 6.4K May 11 15:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 24K May 11 15:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 12 04:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 12 04:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 7 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 12M May 12 08:13 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME gen-ReachabilityFireability-00
FORMULA_NAME gen-ReachabilityFireability-01
FORMULA_NAME gen-ReachabilityFireability-02
FORMULA_NAME gen-ReachabilityFireability-03
FORMULA_NAME gen-ReachabilityFireability-04
FORMULA_NAME gen-ReachabilityFireability-05
FORMULA_NAME gen-ReachabilityFireability-06
FORMULA_NAME gen-ReachabilityFireability-07
FORMULA_NAME gen-ReachabilityFireability-08
FORMULA_NAME gen-ReachabilityFireability-09
FORMULA_NAME gen-ReachabilityFireability-10
FORMULA_NAME gen-ReachabilityFireability-11
FORMULA_NAME gen-ReachabilityFireability-12
FORMULA_NAME gen-ReachabilityFireability-13
FORMULA_NAME gen-ReachabilityFireability-14
FORMULA_NAME gen-ReachabilityFireability-15
=== Now, execution of the tool begins
BK_START 1621302729165
starting LoLA
BK_INPUT MultiCrashLeafsetExtension-PT-S16C07
BK_EXAMINATION: ReachabilityFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityFireability
FORMULA gen-ReachabilityFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-05 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-00: INITIAL 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-01: INITIAL 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-05: EF 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-06: INITIAL 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-07: AG 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-08: INITIAL 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-11: AG 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-12: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-13: EF 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-14: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 77 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 gen-ReachabilityFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 1 (type CNST) for gen-ReachabilityFireability-00
lola: result : false
lola: LAUNCH INITIAL
lola: LAUNCH task # 4 (type CNST) for 3 gen-ReachabilityFireability-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 4 (type CNST) for gen-ReachabilityFireability-01
lola: result : false
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 25 (type CNST) for 24 gen-ReachabilityFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 25 (type CNST) for gen-ReachabilityFireability-08
lola: result : false
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-06: INITIAL 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 82 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 19 (type CNST) for 18 gen-ReachabilityFireability-06
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 19 (type CNST) for gen-ReachabilityFireability-06
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 87 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 15 gen-ReachabilityFireability-05
lola: time limit : 292 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 15 gen-ReachabilityFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 15 gen-ReachabilityFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type SRCH) for 15 gen-ReachabilityFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-08: INITIAL false preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-05: EF 0 1 4 0 1 0 0 0
gen-ReachabilityFireability-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-13: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
48 EF FNDP 0/1169 0/5 gen-ReachabilityFireability-05 --
49 EF STEQ 0/1169 0/5 gen-ReachabilityFireability-05 sara not yet started (preprocessing).
51 EF SRCH 0/1754 1/5 gen-ReachabilityFireability-05 --
52 EF EXCL 0/292 1/32 gen-ReachabilityFireability-05 --
Time elapsed: 92 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-49.sara.
lola: FINISHED task # 48 (type FNDP) for gen-ReachabilityFireability-05
lola: result : true
lola: fired transitions : 2298
lola: tried executions : 46
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 49 (type EQUN) for gen-ReachabilityFireability-05 (obsolete)
lola: CANCELED task # 51 (type SRCH) for gen-ReachabilityFireability-05 (obsolete)
lola: CANCELED task # 52 (type EXCL) for gen-ReachabilityFireability-05 (obsolete)
lola: LAUNCH task # 59 (type EXCL) for 21 gen-ReachabilityFireability-07
lola: time limit : 318 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 21 gen-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 21 gen-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: LAUNCH task # 58 (type SRCH) for 21 gen-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 49 (type EQUN) for gen-ReachabilityFireability-05
lola: result : unknown
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-56.sara.
lola: FINISHED task # 55 (type FNDP) for gen-ReachabilityFireability-07
lola: result : true
lola: fired transitions : 19
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 56 (type EQUN) for gen-ReachabilityFireability-07 (obsolete)
lola: CANCELED task # 58 (type SRCH) for gen-ReachabilityFireability-07 (obsolete)
lola: CANCELED task # 59 (type EXCL) for gen-ReachabilityFireability-07 (obsolete)
lola: FINISHED task # 56 (type EQUN) for gen-ReachabilityFireability-07
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 66 (type EXCL) for 27 gen-ReachabilityFireability-09
lola: time limit : 350 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 62 (type FNDP) for 27 gen-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 63 (type EQUN) for 27 gen-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 65 (type SRCH) for 27 gen-ReachabilityFireability-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-63.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 65 (type SRCH) for gen-ReachabilityFireability-09
lola: result : true
lola: markings : 32
lola: fired transitions : 31
lola: time used : 1.000000
lola: memory pages used : 1
lola: CANCELED task # 62 (type FNDP) for gen-ReachabilityFireability-09 (obsolete)
lola: CANCELED task # 63 (type EQUN) for gen-ReachabilityFireability-09 (obsolete)
lola: CANCELED task # 66 (type EXCL) for gen-ReachabilityFireability-09 (obsolete)
lola: LAUNCH task # 85 (type EXCL) for 36 gen-ReachabilityFireability-12
lola: time limit : 389 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 87 (type FNDP) for 39 gen-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 88 (type EQUN) for 39 gen-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 90 (type SRCH) for 39 gen-ReachabilityFireability-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 63 (type EQUN) for gen-ReachabilityFireability-09
lola: result : unknown
lola: FINISHED task # 62 (type FNDP) for gen-ReachabilityFireability-09
lola: result : true
lola: fired transitions : 30
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-88.sara.
lola: FINISHED task # 90 (type SRCH) for gen-ReachabilityFireability-13
lola: result : true
lola: markings : 96
lola: fired transitions : 110
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 87 (type FNDP) for gen-ReachabilityFireability-13 (obsolete)
lola: CANCELED task # 88 (type EQUN) for gen-ReachabilityFireability-13 (obsolete)
lola: LAUNCH task # 74 (type FNDP) for 12 gen-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 12 gen-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 77 (type SRCH) for 12 gen-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 88 (type EQUN) for gen-ReachabilityFireability-13
lola: result : unknown
lola: FINISHED task # 75 (type EQUN) for gen-ReachabilityFireability-04
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lola: LAUNCH task # 96 (type SRCH) for 30 gen-ReachabilityFireability-10
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 94 (type EQUN) for gen-ReachabilityFireability-10
lola: result : false
lola: CANCELED task # 93 (type FNDP) for gen-ReachabilityFireability-10 (obsolete)
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lola: LAUNCH task # 69 (type EQUN) for 9 gen-ReachabilityFireability-03
lola: time limit : 32000000 sec
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lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 71 (type SRCH) for 9 gen-ReachabilityFireability-03
lola: time limit : 32000000 sec
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lola: FINISHED task # 87 (type FNDP) for gen-ReachabilityFireability-13
lola: result : true
lola: fired transitions : 20
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 68 (type FNDP) for gen-ReachabilityFireability-03
lola: result : true
lola: fired transitions : 38
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 69 (type EQUN) for gen-ReachabilityFireability-03 (obsolete)
lola: CANCELED task # 71 (type SRCH) for gen-ReachabilityFireability-03 (obsolete)
lola: LAUNCH task # 106 (type FNDP) for 42 gen-ReachabilityFireability-14
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lola: LAUNCH task # 109 (type SRCH) for 42 gen-ReachabilityFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-69.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-107.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-03: EF true findpath
gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
gen-ReachabilityFireability-10: EF false state equation
gen-ReachabilityFireability-13: EF true tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 4 1 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 2 3 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF EXCL 1/700 1/32 gen-ReachabilityFireability-12 10180 m, 2036 m/sec, 11913 t fired, .
106 EF FNDP 0/500 0/5 gen-ReachabilityFireability-14 3181 t fired, 89 attempts, .
107 EF STEQ 0/500 0/5 gen-ReachabilityFireability-14 sara is running.
109 EF SRCH 0/583 1/5 gen-ReachabilityFireability-14 2982 m, 596 m/sec, 3467 t fired, .
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gen-ReachabilityFireability-00: INITIAL false preprocessing
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gen-ReachabilityFireability-03: EF true findpath
gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
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gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
gen-ReachabilityFireability-10: EF false state equation
gen-ReachabilityFireability-13: EF true tandem / insertion
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gen-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 4 1 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 2 3 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF EXCL 6/700 6/32 gen-ReachabilityFireability-12 107168 m, 19397 m/sec, 125983 t fired, .
106 EF FNDP 5/500 0/5 gen-ReachabilityFireability-14 37663 t fired, 966 attempts, .
107 EF STEQ 5/500 0/5 gen-ReachabilityFireability-14 sara is running.
109 EF SRCH 5/583 2/5 gen-ReachabilityFireability-14 39827 m, 7369 m/sec, 46320 t fired, .
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gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-03: EF true findpath
gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
gen-ReachabilityFireability-10: EF false state equation
gen-ReachabilityFireability-13: EF true tandem / insertion
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gen-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 4 1 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 2 3 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF EXCL 11/700 10/32 gen-ReachabilityFireability-12 198681 m, 18302 m/sec, 233661 t fired, .
106 EF FNDP 10/495 0/5 gen-ReachabilityFireability-14 74545 t fired, 1840 attempts, .
107 EF STEQ 10/495 0/5 gen-ReachabilityFireability-14 sara is running.
109 EF SRCH 10/578 4/5 gen-ReachabilityFireability-14 71058 m, 6246 m/sec, 82759 t fired, .
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gen-ReachabilityFireability-00: INITIAL false preprocessing
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gen-ReachabilityFireability-03: EF true findpath
gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
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gen-ReachabilityFireability-13: EF true tandem / insertion
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gen-ReachabilityFireability-12: AG 0 4 1 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF EXCL 16/700 14/32 gen-ReachabilityFireability-12 284597 m, 17183 m/sec, 335033 t fired, .
106 EF FNDP 15/490 0/5 gen-ReachabilityFireability-14 108918 t fired, 2634 attempts, .
107 EF STEQ 15/490 0/5 gen-ReachabilityFireability-14 sara is running.
109 EF SRCH 15/573 5/5 gen-ReachabilityFireability-14 106756 m, 7139 m/sec, 124369 t fired, .
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gen-ReachabilityFireability-03: EF true findpath
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gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
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gen-ReachabilityFireability-10: EF false state equation
gen-ReachabilityFireability-13: EF true tandem / insertion
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gen-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
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gen-ReachabilityFireability-12: AG 0 4 1 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 2 2 0 1 0 1 0
gen-ReachabilityFireability-15: AG 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF EXCL 21/700 19/32 gen-ReachabilityFireability-12 391566 m, 21393 m/sec, 461357 t fired, .
106 EF FNDP 20/485 0/5 gen-ReachabilityFireability-14 151095 t fired, 3605 attempts, .
107 EF STEQ 20/485 0/5 gen-ReachabilityFireability-14 sara is running.
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lola: LAUNCH task # 113 (type FNDP) for 45 gen-ReachabilityFireability-15
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-03: EF true findpath
gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
gen-ReachabilityFireability-10: EF false state equation
gen-ReachabilityFireability-13: EF true tandem / insertion
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 4 1 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 2 2 0 1 0 1 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF EXCL 26/700 23/32 gen-ReachabilityFireability-12 476148 m, 16916 m/sec, 561206 t fired, .
106 EF FNDP 25/563 0/5 gen-ReachabilityFireability-14 186865 t fired, 4421 attempts, .
107 EF STEQ 25/563 0/5 gen-ReachabilityFireability-14 sara is running.
113 EF FNDP 5/497 0/5 gen-ReachabilityFireability-15 34338 t fired, 612 attempts, .
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lola: result : false
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lola: result : unknown
lola: fired transitions : 199259
lola: tried executions : 4701
lola: time used : 27.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-101.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-03: EF true findpath
gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
gen-ReachabilityFireability-10: EF false state equation
gen-ReachabilityFireability-13: EF true tandem / insertion
gen-ReachabilityFireability-14: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: AG 0 3 2 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 4 1 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF EXCL 31/876 26/32 gen-ReachabilityFireability-12 552493 m, 15269 m/sec, 651444 t fired, .
100 EF FNDP 3/579 0/5 gen-ReachabilityFireability-02 21434 t fired, 361 attempts, .
101 EF STEQ 3/695 0/5 gen-ReachabilityFireability-02 sara is running.
113 EF FNDP 10/689 0/5 gen-ReachabilityFireability-15 67621 t fired, 1213 attempts, .
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gen-ReachabilityFireability-00: INITIAL false preprocessing
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gen-ReachabilityFireability-03: EF true findpath
gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
gen-ReachabilityFireability-10: EF false state equation
gen-ReachabilityFireability-13: EF true tandem / insertion
gen-ReachabilityFireability-14: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: AG 0 3 2 0 1 0 0 0
gen-ReachabilityFireability-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-12: AG 0 4 1 0 1 0 0 0
gen-ReachabilityFireability-15: AG 0 4 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
85 EF EXCL 36/876 31/32 gen-ReachabilityFireability-12 651585 m, 19818 m/sec, 768787 t fired, .
100 EF FNDP 8/576 0/5 gen-ReachabilityFireability-02 62253 t fired, 1051 attempts, .
101 EF STEQ 8/692 0/5 gen-ReachabilityFireability-02 sara is running.
113 EF FNDP 15/686 0/5 gen-ReachabilityFireability-15 103871 t fired, 1867 attempts, .
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gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
gen-ReachabilityFireability-10: EF false state equation
gen-ReachabilityFireability-13: EF true tandem / insertion
gen-ReachabilityFireability-14: EF false state equation
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gen-ReachabilityFireability-02: AG 0 3 2 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
100 EF FNDP 13/571 0/5 gen-ReachabilityFireability-02 105500 t fired, 1788 attempts, .
101 EF STEQ 13/687 0/5 gen-ReachabilityFireability-02 sara is running.
113 EF FNDP 20/681 0/5 gen-ReachabilityFireability-15 142649 t fired, 2572 attempts, .
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gen-ReachabilityFireability-07: AG false findpath
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gen-ReachabilityFireability-09: AG false tandem / insertion
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
100 EF FNDP 18/566 0/5 gen-ReachabilityFireability-02 145605 t fired, 2476 attempts, .
101 EF STEQ 18/682 0/5 gen-ReachabilityFireability-02 sara is running.
113 EF FNDP 25/676 0/5 gen-ReachabilityFireability-15 177682 t fired, 3208 attempts, .
124 EF EXCL 5/1154 5/32 gen-ReachabilityFireability-11 83517 m, 16703 m/sec, 98128 t fired, .
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gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
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gen-ReachabilityFireability-02: AG 0 3 2 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
100 EF FNDP 23/561 0/5 gen-ReachabilityFireability-02 181799 t fired, 3097 attempts, .
101 EF STEQ 23/677 0/5 gen-ReachabilityFireability-02 sara is running.
113 EF FNDP 30/671 0/5 gen-ReachabilityFireability-15 212814 t fired, 3844 attempts, .
124 EF EXCL 10/1154 9/32 gen-ReachabilityFireability-11 170558 m, 17408 m/sec, 200694 t fired, .
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gen-ReachabilityFireability-00: INITIAL false preprocessing
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gen-ReachabilityFireability-03: EF true findpath
gen-ReachabilityFireability-04: EF false state equation
gen-ReachabilityFireability-05: EF true findpath
gen-ReachabilityFireability-06: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-09: AG false tandem / insertion
gen-ReachabilityFireability-10: EF false state equation
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100 EF FNDP 28/556 0/5 gen-ReachabilityFireability-02 222031 t fired, 3789 attempts, .
101 EF STEQ 28/672 0/5 gen-ReachabilityFireability-02 sara is running.
113 EF FNDP 35/666 0/5 gen-ReachabilityFireability-15 248155 t fired, 4486 attempts, .
124 EF EXCL 15/1154 13/32 gen-ReachabilityFireability-11 253398 m, 16568 m/sec, 298238 t fired, .
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100 EF FNDP 33/551 0/5 gen-ReachabilityFireability-02 263935 t fired, 4513 attempts, .
101 EF STEQ 33/667 0/5 gen-ReachabilityFireability-02 sara is running.
113 EF FNDP 40/661 0/5 gen-ReachabilityFireability-15 283578 t fired, 5130 attempts, .
124 EF EXCL 20/1154 16/32 gen-ReachabilityFireability-11 336762 m, 16672 m/sec, 396704 t fired, .
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100 EF FNDP 38/546 0/5 gen-ReachabilityFireability-02 298653 t fired, 5114 attempts, .
101 EF STEQ 38/662 0/5 gen-ReachabilityFireability-02 sara is running.
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100 EF FNDP 43/541 0/5 gen-ReachabilityFireability-02 336119 t fired, 5763 attempts, .
101 EF STEQ 43/657 0/5 gen-ReachabilityFireability-02 sara is running.
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100 EF FNDP 48/536 0/5 gen-ReachabilityFireability-02 370008 t fired, 6352 attempts, .
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81 EF FNDP 2/856 0/5 gen-ReachabilityFireability-12 17970 t fired, 353 attempts, .
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124 EF EXCL 40/1731 31/32 gen-ReachabilityFireability-11 666113 m, 16199 m/sec, 785930 t fired, .
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81 EF FNDP 7/854 0/5 gen-ReachabilityFireability-12 55967 t fired, 1101 attempts, .
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81 EF FNDP 12/849 0/5 gen-ReachabilityFireability-12 92508 t fired, 1819 attempts, .
82 EF STEQ 12/849 0/5 gen-ReachabilityFireability-12 sara is running.
113 EF FNDP 70/805 0/5 gen-ReachabilityFireability-15 506386 t fired, 9182 attempts, .
117 EF EXCL 5/3418 5/32 gen-ReachabilityFireability-15 91109 m, 18221 m/sec, 107022 t fired, .
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81 EF FNDP 17/844 0/5 gen-ReachabilityFireability-12 122845 t fired, 2417 attempts, .
82 EF STEQ 17/844 0/5 gen-ReachabilityFireability-12 sara is running.
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81 EF FNDP 22/839 0/5 gen-ReachabilityFireability-12 157545 t fired, 3101 attempts, .
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81 EF FNDP 533/613 0/5 gen-ReachabilityFireability-12 3695351 t fired, 72741 attempts, .
82 EF STEQ 533/1184 0/5 gen-ReachabilityFireability-12 sara is running.
114 EF STEQ 5/965 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 485/645 0/5 gen-ReachabilityFireability-11 3329519 t fired, 112980 attempts, .
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81 EF FNDP 538/608 0/5 gen-ReachabilityFireability-12 3730979 t fired, 73441 attempts, .
82 EF STEQ 538/1179 0/5 gen-ReachabilityFireability-12 sara is running.
114 EF STEQ 10/960 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 490/640 0/5 gen-ReachabilityFireability-11 3361566 t fired, 113970 attempts, .
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81 EF FNDP 543/603 0/5 gen-ReachabilityFireability-12 3764314 t fired, 74097 attempts, .
82 EF STEQ 543/1174 0/5 gen-ReachabilityFireability-12 sara is running.
114 EF STEQ 15/955 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 495/635 0/5 gen-ReachabilityFireability-11 3394434 t fired, 114996 attempts, .
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81 EF FNDP 548/598 0/5 gen-ReachabilityFireability-12 3801670 t fired, 74830 attempts, .
82 EF STEQ 548/1169 0/5 gen-ReachabilityFireability-12 sara is running.
114 EF STEQ 20/950 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 500/630 0/5 gen-ReachabilityFireability-11 3429942 t fired, 116112 attempts, .
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81 EF FNDP 553/593 0/5 gen-ReachabilityFireability-12 3838360 t fired, 75552 attempts, .
82 EF STEQ 553/1164 0/5 gen-ReachabilityFireability-12 sara is running.
114 EF STEQ 25/945 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 505/625 0/5 gen-ReachabilityFireability-11 3462921 t fired, 117127 attempts, .
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81 EF FNDP 558/588 0/5 gen-ReachabilityFireability-12 3872830 t fired, 76231 attempts, .
82 EF STEQ 558/1159 0/5 gen-ReachabilityFireability-12 sara is running.
114 EF STEQ 30/940 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 510/620 0/5 gen-ReachabilityFireability-11 3497314 t fired, 118181 attempts, .
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81 EF FNDP 563/583 0/5 gen-ReachabilityFireability-12 3904087 t fired, 76846 attempts, .
82 EF STEQ 563/1154 0/5 gen-ReachabilityFireability-12 sara is running.
114 EF STEQ 35/935 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 515/615 0/5 gen-ReachabilityFireability-11 3535881 t fired, 119387 attempts, .
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81 EF FNDP 568/578 0/5 gen-ReachabilityFireability-12 3937672 t fired, 77505 attempts, .
82 EF STEQ 568/1149 0/5 gen-ReachabilityFireability-12 sara is running.
114 EF STEQ 40/930 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 520/610 0/5 gen-ReachabilityFireability-11 3571019 t fired, 120462 attempts, .
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81 EF FNDP 573/573 0/5 gen-ReachabilityFireability-12 3971254 t fired, 78166 attempts, .
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114 EF STEQ 45/925 0/5 gen-ReachabilityFireability-15 sara is running.
120 EF FNDP 525/605 0/5 gen-ReachabilityFireability-11 3607676 t fired, 121603 attempts, .
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120 EF FNDP 530/600 0/5 gen-ReachabilityFireability-11 3642675 t fired, 122722 attempts, .
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
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82 EF STEQ 583/1134 0/5 gen-ReachabilityFireability-12 sara is running.
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120 EF FNDP 535/595 0/5 gen-ReachabilityFireability-11 3679771 t fired, 123879 attempts, .
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120 EF FNDP 540/590 0/5 gen-ReachabilityFireability-11 3713910 t fired, 124930 attempts, .
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120 EF FNDP 550/580 0/5 gen-ReachabilityFireability-11 3781351 t fired, 127015 attempts, .
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82 EF STEQ 603/1114 0/5 gen-ReachabilityFireability-12 sara is running.
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120 EF FNDP 555/575 0/5 gen-ReachabilityFireability-11 3814902 t fired, 128050 attempts, .
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MultiCrashLeafsetExtension-PT-S16C07"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is MultiCrashLeafsetExtension-PT-S16C07, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r289-tall-162124152700615"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MultiCrashLeafsetExtension-PT-S16C07.tgz
mv MultiCrashLeafsetExtension-PT-S16C07 execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;