Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r289-tall-162124152700607.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is MultiCrashLeafsetExtension-PT-S16C06, examination is ReachabilityFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r289-tall-162124152700607
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 11M
-rw-r--r-- 1 mcc users 37K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 125K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 27K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 90K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 6.6K May 12 07:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 29K May 12 07:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.7K May 12 07:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K May 12 07:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 6.3K May 11 18:52 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 23K May 11 18:52 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.0K May 11 15:54 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K May 11 15:54 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 12 04:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 12 04:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 7 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 11M May 12 08:13 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME gen-ReachabilityFireability-00
FORMULA_NAME gen-ReachabilityFireability-01
FORMULA_NAME gen-ReachabilityFireability-02
FORMULA_NAME gen-ReachabilityFireability-03
FORMULA_NAME gen-ReachabilityFireability-04
FORMULA_NAME gen-ReachabilityFireability-05
FORMULA_NAME gen-ReachabilityFireability-06
FORMULA_NAME gen-ReachabilityFireability-07
FORMULA_NAME gen-ReachabilityFireability-08
FORMULA_NAME gen-ReachabilityFireability-09
FORMULA_NAME gen-ReachabilityFireability-10
FORMULA_NAME gen-ReachabilityFireability-11
FORMULA_NAME gen-ReachabilityFireability-12
FORMULA_NAME gen-ReachabilityFireability-13
FORMULA_NAME gen-ReachabilityFireability-14
FORMULA_NAME gen-ReachabilityFireability-15

=== Now, execution of the tool begins

BK_START 1621301508861

starting LoLA
BK_INPUT MultiCrashLeafsetExtension-PT-S16C06
BK_EXAMINATION: ReachabilityFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityFireability

FORMULA gen-ReachabilityFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityFireability-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityFireability-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityFireability-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA gen-ReachabilityFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621301634424

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: LAUNCH INITIAL
lola: LAUNCH task # 4 (type CNST) for 3 gen-ReachabilityFireability-01
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 1 (type CNST) for 0 gen-ReachabilityFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 25 (type CNST) for 24 gen-ReachabilityFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 37 (type CNST) for 36 gen-ReachabilityFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 37 (type CNST) for gen-ReachabilityFireability-12
lola: result : false
lola: LAUNCH INITIAL
lola: LAUNCH task # 16 (type CNST) for 15 gen-ReachabilityFireability-05
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 46 (type CNST) for 45 gen-ReachabilityFireability-15
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 1 (type CNST) for gen-ReachabilityFireability-00
lola: result : false
lola: FINISHED task # 4 (type CNST) for gen-ReachabilityFireability-01
lola: result : false
lola: FINISHED task # 25 (type CNST) for gen-ReachabilityFireability-08
lola: result : false
lola: FINISHED task # 16 (type CNST) for gen-ReachabilityFireability-05
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-05: INITIAL false preprocessing
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-12: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-06: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-11: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-13: AG 0 0 0 0 0 0 0 0
gen-ReachabilityFireability-14: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-15: INITIAL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
46 INITIAL UNKN 0/0 0/0 gen-ReachabilityFireability-15 --

Time elapsed: 47 secs. Pages in use: 0
# running tasks: 1 of 4 Visible: 16
lola: FINISHED task # 46 (type CNST) for gen-ReachabilityFireability-15
lola: result : false
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 52 (type EXCL) for 12 gen-ReachabilityFireability-04
lola: time limit : 355 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 48 (type FNDP) for 12 gen-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 49 (type EQUN) for 12 gen-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 51 (type SRCH) for 12 gen-ReachabilityFireability-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 52 (type EXCL) for gen-ReachabilityFireability-04
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 48 (type FNDP) for gen-ReachabilityFireability-04 (obsolete)
lola: CANCELED task # 49 (type EQUN) for gen-ReachabilityFireability-04 (obsolete)
lola: CANCELED task # 51 (type SRCH) for gen-ReachabilityFireability-04 (obsolete)
lola: FINISHED task # 49 (type EQUN) for gen-ReachabilityFireability-04
lola: result : false
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-04: EF false tandem / relaxed
gen-ReachabilityFireability-05: INITIAL false preprocessing
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-12: INITIAL false preprocessing
gen-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-06: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-11: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-13: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 52 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 59 (type EXCL) for 21 gen-ReachabilityFireability-07
lola: time limit : 393 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 21 gen-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 21 gen-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 58 (type SRCH) for 21 gen-ReachabilityFireability-07
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-56.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-04: EF false tandem / relaxed
gen-ReachabilityFireability-05: INITIAL false preprocessing
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-12: INITIAL false preprocessing
gen-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-06: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-07: AG 0 1 4 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-11: EF 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-13: AG 0 0 0 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 1/1772 0/5 gen-ReachabilityFireability-07 --
56 EF STEQ 1/3544 0/5 gen-ReachabilityFireability-07 sara is running.
58 EF SRCH 1/3544 1/5 gen-ReachabilityFireability-07 --
59 EF EXCL 1/393 1/32 gen-ReachabilityFireability-07 17963 m, 3592 m/sec, 21061 t fired, .

Time elapsed: 57 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 55 (type FNDP) for gen-ReachabilityFireability-07
lola: result : true
lola: fired transitions : 170
lola: tried executions : 5
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 56 (type EQUN) for gen-ReachabilityFireability-07 (obsolete)
lola: CANCELED task # 58 (type SRCH) for gen-ReachabilityFireability-07 (obsolete)
lola: CANCELED task # 59 (type EXCL) for gen-ReachabilityFireability-07 (obsolete)
lola: LAUNCH task # 65 (type EXCL) for 30 gen-ReachabilityFireability-10
lola: time limit : 442 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 61 (type FNDP) for 30 gen-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 62 (type EQUN) for 30 gen-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 64 (type SRCH) for 30 gen-ReachabilityFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 56 (type EQUN) for gen-ReachabilityFireability-07
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityFireability-62.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-04: EF false tandem / relaxed
gen-ReachabilityFireability-05: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-12: INITIAL false preprocessing
gen-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 1 4 0 1 0 0 0
gen-ReachabilityFireability-11: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 5/319 0/5 gen-ReachabilityFireability-10 47185 t fired, 994 attempts, .
62 EF STEQ 5/319 0/5 gen-ReachabilityFireability-10 sara is running.
64 EF SRCH 5/351 3/5 gen-ReachabilityFireability-10 49360 m, 9872 m/sec, 57564 t fired, .
65 EF EXCL 5/442 4/32 gen-ReachabilityFireability-10 70449 m, 14089 m/sec, 82864 t fired, .

Time elapsed: 62 secs. Pages in use: 7
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-04: EF false tandem / relaxed
gen-ReachabilityFireability-05: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-12: INITIAL false preprocessing
gen-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 1 4 0 1 0 0 0
gen-ReachabilityFireability-11: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-14: EF 0 5 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 10/317 0/5 gen-ReachabilityFireability-10 111593 t fired, 2313 attempts, .
62 EF STEQ 10/317 0/5 gen-ReachabilityFireability-10 sara is running.
64 EF SRCH 10/349 5/5 gen-ReachabilityFireability-10 107429 m, 11613 m/sec, 125467 t fired, .
65 EF EXCL 10/442 9/32 gen-ReachabilityFireability-10 204610 m, 26832 m/sec, 241259 t fired, .

Time elapsed: 67 secs. Pages in use: 14
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 64 (type SRCH) for gen-ReachabilityFireability-10 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityFireability-00: INITIAL false preprocessing
gen-ReachabilityFireability-01: INITIAL false preprocessing
gen-ReachabilityFireability-04: EF false tandem / relaxed
gen-ReachabilityFireability-05: INITIAL false preprocessing
gen-ReachabilityFireability-07: AG false findpath
gen-ReachabilityFireability-08: INITIAL false preprocessing
gen-ReachabilityFireability-12: INITIAL false preprocessing
gen-ReachabilityFireability-15: INITIAL false preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityFireability-02: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-09: AG 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-10: EF 0 1 3 0 1 0 1 0
gen-ReachabilityFireability-11: EF 0 5 0 0 1 0 0 0
gen-ReachabilityFireability-13: AG 0 5 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 15/312 0/5 gen-ReachabilityFireability-10 180579 t fired, 3719 attempts, .
62 EF STEQ 15/312 0/5 gen-ReachabilityFireability-10 sara is running.
65 EF EXCL 15/442 16/32 gen-ReachabilityFireability-10 363944 m, 31866 m/sec, 429622 t fired, .

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lola: tried executions : 404
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61 EF FNDP 20/377 0/5 gen-ReachabilityFireability-10 248090 t fired, 5085 attempts, .
62 EF STEQ 20/377 0/5 gen-ReachabilityFireability-10 sara is running.
65 EF EXCL 20/506 21/32 gen-ReachabilityFireability-10 483693 m, 23949 m/sec, 571600 t fired, .
99 EF FNDP 4/391 0/5 gen-ReachabilityFireability-13 32747 t fired, 933 attempts, .

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61 EF FNDP 25/373 0/5 gen-ReachabilityFireability-10 316610 t fired, 6472 attempts, .
62 EF STEQ 25/373 0/5 gen-ReachabilityFireability-10 sara is running.
65 EF EXCL 25/506 26/32 gen-ReachabilityFireability-10 604948 m, 24251 m/sec, 714688 t fired, .
99 EF FNDP 9/387 0/5 gen-ReachabilityFireability-13 87916 t fired, 2911 attempts, .

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61 EF FNDP 30/368 0/5 gen-ReachabilityFireability-10 374390 t fired, 7638 attempts, .
62 EF STEQ 30/368 0/5 gen-ReachabilityFireability-10 sara is running.
65 EF EXCL 30/506 32/32 gen-ReachabilityFireability-10 738149 m, 26640 m/sec, 871958 t fired, .
99 EF FNDP 14/382 0/5 gen-ReachabilityFireability-13 148181 t fired, 4932 attempts, .

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61 EF FNDP 35/363 0/5 gen-ReachabilityFireability-10 448161 t fired, 9121 attempts, .
62 EF STEQ 35/363 0/5 gen-ReachabilityFireability-10 sara is running.
99 EF FNDP 19/377 0/5 gen-ReachabilityFireability-13 211594 t fired, 6960 attempts, .

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61 EF FNDP 40/358 0/5 gen-ReachabilityFireability-10 508106 t fired, 10331 attempts, .
62 EF STEQ 40/358 0/5 gen-ReachabilityFireability-10 sara is running.
90 EF EXCL 5/584 6/32 gen-ReachabilityFireability-02 134464 m, 26892 m/sec, 158451 t fired, .
99 EF FNDP 24/372 0/5 gen-ReachabilityFireability-13 265452 t fired, 8645 attempts, .

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61 EF FNDP 45/353 0/5 gen-ReachabilityFireability-10 571644 t fired, 11609 attempts, .
62 EF STEQ 45/353 0/5 gen-ReachabilityFireability-10 sara is running.
90 EF EXCL 10/584 13/32 gen-ReachabilityFireability-02 285063 m, 30119 m/sec, 336580 t fired, .
99 EF FNDP 29/367 0/5 gen-ReachabilityFireability-13 315862 t fired, 10192 attempts, .

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61 EF FNDP 50/348 0/5 gen-ReachabilityFireability-10 629288 t fired, 13055 attempts, .
62 EF STEQ 50/348 0/5 gen-ReachabilityFireability-10 sara is running.
90 EF EXCL 15/584 18/32 gen-ReachabilityFireability-02 424357 m, 27858 m/sec, 501435 t fired, .
99 EF FNDP 34/362 0/5 gen-ReachabilityFireability-13 365925 t fired, 11718 attempts, .

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61 EF FNDP 56/343 0/5 gen-ReachabilityFireability-10 646396 t fired, 13573 attempts, .
62 EF STEQ 56/343 0/5 gen-ReachabilityFireability-10 sara is running.
90 EF EXCL 21/584 20/32 gen-ReachabilityFireability-02 465826 m, 8293 m/sec, 550642 t fired, .
99 EF FNDP 40/357 0/5 gen-ReachabilityFireability-13 379287 t fired, 12115 attempts, .

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61 EF FNDP 62/381 0/5 gen-ReachabilityFireability-10 649110 t fired, 13652 attempts, .
74 EF FNDP 1/386 0/5 gen-ReachabilityFireability-06 28 t fired, 1 attempts, .
90 EF EXCL 27/584 20/32 gen-ReachabilityFireability-02 471742 m, 1183 m/sec, 557673 t fired, .
99 EF FNDP 46/346 0/5 gen-ReachabilityFireability-13 382001 t fired, 12202 attempts, .

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gen-ReachabilityFireability-01: INITIAL false preprocessing/home/mcc/BenchKit/BenchKit_head.sh: line 62: 409 Killed lola --conf=$BIN_DIR/configfiles/reachabilityfireabilityconf --formula=$DIR/ReachabilityFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MultiCrashLeafsetExtension-PT-S16C06"
export BK_EXAMINATION="ReachabilityFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is MultiCrashLeafsetExtension-PT-S16C06, examination is ReachabilityFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r289-tall-162124152700607"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/MultiCrashLeafsetExtension-PT-S16C06.tgz
mv MultiCrashLeafsetExtension-PT-S16C06 execution
cd execution
if [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "UpperBounds" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] || [ "ReachabilityFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityFireability" = "ReachabilityDeadlock" ] || [ "ReachabilityFireability" = "QuasiLiveness" ] || [ "ReachabilityFireability" = "StableMarking" ] || [ "ReachabilityFireability" = "Liveness" ] || [ "ReachabilityFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;