About the Execution of LoLA for MultiCrashLeafsetExtension-PT-S16C05
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 4006.048 | 3600000.00 | 4117427.00 | 8274.90 | TTTTFFFFFTFFFT?F | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r289-tall-162124152700598.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is MultiCrashLeafsetExtension-PT-S16C05, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r289-tall-162124152700598
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 9.7M
-rw-r--r-- 1 mcc users 54K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 189K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 45K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 154K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 7.0K May 12 07:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 31K May 12 07:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.4K May 12 07:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K May 12 07:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 6.2K May 11 18:51 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 22K May 11 18:51 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.1K May 11 15:53 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K May 11 15:53 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 12 04:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 12 04:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 7 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 9.1M May 12 08:13 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME gen-ReachabilityCardinality-00
FORMULA_NAME gen-ReachabilityCardinality-01
FORMULA_NAME gen-ReachabilityCardinality-02
FORMULA_NAME gen-ReachabilityCardinality-03
FORMULA_NAME gen-ReachabilityCardinality-04
FORMULA_NAME gen-ReachabilityCardinality-05
FORMULA_NAME gen-ReachabilityCardinality-06
FORMULA_NAME gen-ReachabilityCardinality-07
FORMULA_NAME gen-ReachabilityCardinality-08
FORMULA_NAME gen-ReachabilityCardinality-09
FORMULA_NAME gen-ReachabilityCardinality-10
FORMULA_NAME gen-ReachabilityCardinality-11
FORMULA_NAME gen-ReachabilityCardinality-12
FORMULA_NAME gen-ReachabilityCardinality-13
FORMULA_NAME gen-ReachabilityCardinality-14
FORMULA_NAME gen-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1621298987509
starting LoLA
BK_INPUT MultiCrashLeafsetExtension-PT-S16C05
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA gen-ReachabilityCardinality-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-11 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-01 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-07 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-13 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA gen-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_TIME_CONFINEMENT_REACHED
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 17 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-13: AG 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-14: EF 0 0 0 0 0 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 22 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 27 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 32 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 53 (type EXCL) for 36 gen-ReachabilityCardinality-12
lola: time limit : 223 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 49 (type FNDP) for 36 gen-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 50 (type EQUN) for 36 gen-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 52 (type SRCH) for 36 gen-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-50.sara.
lola: FINISHED task # 53 (type EXCL) for gen-ReachabilityCardinality-12
lola: result : true
lola: markings : 1362
lola: fired transitions : 1586
lola: time used : 2.000000
lola: memory pages used : 1
lola: CANCELED task # 49 (type FNDP) for gen-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 50 (type EQUN) for gen-ReachabilityCardinality-12 (obsolete)
lola: CANCELED task # 52 (type SRCH) for gen-ReachabilityCardinality-12 (obsolete)
lola: FINISHED task # 50 (type EQUN) for gen-ReachabilityCardinality-12
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 59 (type EXCL) for 24 gen-ReachabilityCardinality-08
lola: time limit : 254 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 55 (type FNDP) for 24 gen-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 56 (type EQUN) for 24 gen-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 58 (type SRCH) for 24 gen-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-56.sara.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 49 (type FNDP) for gen-ReachabilityCardinality-12
lola: result : true
lola: fired transitions : 3791
lola: tried executions : 90
lola: time used : 5.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-12: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 0 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 1 4 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 2/185 0/5 gen-ReachabilityCardinality-08 5410 t fired, 138 attempts, .
56 EF STEQ 2/185 0/5 gen-ReachabilityCardinality-08 sara is running.
58 EF SRCH 2/196 1/5 gen-ReachabilityCardinality-08 4154 m, 830 m/sec, 4796 t fired, .
59 EF EXCL 2/237 1/32 gen-ReachabilityCardinality-08 15000 m, 3000 m/sec, 17636 t fired, .
Time elapsed: 37 secs. Pages in use: 3
# running tasks: 4 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-12: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 1 4 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 7/175 0/5 gen-ReachabilityCardinality-08 79686 t fired, 2021 attempts, .
56 EF STEQ 7/175 0/5 gen-ReachabilityCardinality-08 sara is running.
58 EF SRCH 7/175 4/5 gen-ReachabilityCardinality-08 85538 m, 16276 m/sec, 99596 t fired, .
59 EF EXCL 7/237 8/32 gen-ReachabilityCardinality-08 196109 m, 36221 m/sec, 231589 t fired, .
Time elapsed: 42 secs. Pages in use: 12
# running tasks: 4 of 4 Visible: 16
lola: CANCELED task # 58 (type SRCH) for gen-ReachabilityCardinality-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-12: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 1 3 0 1 0 1 0
gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 12/171 0/5 gen-ReachabilityCardinality-08 154457 t fired, 3906 attempts, .
56 EF STEQ 12/171 0/5 gen-ReachabilityCardinality-08 sara is running.
59 EF EXCL 12/237 15/32 gen-ReachabilityCardinality-08 379256 m, 36629 m/sec, 448394 t fired, .
Time elapsed: 47 secs. Pages in use: 17
# running tasks: 4 of 4 Visible: 16
lola: LAUNCH task # 61 (type FNDP) for 12 gen-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-12: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-08: EF 0 1 3 0 1 0 1 0
gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
55 EF FNDP 17/175 0/5 gen-ReachabilityCardinality-08 230214 t fired, 5810 attempts, .
56 EF STEQ 17/166 0/5 gen-ReachabilityCardinality-08 sara is running.
59 EF EXCL 17/237 22/32 gen-ReachabilityCardinality-08 561831 m, 36515 m/sec, 664677 t fired, .
61 EF FNDP 5/177 0/5 gen-ReachabilityCardinality-04 75246 t fired, 3132 attempts, .
Time elapsed: 52 secs. Pages in use: 22
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 56 (type EQUN) for gen-ReachabilityCardinality-08
lola: result : false
lola: CANCELED task # 55 (type FNDP) for gen-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 59 (type EXCL) for gen-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 90 (type EXCL) for 15 gen-ReachabilityCardinality-05
lola: time limit : 253 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 99 (type FNDP) for 45 gen-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 100 (type EQUN) for 45 gen-ReachabilityCardinality-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 55 (type FNDP) for gen-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 254837
lola: tried executions : 6429
lola: time used : 19.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-100.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-12: AG false tandem / relaxed
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-15: EF 0 3 2 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 10/190 0/5 gen-ReachabilityCardinality-04 147818 t fired, 5921 attempts, .
90 EF EXCL 3/253 5/32 gen-ReachabilityCardinality-05 123995 m, 24799 m/sec, 146496 t fired, .
99 EF FNDP 3/186 0/5 gen-ReachabilityCardinality-15 48795 t fired, 1717 attempts, .
100 EF STEQ 3/186 0/5 gen-ReachabilityCardinality-15 sara is running.
Time elapsed: 57 secs. Pages in use: 24
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 100 (type EQUN) for gen-ReachabilityCardinality-15
lola: result : false
lola: CANCELED task # 99 (type FNDP) for gen-ReachabilityCardinality-15 (obsolete)
lola: LAUNCH task # 68 (type FNDP) for 33 gen-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type EQUN) for 33 gen-ReachabilityCardinality-11
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 99 (type FNDP) for gen-ReachabilityCardinality-15
lola: result : unknown
lola: fired transitions : 117586
lola: tried executions : 3389
lola: time used : 7.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 68 (type FNDP) for gen-ReachabilityCardinality-11
lola: result : true
lola: fired transitions : 1859
lola: tried executions : 47
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 69 (type EQUN) for gen-ReachabilityCardinality-11 (obsolete)
lola: LAUNCH task # 74 (type FNDP) for 3 gen-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 75 (type EQUN) for 3 gen-ReachabilityCardinality-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 69 (type EQUN) for gen-ReachabilityCardinality-11
lola: result : unknown
lola: FINISHED task # 74 (type FNDP) for gen-ReachabilityCardinality-01
lola: result : true
lola: fired transitions : 120
lola: tried executions : 3
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 75 (type EQUN) for gen-ReachabilityCardinality-01 (obsolete)
lola: LAUNCH task # 112 (type FNDP) for 30 gen-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 113 (type EQUN) for 30 gen-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-75.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-113.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 15/239 0/5 gen-ReachabilityCardinality-04 215920 t fired, 8431 attempts, .
90 EF EXCL 8/322 12/32 gen-ReachabilityCardinality-05 301268 m, 35454 m/sec, 356093 t fired, .
112 EF FNDP 1/235 0/5 gen-ReachabilityCardinality-10 4589 t fired, 238 attempts, .
113 EF STEQ 1/235 0/5 gen-ReachabilityCardinality-10 sara is running.
Time elapsed: 62 secs. Pages in use: 24
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-10: EF 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 20/238 0/5 gen-ReachabilityCardinality-04 276508 t fired, 10682 attempts, .
90 EF EXCL 13/322 18/32 gen-ReachabilityCardinality-05 441426 m, 28031 m/sec, 522051 t fired, .
112 EF FNDP 6/234 0/5 gen-ReachabilityCardinality-10 68689 t fired, 2874 attempts, .
113 EF STEQ 6/234 0/5 gen-ReachabilityCardinality-10 sara is running.
Time elapsed: 67 secs. Pages in use: 24
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 75 (type EQUN) for gen-ReachabilityCardinality-01
lola: result : true
lola: FINISHED task # 113 (type EQUN) for gen-ReachabilityCardinality-10
lola: result : false
lola: CANCELED task # 112 (type FNDP) for gen-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 126 (type FNDP) for 18 gen-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 127 (type EQUN) for 18 gen-ReachabilityCardinality-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 112 (type FNDP) for gen-ReachabilityCardinality-10
lola: result : unknown
lola: fired transitions : 112252
lola: tried executions : 4586
lola: time used : 9.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 126 (type FNDP) for gen-ReachabilityCardinality-06
lola: result : true
lola: fired transitions : 45
lola: tried executions : 2
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 127 (type EQUN) for gen-ReachabilityCardinality-06 (obsolete)
lola: LAUNCH task # 93 (type FNDP) for 6 gen-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 94 (type EQUN) for 6 gen-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-127.sara.
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-94.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-04: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 25/273 0/5 gen-ReachabilityCardinality-04 336357 t fired, 12843 attempts, .
90 EF EXCL 18/394 23/32 gen-ReachabilityCardinality-05 580916 m, 27898 m/sec, 687356 t fired, .
93 EF FNDP 2/294 0/5 gen-ReachabilityCardinality-02 19618 t fired, 745 attempts, .
94 EF STEQ 2/294 0/5 gen-ReachabilityCardinality-02 sara is running.
Time elapsed: 72 secs. Pages in use: 24
# running tasks: 4 of 4 Visible: 16
sara: place or transition ordering is non-deterministic
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-00: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-02: AG 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-03: EF 0 5 0 0 1 0 0 0
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gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 5 0 0 1 0 0 0
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61 EF FNDP 30/271 0/5 gen-ReachabilityCardinality-04 393167 t fired, 14941 attempts, .
90 EF EXCL 23/394 29/32 gen-ReachabilityCardinality-05 738568 m, 31530 m/sec, 874288 t fired, .
93 EF FNDP 7/292 0/5 gen-ReachabilityCardinality-02 81386 t fired, 2842 attempts, .
94 EF STEQ 7/292 0/5 gen-ReachabilityCardinality-02 sara is running.
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gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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61 EF FNDP 35/264 0/5 gen-ReachabilityCardinality-04 465267 t fired, 17555 attempts, .
93 EF FNDP 12/285 0/5 gen-ReachabilityCardinality-02 149744 t fired, 5086 attempts, .
94 EF STEQ 12/285 0/5 gen-ReachabilityCardinality-02 sara is running.
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gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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61 EF FNDP 40/261 0/5 gen-ReachabilityCardinality-04 540184 t fired, 20198 attempts, .
84 EF EXCL 5/439 8/32 gen-ReachabilityCardinality-14 195630 m, 39126 m/sec, 231042 t fired, .
93 EF FNDP 17/282 0/5 gen-ReachabilityCardinality-02 226207 t fired, 7550 attempts, .
94 EF STEQ 17/282 0/5 gen-ReachabilityCardinality-02 sara is running.
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61 EF FNDP 45/256 0/5 gen-ReachabilityCardinality-04 615560 t fired, 22954 attempts, .
84 EF EXCL 10/439 16/32 gen-ReachabilityCardinality-14 388372 m, 38548 m/sec, 459248 t fired, .
93 EF FNDP 22/277 0/5 gen-ReachabilityCardinality-02 303018 t fired, 9995 attempts, .
94 EF STEQ 22/277 0/5 gen-ReachabilityCardinality-02 sara is running.
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61 EF FNDP 50/251 0/5 gen-ReachabilityCardinality-04 690744 t fired, 25578 attempts, .
84 EF EXCL 15/439 23/32 gen-ReachabilityCardinality-14 578109 m, 37947 m/sec, 684023 t fired, .
93 EF FNDP 27/272 0/5 gen-ReachabilityCardinality-02 380048 t fired, 12429 attempts, .
94 EF STEQ 27/272 0/5 gen-ReachabilityCardinality-02 sara is running.
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61 EF FNDP 55/246 0/5 gen-ReachabilityCardinality-04 765753 t fired, 28174 attempts, .
84 EF EXCL 20/439 30/32 gen-ReachabilityCardinality-14 766770 m, 37732 m/sec, 907532 t fired, .
93 EF FNDP 32/267 0/5 gen-ReachabilityCardinality-02 457325 t fired, 14862 attempts, .
94 EF STEQ 32/267 0/5 gen-ReachabilityCardinality-02 sara is running.
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gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 4 0 0 1 0 1 0
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61 EF FNDP 60/241 0/5 gen-ReachabilityCardinality-04 840738 t fired, 30897 attempts, .
93 EF FNDP 37/262 0/5 gen-ReachabilityCardinality-02 534472 t fired, 17281 attempts, .
94 EF STEQ 37/262 0/5 gen-ReachabilityCardinality-02 sara is running.
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gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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gen-ReachabilityCardinality-04: EF 0 4 1 0 1 0 0 0
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gen-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
gen-ReachabilityCardinality-13: AG 0 4 1 0 1 0 0 0
gen-ReachabilityCardinality-14: EF 0 4 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 65/295 0/5 gen-ReachabilityCardinality-04 916035 t fired, 33583 attempts, .
93 EF FNDP 42/283 0/5 gen-ReachabilityCardinality-02 611844 t fired, 19690 attempts, .
94 EF STEQ 42/283 0/5 gen-ReachabilityCardinality-02 sara is running.
110 EF EXCL 5/582 8/32 gen-ReachabilityCardinality-13 193854 m, 38770 m/sec, 228936 t fired, .
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gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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61 EF FNDP 70/290 0/5 gen-ReachabilityCardinality-04 991054 t fired, 36265 attempts, .
93 EF FNDP 47/278 0/5 gen-ReachabilityCardinality-02 688931 t fired, 22088 attempts, .
94 EF STEQ 47/278 0/5 gen-ReachabilityCardinality-02 sara is running.
110 EF EXCL 10/582 16/32 gen-ReachabilityCardinality-13 387123 m, 38653 m/sec, 457780 t fired, .
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gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-15: EF false state equation
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61 EF FNDP 75/285 0/5 gen-ReachabilityCardinality-04 1066076 t fired, 38992 attempts, .
93 EF FNDP 52/273 0/5 gen-ReachabilityCardinality-02 766291 t fired, 24495 attempts, .
94 EF STEQ 52/273 0/5 gen-ReachabilityCardinality-02 sara is running.
110 EF EXCL 15/582 23/32 gen-ReachabilityCardinality-13 576996 m, 37974 m/sec, 682703 t fired, .
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gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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61 EF FNDP 80/280 0/5 gen-ReachabilityCardinality-04 1141025 t fired, 41704 attempts, .
93 EF FNDP 57/268 0/5 gen-ReachabilityCardinality-02 843994 t fired, 26894 attempts, .
94 EF STEQ 57/268 0/5 gen-ReachabilityCardinality-02 sara is running.
110 EF EXCL 20/582 30/32 gen-ReachabilityCardinality-13 765545 m, 37709 m/sec, 906075 t fired, .
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gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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61 EF FNDP 85/275 0/5 gen-ReachabilityCardinality-04 1216069 t fired, 44408 attempts, .
93 EF FNDP 62/263 0/5 gen-ReachabilityCardinality-02 921453 t fired, 29299 attempts, .
94 EF STEQ 62/263 0/5 gen-ReachabilityCardinality-02 sara is running.
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gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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gen-ReachabilityCardinality-15: EF false state equation
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61 EF FNDP 90/355 0/5 gen-ReachabilityCardinality-04 1286414 t fired, 46940 attempts, .
93 EF FNDP 67/375 0/5 gen-ReachabilityCardinality-02 999253 t fired, 31670 attempts, .
94 EF STEQ 67/375 0/5 gen-ReachabilityCardinality-02 sara is running.
123 EF EXCL 1/1154 2/32 gen-ReachabilityCardinality-07 35650 m, 7130 m/sec, 41948 t fired, .
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gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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61 EF FNDP 95/500 0/5 gen-ReachabilityCardinality-04 1361515 t fired, 49521 attempts, .
93 EF FNDP 72/435 0/5 gen-ReachabilityCardinality-02 1076749 t fired, 34061 attempts, .
94 EF STEQ 72/435 0/5 gen-ReachabilityCardinality-02 sara is running.
97 EF EXCL 3/1730 4/32 gen-ReachabilityCardinality-02 98943 m, 19788 m/sec, 116825 t fired, .
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lola: FINISHED task # 94 (type EQUN) for gen-ReachabilityCardinality-02
lola: result : false
lola: CANCELED task # 93 (type FNDP) for gen-ReachabilityCardinality-02 (obsolete)
lola: CANCELED task # 97 (type EXCL) for gen-ReachabilityCardinality-02 (obsolete)
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lola: LAUNCH task # 106 (type FNDP) for 39 gen-ReachabilityCardinality-13
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lola: LAUNCH task # 107 (type EQUN) for 39 gen-ReachabilityCardinality-13
lola: time limit : 32000000 sec
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lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 93 (type FNDP) for gen-ReachabilityCardinality-02
lola: result : unknown
lola: fired transitions : 1101998
lola: tried executions : 34826
lola: time used : 74.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-107.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-04: EF 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 4 0 0 1 0 1 0
gen-ReachabilityCardinality-13: AG 0 2 2 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 4 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 100/613 0/5 gen-ReachabilityCardinality-04 1434179 t fired, 52050 attempts, .
65 EF EXCL 3/3456 5/32 gen-ReachabilityCardinality-04 114835 m, 22967 m/sec, 135690 t fired, .
106 EF FNDP 3/691 0/5 gen-ReachabilityCardinality-13 46592 t fired, 1351 attempts, .
107 EF STEQ 3/576 0/5 gen-ReachabilityCardinality-13 sara is running.
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gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-04: EF 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 4 0 0 1 0 1 0
gen-ReachabilityCardinality-13: AG 0 2 2 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 4 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 105/610 0/5 gen-ReachabilityCardinality-04 1509757 t fired, 54698 attempts, .
65 EF EXCL 8/3456 12/32 gen-ReachabilityCardinality-04 297915 m, 36616 m/sec, 352047 t fired, .
106 EF FNDP 8/688 0/5 gen-ReachabilityCardinality-13 121962 t fired, 3534 attempts, .
107 EF STEQ 8/573 0/5 gen-ReachabilityCardinality-13 sara is running.
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lola: FINISHED task # 107 (type EQUN) for gen-ReachabilityCardinality-13
lola: result : false
lola: CANCELED task # 106 (type FNDP) for gen-ReachabilityCardinality-13 (obsolete)
lola: LAUNCH task # 80 (type FNDP) for 42 gen-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 81 (type EQUN) for 42 gen-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: memory limit: 5 pages
lola: FINISHED task # 106 (type FNDP) for gen-ReachabilityCardinality-13
lola: result : unknown
lola: fired transitions : 165009
lola: tried executions : 4780
lola: time used : 11.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-81.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-04: EF 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 4 0 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 2 2 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 110/780 0/5 gen-ReachabilityCardinality-04 1582754 t fired, 57178 attempts, .
65 EF EXCL 13/3456 19/32 gen-ReachabilityCardinality-04 470839 m, 34584 m/sec, 556793 t fired, .
80 EF FNDP 2/861 0/5 gen-ReachabilityCardinality-14 28749 t fired, 843 attempts, .
81 EF STEQ 2/861 0/5 gen-ReachabilityCardinality-14 sara is running.
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sara: place or transition ordering is non-deterministic
lola: FINISHED task # 81 (type EQUN) for gen-ReachabilityCardinality-14
lola: result : unknown
lola: LAUNCH task # 86 (type FNDP) for 15 gen-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-04: EF 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 3 1 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 2 1 0 2 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 115/1070 0/5 gen-ReachabilityCardinality-04 1656369 t fired, 59764 attempts, .
65 EF EXCL 18/3456 25/32 gen-ReachabilityCardinality-04 645014 m, 34835 m/sec, 763348 t fired, .
80 EF FNDP 7/855 0/5 gen-ReachabilityCardinality-14 100904 t fired, 2950 attempts, .
86 EF FNDP 1/859 0/5 gen-ReachabilityCardinality-05 14706 t fired, 446 attempts, .
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gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-04: EF 0 3 2 0 1 0 0 0
gen-ReachabilityCardinality-05: EF 0 3 1 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 2 1 0 2 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 120/1069 0/5 gen-ReachabilityCardinality-04 1731281 t fired, 62410 attempts, .
65 EF EXCL 23/3456 32/32 gen-ReachabilityCardinality-04 823516 m, 35700 m/sec, 974461 t fired, .
80 EF FNDP 12/854 0/5 gen-ReachabilityCardinality-14 174447 t fired, 5096 attempts, .
86 EF FNDP 6/858 0/5 gen-ReachabilityCardinality-05 85674 t fired, 2511 attempts, .
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lola: CANCELED task # 65 (type EXCL) for gen-ReachabilityCardinality-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-04: EF 0 3 1 0 1 0 1 0
gen-ReachabilityCardinality-05: EF 0 3 1 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 2 1 0 2 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 125/1064 0/5 gen-ReachabilityCardinality-04 1806328 t fired, 65088 attempts, .
80 EF FNDP 17/849 0/5 gen-ReachabilityCardinality-14 248151 t fired, 7244 attempts, .
86 EF FNDP 11/853 0/5 gen-ReachabilityCardinality-05 156746 t fired, 4577 attempts, .
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lola: LAUNCH task # 62 (type EQUN) for 12 gen-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-62.sara.
sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-04: EF 0 2 2 0 1 0 1 0
gen-ReachabilityCardinality-05: EF 0 3 1 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 2 1 0 2 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
61 EF FNDP 130/1651 0/5 gen-ReachabilityCardinality-04 1880715 t fired, 67628 attempts, .
62 EF STEQ 5/1142 0/5 gen-ReachabilityCardinality-04 sara is running.
80 EF FNDP 22/1131 0/5 gen-ReachabilityCardinality-14 320787 t fired, 9359 attempts, .
86 EF FNDP 16/1135 0/5 gen-ReachabilityCardinality-05 228374 t fired, 6659 attempts, .
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lola: FINISHED task # 62 (type EQUN) for gen-ReachabilityCardinality-04
lola: result : false
lola: CANCELED task # 61 (type FNDP) for gen-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 87 (type EQUN) for 15 gen-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 89 (type SRCH) for 15 gen-ReachabilityCardinality-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 61 (type FNDP) for gen-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 1934463
lola: tried executions : 69528
lola: time used : 134.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-87.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-05: EF 0 1 3 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 2 1 0 2 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 27/3419 0/5 gen-ReachabilityCardinality-14 391000 t fired, 11401 attempts, .
86 EF FNDP 21/1699 0/5 gen-ReachabilityCardinality-05 297747 t fired, 8672 attempts, .
87 EF STEQ 1/1709 0/5 gen-ReachabilityCardinality-05 sara is running.
89 EF SRCH 1/1709 1/5 gen-ReachabilityCardinality-05 16296 m, 3259 m/sec, 18715 t fired, .
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sara: place or transition ordering is non-deterministic
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-05: EF 0 1 3 0 1 0 1 0
gen-ReachabilityCardinality-14: EF 0 2 1 0 2 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 32/3418 0/5 gen-ReachabilityCardinality-14 464437 t fired, 13534 attempts, .
86 EF FNDP 26/1698 0/5 gen-ReachabilityCardinality-05 370144 t fired, 10767 attempts, .
87 EF STEQ 6/1708 0/5 gen-ReachabilityCardinality-05 sara is running.
89 EF SRCH 6/1708 4/5 gen-ReachabilityCardinality-05 80520 m, 12844 m/sec, 93316 t fired, .
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lola: FINISHED task # 87 (type EQUN) for gen-ReachabilityCardinality-05
lola: result : false
lola: CANCELED task # 86 (type FNDP) for gen-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 89 (type SRCH) for gen-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 83 (type SRCH) for 42 gen-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 85 (type SRCH) for 42 gen-ReachabilityCardinality-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 86 (type FNDP) for gen-ReachabilityCardinality-05
lola: result : unknown
lola: fired transitions : 401154
lola: tried executions : 11670
lola: time used : 28.000000
lola: memory pages used : 0
lola: FINISHED task # 85 (type SRCH) for gen-ReachabilityCardinality-14
lola: result : unknown
lola: markings : 18
lola: fired transitions : 17
lola: time used : 0.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-14: EF 0 0 2 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 37/3445 0/5 gen-ReachabilityCardinality-14 535962 t fired, 15612 attempts, .
83 EF SRCH 3/3411 2/5 gen-ReachabilityCardinality-14 33369 m, 6673 m/sec, 38841 t fired, .
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gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-14: EF 0 0 2 0 3 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 42/3445 0/5 gen-ReachabilityCardinality-14 609676 t fired, 17758 attempts, .
83 EF SRCH 8/3411 4/5 gen-ReachabilityCardinality-14 96052 m, 12536 m/sec, 112182 t fired, .
Time elapsed: 197 secs. Pages in use: 32
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lola: CANCELED task # 83 (type SRCH) for gen-ReachabilityCardinality-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-14: EF 0 0 1 0 3 0 2 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 47/3445 0/5 gen-ReachabilityCardinality-14 683600 t fired, 19906 attempts, .
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gen-ReachabilityCardinality-00: EF true tandem / relaxed
gen-ReachabilityCardinality-01: EF true findpath
gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
gen-ReachabilityCardinality-14: EF 0 0 1 0 3 0 2 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
80 EF FNDP 52/3445 0/5 gen-ReachabilityCardinality-14 757530 t fired, 22052 attempts, .
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80 EF FNDP 1792/3445 0/5 gen-ReachabilityCardinality-14 27077137 t fired, 784707 attempts, .
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80 EF FNDP 1797/3445 0/5 gen-ReachabilityCardinality-14 27153319 t fired, 786914 attempts, .
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80 EF FNDP 1982/3445 0/5 gen-ReachabilityCardinality-14 29970663 t fired, 868538 attempts, .
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80 EF FNDP 1987/3445 0/5 gen-ReachabilityCardinality-14 30046895 t fired, 870747 attempts, .
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80 EF FNDP 1992/3445 0/5 gen-ReachabilityCardinality-14 30123255 t fired, 872962 attempts, .
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80 EF FNDP 1997/3445 0/5 gen-ReachabilityCardinality-14 30199527 t fired, 875174 attempts, .
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80 EF FNDP 2002/3445 0/5 gen-ReachabilityCardinality-14 30275794 t fired, 877384 attempts, .
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80 EF FNDP 2007/3445 0/5 gen-ReachabilityCardinality-14 30351931 t fired, 879589 attempts, .
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80 EF FNDP 2012/3445 0/5 gen-ReachabilityCardinality-14 30428209 t fired, 881799 attempts, .
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80 EF FNDP 2077/3445 0/5 gen-ReachabilityCardinality-14 31419089 t fired, 910508 attempts, .
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gen-ReachabilityCardinality-02: AG true state equation
gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
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80 EF FNDP 2082/3445 0/5 gen-ReachabilityCardinality-14 31495387 t fired, 912720 attempts, .
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gen-ReachabilityCardinality-03: EF true tandem / relaxed
gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
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80 EF FNDP 2087/3445 0/5 gen-ReachabilityCardinality-14 31571501 t fired, 914923 attempts, .
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gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
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80 EF FNDP 2092/3445 0/5 gen-ReachabilityCardinality-14 31647676 t fired, 917132 attempts, .
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gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
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80 EF FNDP 2097/3445 0/5 gen-ReachabilityCardinality-14 31723810 t fired, 919336 attempts, .
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gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
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80 EF FNDP 2102/3445 0/5 gen-ReachabilityCardinality-14 31800148 t fired, 921551 attempts, .
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gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
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80 EF FNDP 2107/3445 0/5 gen-ReachabilityCardinality-14 31876340 t fired, 923761 attempts, .
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gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
gen-ReachabilityCardinality-15: EF false state equation
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80 EF FNDP 2112/3445 0/5 gen-ReachabilityCardinality-14 31952630 t fired, 925974 attempts, .
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gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
gen-ReachabilityCardinality-12: AG false tandem / relaxed
gen-ReachabilityCardinality-13: AG true state equation
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gen-ReachabilityCardinality-05: EF false state equation
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gen-ReachabilityCardinality-09: EF true tandem / relaxed
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80 EF FNDP 2122/3445 0/5 gen-ReachabilityCardinality-14 32104973 t fired, 930386 attempts, .
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80 EF FNDP 2127/3445 0/5 gen-ReachabilityCardinality-14 32181078 t fired, 932590 attempts, .
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gen-ReachabilityCardinality-09: EF true tandem / relaxed
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gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
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gen-ReachabilityCardinality-09: EF true tandem / relaxed
gen-ReachabilityCardinality-10: EF false state equation
gen-ReachabilityCardinality-11: AG false findpath
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gen-ReachabilityCardinality-04: EF false state equation
gen-ReachabilityCardinality-05: EF false state equation
gen-ReachabilityCardinality-06: AG false findpath
gen-ReachabilityCardinality-07: AG false tandem / relaxed
gen-ReachabilityCardinality-08: EF false state equation
gen-ReachabilityCardinality-09: EF true tandem / relaxed
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gen-ReachabilityCardinality-12: AG false tandem / relaxed
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========== file over 1MB has been truncated ======
retrieve it from the run archives if needed
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="MultiCrashLeafsetExtension-PT-S16C05"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is MultiCrashLeafsetExtension-PT-S16C05, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r289-tall-162124152700598"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/MultiCrashLeafsetExtension-PT-S16C05.tgz
mv MultiCrashLeafsetExtension-PT-S16C05 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;