fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r289-tall-162124152700562
Last Updated
Jun 28, 2021

About the Execution of LoLA for LeafsetExtension-PT-S64C4

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15269.147 1537185.00 2244334.00 3047.30 [undef] Cannot compute

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r289-tall-162124152700562.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.......................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is LeafsetExtension-PT-S64C4, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r289-tall-162124152700562
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 33M
-rw-r--r-- 1 mcc users 47K May 15 08:57 CTLCardinality.txt
-rw-r--r-- 1 mcc users 172K May 15 08:57 CTLCardinality.xml
-rw-r--r-- 1 mcc users 26K May 15 08:57 CTLFireability.txt
-rw-r--r-- 1 mcc users 90K May 15 08:57 CTLFireability.xml
-rw-r--r-- 1 mcc users 6.4K May 12 07:58 LTLCardinality.txt
-rw-r--r-- 1 mcc users 28K May 12 07:58 LTLCardinality.xml
-rw-r--r-- 1 mcc users 4.3K May 12 07:58 LTLFireability.txt
-rw-r--r-- 1 mcc users 20K May 12 07:58 LTLFireability.xml
-rw-r--r-- 1 mcc users 1 May 12 08:13 NewModel
-rw-r--r-- 1 mcc users 3.8K May 11 18:45 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 13K May 11 18:45 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 5.4K May 11 15:50 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 20K May 11 15:50 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K May 12 04:40 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.0K May 12 04:40 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 12 08:13 equiv_col
-rw-r--r-- 1 mcc users 6 May 12 08:13 instance
-rw-r--r-- 1 mcc users 6 May 12 08:13 iscolored
-rw-r--r-- 1 mcc users 33M May 12 08:13 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-00
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-01
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-02
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-03
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-04
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-05
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-06
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-07
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-08
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-09
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-10
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-11
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-12
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-13
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-14
FORMULA_NAME LeafsetExtension-PT-S64C4-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1621293986930

starting LoLA
BK_INPUT LeafsetExtension-PT-S64C4
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

BK_STOP 1621295524115

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:478
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:714
lola: LAUNCH task # 64 (type SKEL/SRCH) for 0 LeafsetExtension-PT-S64C4-CTLFireability-00
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 64 (type SKEL/SRCH) for LeafsetExtension-PT-S64C4-CTLFireability-00
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: NOTDEADLOCKFREE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1266 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1271 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 4.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
lola: Rule S: 0 transitions removed,0 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1276 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1281 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1286 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1291 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1296 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1301 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 66 (type SKEL/FNDP) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type SKEL/EQUN) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 68 (type SKEL/SRCH) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 69 (type SKEL/SRCH) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 66 (type SKEL/FNDP) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 67 (type EQUN) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
lola: CANCELED task # 68 (type SRCH) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
lola: CANCELED task # 69 (type SRCH) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
sara: try reading problem file /home/mcc/execution/CTLFireability-67.sara.
lola: Created skeleton in 1.000000 secs.
lola: RELEASE
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 67 (type SKEL/EQUN) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 3 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1306 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 5 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1311 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 5 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1316 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 3.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1321 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 5.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1326 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1331 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1336 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1341 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1346 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1351 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1356 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1361 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1366 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1371 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1376 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1381 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1386 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1391 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1396 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1401 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1406 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1411 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1416 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1421 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 6 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1426 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 73 (type EXCL) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 108 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 71 (type FNDP) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type EQUN) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 74 (type SRCH) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 73 (type EXCL) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 71 (type FNDP) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
lola: CANCELED task # 72 (type EQUN) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
lola: CANCELED task # 74 (type SRCH) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
lola: FINISHED task # 74 (type SRCH) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 71 (type FNDP) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
sara: try reading problem file /home/mcc/execution/CTLFireability-72.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 72 (type EQUN) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 10 0 0 2
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1431 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 77 (type EXCL) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 114 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 75 (type FNDP) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 76 (type EQUN) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 78 (type SRCH) for 30 LeafsetExtension-PT-S64C4-CTLFireability-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 77 (type EXCL) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : true
lola: markings : 2
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: CANCELED task # 75 (type FNDP) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
lola: CANCELED task # 76 (type EQUN) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
lola: CANCELED task # 78 (type SRCH) for LeafsetExtension-PT-S64C4-CTLFireability-10 (obsolete)
lola: FINISHED task # 75 (type FNDP) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:711
sara: try reading problem file /home/mcc/execution/CTLFireability-76.sara.
sara: place or transition ordering is non-deterministic

lola: FINISHED task # 76 (type EQUN) for LeafsetExtension-PT-S64C4-CTLFireability-10
lola: result : true
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1436 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1441 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 1446 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: LAUNCH task # 7 (type EXCL) for 6 LeafsetExtension-PT-S64C4-CTLFireability-02
lola: time limit : 126 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 3/126 1/32 LeafsetExtension-PT-S64C4-CTLFireability-02 3607 m, 721 m/sec, 11413 t fired, .

Time elapsed: 1451 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 8/126 1/32 LeafsetExtension-PT-S64C4-CTLFireability-02 10232 m, 1325 m/sec, 32582 t fired, .

Time elapsed: 1456 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 13/126 2/32 LeafsetExtension-PT-S64C4-CTLFireability-02 15110 m, 975 m/sec, 50901 t fired, .

Time elapsed: 1461 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 18/126 2/32 LeafsetExtension-PT-S64C4-CTLFireability-02 20834 m, 1144 m/sec, 71604 t fired, .

Time elapsed: 1466 secs. Pages in use: 2
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 23/126 3/32 LeafsetExtension-PT-S64C4-CTLFireability-02 26829 m, 1199 m/sec, 90776 t fired, .

Time elapsed: 1471 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 28/126 3/32 LeafsetExtension-PT-S64C4-CTLFireability-02 31675 m, 969 m/sec, 109187 t fired, .

Time elapsed: 1476 secs. Pages in use: 3
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 33/126 4/32 LeafsetExtension-PT-S64C4-CTLFireability-02 36589 m, 982 m/sec, 127105 t fired, .

Time elapsed: 1481 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 38/126 4/32 LeafsetExtension-PT-S64C4-CTLFireability-02 42156 m, 1113 m/sec, 144904 t fired, .

Time elapsed: 1486 secs. Pages in use: 4
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 43/126 5/32 LeafsetExtension-PT-S64C4-CTLFireability-02 47456 m, 1060 m/sec, 163123 t fired, .

Time elapsed: 1491 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 48/126 5/32 LeafsetExtension-PT-S64C4-CTLFireability-02 52850 m, 1078 m/sec, 184016 t fired, .

Time elapsed: 1496 secs. Pages in use: 5
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 53/126 6/32 LeafsetExtension-PT-S64C4-CTLFireability-02 59272 m, 1284 m/sec, 204514 t fired, .

Time elapsed: 1501 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 58/126 6/32 LeafsetExtension-PT-S64C4-CTLFireability-02 64556 m, 1056 m/sec, 223503 t fired, .

Time elapsed: 1506 secs. Pages in use: 6
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 63/126 7/32 LeafsetExtension-PT-S64C4-CTLFireability-02 70173 m, 1123 m/sec, 244050 t fired, .

Time elapsed: 1511 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 68/126 7/32 LeafsetExtension-PT-S64C4-CTLFireability-02 76190 m, 1203 m/sec, 262538 t fired, .

Time elapsed: 1516 secs. Pages in use: 7
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 13 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 73/126 8/32 LeafsetExtension-PT-S64C4-CTLFireability-02 81403 m, 1042 m/sec, 281378 t fired, .

Time elapsed: 1521 secs. Pages in use: 8
# running tasks: 1 of 4 Visible: 16
lola: planning for (null) stopped (result already fixed).
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 14 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 78/126 9/32 LeafsetExtension-PT-S64C4-CTLFireability-02 86868 m, 1093 m/sec, 300968 t fired, .

Time elapsed: 1526 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 14 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 83/126 9/32 LeafsetExtension-PT-S64C4-CTLFireability-02 94141 m, 1454 m/sec, 324206 t fired, .

Time elapsed: 1531 secs. Pages in use: 9
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
LeafsetExtension-PT-S64C4-CTLFireability-00: EXEF 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-06: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-08: EXEG 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-10: CONJ 0 0 0 0 14 0 0 3
LeafsetExtension-PT-S64C4-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
LeafsetExtension-PT-S64C4-CTLFireability-15: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 88/126 11/32 LeafsetExtension-PT-S64C4-CTLFireability-02 110073 m, 3186 m/sec, 378906 t fired, .

Time elapsed: 1536 secs. Pages in use: 11
# running tasks: 1 of 4 Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 409 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="LeafsetExtension-PT-S64C4"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is LeafsetExtension-PT-S64C4, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r289-tall-162124152700562"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/LeafsetExtension-PT-S64C4.tgz
mv LeafsetExtension-PT-S64C4 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;