About the Execution of LoLA for TokenRing-COL-040
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16236.796 | 725759.00 | 741858.00 | 2637.60 | F??FF???F????F?? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r270-smll-162123877100042.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2021-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
............................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is TokenRing-COL-040, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r270-smll-162123877100042
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 300K
-rw-r--r-- 1 mcc users 7.1K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 76K May 10 09:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 6.5K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 49K May 10 09:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.0K Mar 28 16:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 20K Mar 28 16:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.3K Mar 28 16:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 16K Mar 28 16:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Mar 27 14:23 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 14:23 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Mar 25 21:00 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 25 21:00 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 08:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 08:16 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:52 equiv_pt
-rw-r--r-- 1 mcc users 4 May 5 16:52 instance
-rw-r--r-- 1 mcc users 5 May 5 16:52 iscolored
-rw-r--r-- 1 mcc users 28K May 5 16:52 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME TokenRing-COL-040-CTLFireability-00
FORMULA_NAME TokenRing-COL-040-CTLFireability-01
FORMULA_NAME TokenRing-COL-040-CTLFireability-02
FORMULA_NAME TokenRing-COL-040-CTLFireability-03
FORMULA_NAME TokenRing-COL-040-CTLFireability-04
FORMULA_NAME TokenRing-COL-040-CTLFireability-05
FORMULA_NAME TokenRing-COL-040-CTLFireability-06
FORMULA_NAME TokenRing-COL-040-CTLFireability-07
FORMULA_NAME TokenRing-COL-040-CTLFireability-08
FORMULA_NAME TokenRing-COL-040-CTLFireability-09
FORMULA_NAME TokenRing-COL-040-CTLFireability-10
FORMULA_NAME TokenRing-COL-040-CTLFireability-11
FORMULA_NAME TokenRing-COL-040-CTLFireability-12
FORMULA_NAME TokenRing-COL-040-CTLFireability-13
FORMULA_NAME TokenRing-COL-040-CTLFireability-14
FORMULA_NAME TokenRing-COL-040-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1621337123582
starting LoLA
BK_INPUT TokenRing-COL-040
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA TokenRing-COL-040-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TokenRing-COL-040-CTLFireability-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TokenRing-COL-040-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TokenRing-COL-040-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA TokenRing-COL-040-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621337849341
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:196
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:182
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:132
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: LAUNCH INITIAL
lola: LAUNCH task # 2 (type SKEL/CNST) for 0 TokenRing-COL-040-CTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: ASSUMEDDEADLOCKFREE
lola: LAUNCH task # 11 (type SKEL/CNST) for 9 TokenRing-COL-040-CTLFireability-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 14 (type SKEL/CNST) for 12 TokenRing-COL-040-CTLFireability-04
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 26 (type SKEL/CNST) for 24 TokenRing-COL-040-CTLFireability-08
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 41 (type SKEL/CNST) for 39 TokenRing-COL-040-CTLFireability-13
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 41 (type SKEL/CNST) for TokenRing-COL-040-CTLFireability-13
lola: result : false
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: FINISHED task # 11 (type SKEL/CNST) for TokenRing-COL-040-CTLFireability-03
lola: result : false
lola: FINISHED task # 14 (type SKEL/CNST) for TokenRing-COL-040-CTLFireability-04
lola: result : false
lola: FINISHED task # 26 (type SKEL/CNST) for TokenRing-COL-040-CTLFireability-08
lola: result : false
lola: LAUNCH task # 48 (type SKEL/SRCH) for 3 TokenRing-COL-040-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 2 (type SKEL/CNST) for TokenRing-COL-040-CTLFireability-00
lola: result : false
lola: FINISHED task # 48 (type SKEL/SRCH) for TokenRing-COL-040-CTLFireability-01
lola: result : false
lola: markings : 1
lola: fired transitions : 2
lola: time used : 0.000000
lola: memory pages used : 1
lola: TR BINDINGS
lola: TR BINDINGS DONE
lola: Places: 1681, Transitions: 65641
lola: @ trans MainProcess
lola: @ trans OtherProcess
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 5 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 10 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 15 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 20 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 25 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 30 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 35 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 40 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 45 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 50 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 55 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 60 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 65 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 70 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 75 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 80 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 85 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 90 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 95 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 100 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 105 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 110 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 115 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 120 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 125 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 130 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 135 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 140 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 145 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 150 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 155 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 160 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 165 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 170 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 175 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 180 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 185 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 190 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 195 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 200 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 205 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 210 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 215 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 220 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 225 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 230 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 235 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 240 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 245 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 250 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 255 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 260 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 266 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 271 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 276 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 281 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 286 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 291 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 296 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 301 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 306 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 311 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 316 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 321 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 326 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 331 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 336 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 341 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 346 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 351 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 356 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 361 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 366 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 371 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 376 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 381 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 386 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 391 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 396 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 401 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 406 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 411 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 416 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 421 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 426 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 431 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 436 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 441 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 446 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 451 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 456 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 461 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 466 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 471 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 476 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 481 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 486 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 491 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 496 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 501 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 506 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 511 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 516 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 521 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 526 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 531 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 536 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 541 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 546 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 551 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 556 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 561 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 566 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 571 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 576 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 581 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 586 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 591 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 596 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 601 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 606 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 611 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 616 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 621 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 626 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 631 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 636 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 641 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 646 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 651 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 656 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 661 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 666 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 671 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 676 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 681 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 686 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 691 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 696 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 701 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 706 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 711 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 716 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-040-CTLFireability-00: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-03: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-04: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-08: INITIAL false skeleton: preprocessing
TokenRing-COL-040-CTLFireability-13: INITIAL false skeleton: preprocessing
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-040-CTLFireability-01: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-02: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-05: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-10: F 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-12: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-040-CTLFireability-15: CTL 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 721 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 403 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TokenRing-COL-040"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is TokenRing-COL-040, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r270-smll-162123877100042"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/TokenRing-COL-040.tgz
mv TokenRing-COL-040 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;