fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r270-smll-162123877100018
Last Updated
Jun 28, 2021

About the Execution of LoLA for TokenRing-COL-015

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
16244.239 188309.00 195157.00 979.50 T?FT?????T?TF??? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r270-smll-162123877100018.qcow2', fmt=qcow2 size=4294967296 backing_file=/data/fkordon/mcc2021-input.qcow2 cluster_size=65536 lazy_refcounts=off refcount_bits=16
Waiting for the VM to be ready (probing ssh)
...............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is TokenRing-COL-015, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r270-smll-162123877100018
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 324K
-rw-r--r-- 1 mcc users 8.4K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 90K May 10 09:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 7.3K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 58K May 10 09:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.6K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.3K Mar 28 16:46 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 16:46 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.5K Mar 28 16:46 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 16:46 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Mar 27 14:12 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 14:12 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.3K Mar 25 20:14 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 25 20:14 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 08:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.7K Mar 22 08:16 UpperBounds.xml
-rw-r--r-- 1 mcc users 5 May 5 16:52 equiv_pt
-rw-r--r-- 1 mcc users 4 May 5 16:52 instance
-rw-r--r-- 1 mcc users 5 May 5 16:52 iscolored
-rw-r--r-- 1 mcc users 16K May 5 16:52 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME TokenRing-COL-015-CTLFireability-00
FORMULA_NAME TokenRing-COL-015-CTLFireability-01
FORMULA_NAME TokenRing-COL-015-CTLFireability-02
FORMULA_NAME TokenRing-COL-015-CTLFireability-03
FORMULA_NAME TokenRing-COL-015-CTLFireability-04
FORMULA_NAME TokenRing-COL-015-CTLFireability-05
FORMULA_NAME TokenRing-COL-015-CTLFireability-06
FORMULA_NAME TokenRing-COL-015-CTLFireability-07
FORMULA_NAME TokenRing-COL-015-CTLFireability-08
FORMULA_NAME TokenRing-COL-015-CTLFireability-09
FORMULA_NAME TokenRing-COL-015-CTLFireability-10
FORMULA_NAME TokenRing-COL-015-CTLFireability-11
FORMULA_NAME TokenRing-COL-015-CTLFireability-12
FORMULA_NAME TokenRing-COL-015-CTLFireability-13
FORMULA_NAME TokenRing-COL-015-CTLFireability-14
FORMULA_NAME TokenRing-COL-015-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1621333560308

starting LoLA
BK_INPUT TokenRing-COL-015
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA TokenRing-COL-015-CTLFireability-03 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TokenRing-COL-015-CTLFireability-00 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TokenRing-COL-015-CTLFireability-02 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TokenRing-COL-015-CTLFireability-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TokenRing-COL-015-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA TokenRing-COL-015-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621333748617

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains High-Level net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading HL formula in XML format (--xmlformula)
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:196
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:135
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:122
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:284
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:168
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:129
lola: rewrite Frontend/Parser/formula_rewrite.k:196
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:287
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:228
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:278
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:165
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:117
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:116
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:98
lola: rewrite Frontend/Parser/formula_rewrite.k:153
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:123
lola: rewrite Frontend/Parser/formula_rewrite.k:159
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:120
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:415
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:115
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:179
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:281
lola: rewrite Frontend/Parser/formula_rewrite.k:114
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:156
lola: rewrite Frontend/Parser/formula_rewrite.k:147
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:121
lola: rewrite Frontend/Parser/formula_rewrite.k:96
lola: rewrite Frontend/Parser/formula_rewrite.k:162
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:138
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: rewrite Frontend/Parser/formula_rewrite.k:183
lola: rewrite Frontend/Parser/formula_rewrite.k:199
lola: rewrite Frontend/Parser/formula_rewrite.k:150
lola: LAUNCH INITIAL
lola: LAUNCH task # 11 (type SKEL/CNST) for 9 TokenRing-COL-015-CTLFireability-03
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 11 (type SKEL/CNST) for TokenRing-COL-015-CTLFireability-03
lola: result : true
lola: LAUNCH INITIAL
lola: LAUNCH task # 2 (type SKEL/CNST) for 0 TokenRing-COL-015-CTLFireability-00
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: FINISHED task # 2 (type SKEL/CNST) for TokenRing-COL-015-CTLFireability-00
lola: result : true
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 53 (type SKEL/FNDP) for 15 TokenRing-COL-015-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 54 (type SKEL/EQUN) for 15 TokenRing-COL-015-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: ASSUMEDDEADLOCKFREE
lola: LAUNCH task # 55 (type SKEL/SRCH) for 15 TokenRing-COL-015-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: ASSUMEDDEADLOCKFREE
lola: TR BINDINGS
lola: LAUNCH task # 56 (type SKEL/SRCH) for 15 TokenRing-COL-015-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 8 (type SKEL/CNST) for 6 TokenRing-COL-015-CTLFireability-02
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 33 (type SKEL/CNST) for 31 TokenRing-COL-015-CTLFireability-09
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 39 (type SKEL/CNST) for 37 TokenRing-COL-015-CTLFireability-11
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: LAUNCH INITIAL
lola: LAUNCH task # 42 (type SKEL/CNST) for 40 TokenRing-COL-015-CTLFireability-12
lola: time limit : 0 sec
lola: memory limit: 0 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:730
lola: rewrite Frontend/Parser/formula_rewrite.k:749
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 8 (type SKEL/CNST) for TokenRing-COL-015-CTLFireability-02
lola: result : false
lola: FINISHED task # 55 (type SKEL/SRCH) for TokenRing-COL-015-CTLFireability-05
lola: result : true
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 56 (type SKEL/SRCH) for TokenRing-COL-015-CTLFireability-05
lola: result : unknown
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 33 (type SKEL/CNST) for TokenRing-COL-015-CTLFireability-09
lola: result : true
lola: FINISHED task # 39 (type SKEL/CNST) for TokenRing-COL-015-CTLFireability-11
lola: result : true
lola: FINISHED task # 42 (type SKEL/CNST) for TokenRing-COL-015-CTLFireability-12
lola: result : false
lola: CANCELED task # 53 (type FNDP) for TokenRing-COL-015-CTLFireability-05 (obsolete)
lola: CANCELED task # 54 (type EQUN) for TokenRing-COL-015-CTLFireability-05 (obsolete)
lola: LAUNCH task # 58 (type SKEL/SRCH) for 22 TokenRing-COL-015-CTLFireability-06
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 59 (type SKEL/SRCH) for 15 TokenRing-COL-015-CTLFireability-05
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 53 (type SKEL/FNDP) for TokenRing-COL-015-CTLFireability-05
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: FINISHED task # 58 (type SKEL/SRCH) for TokenRing-COL-015-CTLFireability-06
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 54 (type SKEL/EQUN) for TokenRing-COL-015-CTLFireability-05
lola: result : unknown
lola: FINISHED task # 59 (type SKEL/SRCH) for TokenRing-COL-015-CTLFireability-05
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: TR BINDINGS DONE
lola: Places: 256, Transitions: 3616
lola: @ trans MainProcess
lola: @ trans OtherProcess
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 5 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 10 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 15 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 20 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 25 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 30 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 35 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 40 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 45 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 50 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 55 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 60 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 65 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 70 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 75 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 80 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 85 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 90 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 95 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 100 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 105 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 110 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 115 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 120 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 125 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 130 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 135 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 140 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 145 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 150 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 155 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: RELEASE
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 160 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 165 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 170 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 175 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 180 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
TokenRing-COL-015-CTLFireability-00: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-02: INITIAL false skeleton: preprocessing
TokenRing-COL-015-CTLFireability-03: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-09: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-11: INITIAL true skeleton: preprocessing
TokenRing-COL-015-CTLFireability-12: INITIAL false skeleton: preprocessing

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
TokenRing-COL-015-CTLFireability-01: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-04: AGEF 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-05: DISJ 0 0 0 0 5 0 0 0
TokenRing-COL-015-CTLFireability-06: F 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-07: SP ACTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-10: INITIAL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
TokenRing-COL-015-CTLFireability-15: INITIAL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 185 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 475 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="TokenRing-COL-015"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is TokenRing-COL-015, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r270-smll-162123877100018"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/TokenRing-COL-015.tgz
mv TokenRing-COL-015 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;