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Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r251-tall-162106741600146
Last Updated
Jun 28, 2021

About the Execution of LoLA for SmallOperatingSystem-PT-MT8192DC4096

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
7019.764 150325.00 126412.00 307.40 ?F??????T?????FT normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r251-tall-162106741600146.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
...................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r251-tall-162106741600146
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 344K
-rw-r--r-- 1 mcc users 13K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 81K May 10 09:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 74K May 10 09:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.9K Mar 28 16:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 23K Mar 28 16:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 28 16:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 16:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K Mar 27 13:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 27 13:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.6K Mar 25 19:29 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 25 19:29 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.0K Mar 22 08:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Mar 22 08:16 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:52 equiv_col
-rw-r--r-- 1 mcc users 13 May 5 16:52 instance
-rw-r--r-- 1 mcc users 6 May 5 16:52 iscolored
-rw-r--r-- 1 mcc users 8.1K May 5 16:52 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1621122830108

starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT8192DC4096
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621122980433

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:472
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:469
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:448
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: Created skeleton in 0.000000 secs.
lola: LAUNCH task # 64 (type EXCL) for 43 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09
lola: time limit : 138 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 66 (type FNDP) for 3 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 67 (type EQUN) for 3 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 69 (type SRCH) for 3 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: Created skeleton in 0.000000 secs.
sara: try reading problem file /home/mcc/execution/CTLFireability-67.sara.
sara: place or transition ordering is non-deterministic
lola: FINISHED task # 69 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:726
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 66 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
lola: result : true
lola: fired transitions : 16383
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: Created skeleton in 0.000000 secs.
lola: CANCELED task # 67 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01 (obsolete)
lola: LAUNCH task # 76 (type FNDP) for 10 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 77 (type EQUN) for 10 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: LAUNCH task # 80 (type SRCH) for 10 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 67 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: FINISHED task # 80 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 72 (type FNDP) for 10 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: FINISHED task # 76 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: result : true
lola: fired transitions : 4095
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 77 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02 (obsolete)
lola: LAUNCH task # 81 (type FNDP) for 40 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
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lola: LAUNCH task # 82 (type EQUN) for 40 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
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lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: FINISHED task # 77 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: result : unknown
lola: FINISHED task # 72 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02
lola: result : true
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 84 (type SRCH) for 40 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
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lola: memory limit: 5 pages
sara: try reading problem file /home/mcc/execution/CTLFireability-82.sara.
lola: FINISHED task # 81 (type FNDP) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
lola: result : true
lola: fired transitions : 4095
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 82 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08 (obsolete)
lola: CANCELED task # 84 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08 (obsolete)
lola: FINISHED task # 84 (type SRCH) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
lola: result : unknown
lola: time used : 0.000000
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lola: FINISHED task # 82 (type EQUN) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08
lola: result : unknown
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
64 AGEF EXCL 5/257 21/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09 4714389 m, 942877 m/sec, 7828122 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: FINISHED task # 62 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15
lola: result : true
lola: markings : 1
lola: time used : 0.000000
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lola: LAUNCH task # 59 (type EXCL) for 58 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14
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lola: FINISHED task # 59 (type EXCL) for SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14
lola: result : false
lola: markings : 16385
lola: fired transitions : 32770
lola: time used : 0.000000
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lola: LAUNCH task # 53 (type EXCL) for 52 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12
lola: time limit : 326 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
53 CTL EXCL 5/326 19/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12 4280339 m, 856067 m/sec, 8544638 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: time limit : 358 sec
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/358 20/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07 4531775 m, 906355 m/sec, 9047534 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/396 15/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 3417588 m, 683517 m/sec, 10236659 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 10/396 28/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04 6584200 m, 633322 m/sec, 19736748 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 1 0 0 8 0 0 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 1 0 0 1 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/444 14/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03 3129256 m, 625851 m/sec, 9371633 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 10/444 26/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03 6027385 m, 579625 m/sec, 18066256 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/505 18/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00 4126274 m, 825254 m/sec, 8236503 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
70 AGEF EXCL 5/588 19/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02 4930932 m, 986186 m/sec, 9845878 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 1 0 0 1 0 0 0

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47 CTL EXCL 5/704 18/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10 4207214 m, 841442 m/sec, 8398382 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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50 CTL EXCL 5/877 15/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11 3463004 m, 692600 m/sec, 10372905 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

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50 CTL EXCL 10/877 29/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11 6681516 m, 643702 m/sec, 20028705 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 0 0 0 8 0 1 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 0 1 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
56 CTL EXCL 10/1165 28/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13 6652522 m, 640989 m/sec, 19941719 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 0 0 0 8 0 1 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: time limit : 1740 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 0 0 0 8 0 1 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 5/1740 15/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06 3521603 m, 704320 m/sec, 10548710 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 0 0 0 8 0 1 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
35 CTL EXCL 10/1740 29/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06 6816199 m, 658919 m/sec, 20432766 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 0 0 0 8 0 1 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/3465 14/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05 3251375 m, 650275 m/sec, 9738000 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 0 0 0 8 0 1 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/3465 27/32 SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05 6273291 m, 604383 m/sec, 18803993 t fired, .

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SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ 0 0 0 0 8 0 1 5
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL 0 0 0 0 1 0 1 0

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FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-01: CONJ false findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-02: DISJ unknown DISJ
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-03: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-05: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-06: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-07: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-08: EF true findpath
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-09: EFAG unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-10: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-12: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-13: CTL unknown AGGR
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-14: CTL false CTL model checker
SmallOperatingSystem-PT-MT8192DC4096-CTLFireability-15: CTL true CTL model checker


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT8192DC4096"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT8192DC4096, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r251-tall-162106741600146"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT8192DC4096.tgz
mv SmallOperatingSystem-PT-MT8192DC4096 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;