About the Execution of LoLA for SmallOperatingSystem-PT-MT4096DC2048
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 8983.808 | 200434.00 | 174314.00 | 567.50 | ??????????F?FF?T | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/data/fkordon/mcc2021-input.r251-tall-162106741600130.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
..................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is SmallOperatingSystem-PT-MT4096DC2048, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r251-tall-162106741600130
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 432K
-rw-r--r-- 1 mcc users 19K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 119K May 10 09:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 17K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 116K May 10 09:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.2K Mar 28 16:42 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 16:42 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.6K Mar 28 16:42 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 16:42 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.4K Mar 27 13:41 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 19K Mar 27 13:41 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Mar 25 19:28 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 14K Mar 25 19:28 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 2.1K Mar 22 08:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 4.1K Mar 22 08:16 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:52 equiv_col
-rw-r--r-- 1 mcc users 13 May 5 16:52 instance
-rw-r--r-- 1 mcc users 6 May 5 16:52 iscolored
-rw-r--r-- 1 mcc users 8.1K May 5 16:52 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14
FORMULA_NAME SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15
=== Now, execution of the tool begins
BK_START 1621120264971
starting LoLA
BK_INPUT SmallOperatingSystem-PT-MT4096DC2048
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621120465405
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:445
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:475
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 1 (type EXCL) for 0 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00
lola: time limit : 143 sec
lola: memory limit: 32 pages
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:753
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 5/211 14/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 3261670 m, 652334 m/sec, 9777347 t fired, .
Time elapsed: 6 secs. Pages in use: 14
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
1 CTL EXCL 10/211 27/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 6278913 m, 603448 m/sec, 18823417 t fired, .
Time elapsed: 11 secs. Pages in use: 27
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 1 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL 0 1 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 16 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 52 (type EXCL) for 34 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10
lola: time limit : 224 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10
lola: result : true
lola: markings : 4
lola: fired transitions : 3
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 50 (type EXCL) for 49 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15
lola: time limit : 238 sec
lola: memory limit: 32 pages
lola: FINISHED task # 50 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15
lola: result : true
lola: markings : 1
lola: fired transitions : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 47 (type EXCL) for 46 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14
lola: time limit : 256 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 5/256 17/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14 3937517 m, 787503 m/sec, 7867481 t fired, .
Time elapsed: 21 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 1 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
47 CTL EXCL 10/256 30/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14 7136634 m, 639823 m/sec, 14260086 t fired, .
Time elapsed: 26 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 47 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 31 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 44 (type EXCL) for 43 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13
lola: time limit : 274 sec
lola: memory limit: 32 pages
lola: FINISHED task # 44 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13
lola: result : false
lola: markings : 2
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 41 (type EXCL) for 40 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12
lola: time limit : 297 sec
lola: memory limit: 32 pages
lola: FINISHED task # 41 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12
lola: result : false
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 38 (type EXCL) for 37 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11
lola: time limit : 324 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
38 CTL EXCL 5/324 20/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11 4534753 m, 906950 m/sec, 9072289 t fired, .
Time elapsed: 36 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 38 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 41 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 32 (type EXCL) for 31 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09
lola: time limit : 355 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 5/355 5/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 1071535 m, 214307 m/sec, 7492719 t fired, .
Time elapsed: 46 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 10/355 9/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 2112026 m, 208098 m/sec, 14776325 t fired, .
Time elapsed: 51 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 15/355 14/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 3134059 m, 204406 m/sec, 21930724 t fired, .
Time elapsed: 56 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 20/355 18/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 4155503 m, 204288 m/sec, 29080999 t fired, .
Time elapsed: 61 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 25/355 22/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 5103891 m, 189677 m/sec, 35713724 t fired, .
Time elapsed: 66 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 30/355 26/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 6031543 m, 185530 m/sec, 42207432 t fired, .
Time elapsed: 71 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
32 CTL EXCL 35/355 30/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 6954619 m, 184615 m/sec, 48669118 t fired, .
Time elapsed: 76 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 32 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 81 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 26 (type EXCL) for 25 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07
lola: time limit : 391 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
26 CTL EXCL 5/391 19/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07 4377069 m, 875413 m/sec, 8740510 t fired, .
Time elapsed: 86 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 26 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 91 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 23 (type EXCL) for 22 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06
lola: time limit : 438 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 5/438 17/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06 3815804 m, 763160 m/sec, 7624035 t fired, .
Time elapsed: 96 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
23 CTL EXCL 10/438 30/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06 6986982 m, 634235 m/sec, 13960759 t fired, .
Time elapsed: 101 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 23 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 106 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 20 (type EXCL) for 19 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05
lola: time limit : 499 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 5/499 15/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 3525222 m, 705044 m/sec, 10568047 t fired, .
Time elapsed: 111 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
20 CTL EXCL 10/499 28/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 6524655 m, 599886 m/sec, 19560686 t fired, .
Time elapsed: 116 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 20 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 121 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 17 (type EXCL) for 16 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04
lola: time limit : 579 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
17 CTL EXCL 5/579 19/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04 4452499 m, 890499 m/sec, 8899578 t fired, .
Time elapsed: 126 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 17 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 131 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 14 (type EXCL) for 13 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03
lola: time limit : 693 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 5/693 18/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03 4206586 m, 841317 m/sec, 8759824 t fired, .
Time elapsed: 136 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 10/693 18/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03 4206586 m, 0 m/sec, 18909211 t fired, .
Time elapsed: 141 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
14 CTL EXCL 15/693 31/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03 7199766 m, 598636 m/sec, 26996570 t fired, .
Time elapsed: 146 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 14 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 151 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 11 (type EXCL) for 10 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02
lola: time limit : 862 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
11 CTL EXCL 5/862 19/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02 4428115 m, 885623 m/sec, 8842608 t fired, .
Time elapsed: 156 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 11 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 2 0 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 161 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 8 (type EXCL) for 3 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01
lola: time limit : 1146 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 5/1146 18/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 4206585 m, 841317 m/sec, 8816091 t fired, .
Time elapsed: 166 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 10/1146 18/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 4206585 m, 0 m/sec, 18987801 t fired, .
Time elapsed: 171 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 1 1 0 2 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
8 CTL EXCL 15/1146 31/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 7231258 m, 604934 m/sec, 27061600 t fired, .
Time elapsed: 176 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 8 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 1 0 0 2 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 181 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 6 (type EXCL) for 3 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01
lola: time limit : 1709 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 0 1 0 2 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
6 CTL EXCL 5/1709 20/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 4626880 m, 925376 m/sec, 9240172 t fired, .
Time elapsed: 186 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 6 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 191 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: LAUNCH task # 29 (type EXCL) for 28 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08
lola: time limit : 3409 sec
lola: memory limit: 32 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 0 1 0 1 0 0 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
29 CTL EXCL 5/3409 20/32 SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08 4583103 m, 916620 m/sec, 9152615 t fired, .
Time elapsed: 196 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: CANCELED task # 29 (type EXCL) for SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08 (memory limit exceeded)
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ 0 0 0 0 2 0 2 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL 0 0 0 0 1 0 1 0
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL 0 0 0 0 1 0 1 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
Time elapsed: 201 secs. Pages in use: 32
# running tasks: 1 of 4 Visible: 16
lola: Portfolio finished: no open tasks 16
FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-00: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-01: CONJ unknown CONJ
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-02: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-03: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-04: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-05: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-06: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-07: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-08: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-09: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-10: AXAG false state space /EXEF
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-11: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-12: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-13: CTL false CTL model checker
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-14: CTL unknown AGGR
SmallOperatingSystem-PT-MT4096DC2048-CTLFireability-15: CTL true CTL model checker
Time elapsed: 201 secs. Pages in use: 32
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="SmallOperatingSystem-PT-MT4096DC2048"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is SmallOperatingSystem-PT-MT4096DC2048, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r251-tall-162106741600130"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/SmallOperatingSystem-PT-MT4096DC2048.tgz
mv SmallOperatingSystem-PT-MT4096DC2048 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;