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Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r175-tajo-162089412000746
Last Updated
Jun 28, 2021

About the Execution of LoLA for ResAllocation-PT-R003C015

Execution Summary
Max Memory
Used (MB)		 Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
3023.520 150532.00 291026.00 32.50 FF?F???TFFTTTFF? normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2021-input.r175-tajo-162089412000746.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.........................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is ResAllocation-PT-R003C015, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r175-tajo-162089412000746
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 460K
-rw-r--r-- 1 mcc users 12K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 99K May 10 09:44 CTLCardinality.xml
-rw-r--r-- 1 mcc users 11K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 89K May 10 09:44 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.7K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.7K Mar 28 16:32 LTLCardinality.txt
-rw-r--r-- 1 mcc users 25K Mar 28 16:32 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.1K Mar 28 16:32 LTLFireability.txt
-rw-r--r-- 1 mcc users 15K Mar 28 16:32 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.5K Mar 27 10:55 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 10:55 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.1K Mar 25 14:02 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 25 14:02 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.8K Mar 22 08:15 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.8K Mar 22 08:15 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 9 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 107K May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-00
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-01
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-02
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-03
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-04
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-05
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-06
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-07
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-08
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-09
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-10
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-11
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-12
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-13
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-14
FORMULA_NAME ResAllocation-PT-R003C015-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1621095991502

starting LoLA
BK_INPUT ResAllocation-PT-R003C015
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA ResAllocation-PT-R003C015-CTLFireability-13 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-00 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-01 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-03 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-14 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-11 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-12 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-07 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-10 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA ResAllocation-PT-R003C015-CTLFireability-09 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1621096142034

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:400
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:397
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:340
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:457
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:553
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:454
lola: rewrite Frontend/Parser/formula_rewrite.k:451
lola: rewrite Frontend/Parser/formula_rewrite.k:460
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:550
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Rule S: 0 transitions removed,0 places removed
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: LAUNCH task # 52 (type EXCL) for 51 ResAllocation-PT-R003C015-CTLFireability-13
lola: time limit : 150 sec
lola: memory limit: 32 pages
lola: FINISHED task # 52 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-13
lola: result : false
lola: markings : 30
lola: fired transitions : 31
lola: time used : 0.000000
lola: memory pages used : 1
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: Created skeleton in 0.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 1 (type EXCL) for 0 ResAllocation-PT-R003C015-CTLFireability-00
lola: time limit : 180 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: FINISHED task # 1 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-00
lola: result : false
lola: markings : 543
lola: fired transitions : 1547
lola: time used : 0.000000
lola: memory pages used : 1
lola: LAUNCH task # 4 (type EXCL) for 3 ResAllocation-PT-R003C015-CTLFireability-01
lola: time limit : 189 sec
lola: memory limit: 32 pages
lola: FINISHED task # 4 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-01
lola: result : false
lola: markings : 4
lola: fired transitions : 6
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: LAUNCH task # 10 (type EXCL) for 9 ResAllocation-PT-R003C015-CTLFireability-03
lola: time limit : 200 sec
lola: memory limit: 32 pages
lola: FINISHED task # 10 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-03
lola: result : false
lola: markings : 69
lola: fired transitions : 261
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: LAUNCH task # 29 (type EXCL) for 18 ResAllocation-PT-R003C015-CTLFireability-06
lola: time limit : 211 sec
lola: memory limit: 32 pages
lola: FINISHED task # 29 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-06
lola: result : true
lola: markings : 1
lola: time used : 0.000000
lola: memory pages used : 1
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:703
lola: LAUNCH task # 46 (type EXCL) for 45 ResAllocation-PT-R003C015-CTLFireability-11
lola: time limit : 257 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:810
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:661
lola: rewrite Frontend/Parser/formula_rewrite.k:666
lola: rewrite Frontend/Parser/formula_rewrite.k:659
lola: rewrite Frontend/Parser/formula_rewrite.k:662
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:668
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:679
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: LAUNCH task # 71 (type FNDP) for 54 ResAllocation-PT-R003C015-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 72 (type EQUN) for 54 ResAllocation-PT-R003C015-CTLFireability-14
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lola: LAUNCH task # 74 (type SRCH) for 54 ResAllocation-PT-R003C015-CTLFireability-14
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:788
lola: FINISHED task # 74 (type SRCH) for ResAllocation-PT-R003C015-CTLFireability-14
lola: result : unknown
lola: time used : 0.000000
lola: memory pages used : 1
lola: FINISHED task # 71 (type FNDP) for ResAllocation-PT-R003C015-CTLFireability-14
lola: result : true
lola: fired transitions : 1
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: CANCELED task # 72 (type EQUN) for ResAllocation-PT-R003C015-CTLFireability-14 (obsolete)
lola: FINISHED task # 46 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-11
lola: result : true
lola: markings : 7394
lola: fired transitions : 33941
lola: time used : 0.000000
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lola: LAUNCH task # 66 (type EXCL) for 65 ResAllocation-PT-R003C015-CTLFireability-15
lola: time limit : 360 sec
lola: memory limit: 32 pages
sara: try reading problem file /home/mcc/execution/CTLFireability-72.sara.
sara: place or transition ordering is non-deterministic
sara: warning, failure of lp_solve (at job 2)
sara: warning, failure of lp_solve (at job 2)
sara: warning, failure of lp_solve (at job 2)
sara: warning, failure of lp_solve (at job 159)
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 1 0 0 5 0 0 2
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
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ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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66 CTL EXCL 5/360 8/32 ResAllocation-PT-R003C015-CTLFireability-15 1725799 m, 345159 m/sec, 10183853 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 1 0 0 5 0 0 2
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ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
66 CTL EXCL 10/360 15/32 ResAllocation-PT-R003C015-CTLFireability-15 3425399 m, 339920 m/sec, 20661360 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 1 0 0 5 0 0 2
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ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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66 CTL EXCL 15/360 22/32 ResAllocation-PT-R003C015-CTLFireability-15 5033988 m, 321717 m/sec, 30976984 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 1 0 0 5 0 0 2
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ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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66 CTL EXCL 20/360 28/32 ResAllocation-PT-R003C015-CTLFireability-15 6645123 m, 322227 m/sec, 41186399 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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ResAllocation-PT-R003C015-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 1 0 0 5 0 0 2
ResAllocation-PT-R003C015-CTLFireability-07: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-08: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-12: CTL 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: time limit : 397 sec
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lola: FINISHED task # 49 (type EXCL) for ResAllocation-PT-R003C015-CTLFireability-12
lola: result : true
lola: markings : 326
lola: fired transitions : 463
lola: time used : 0.000000
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lola: result : false
lola: markings : 365
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lola: result : true
lola: markings : 812850
lola: fired transitions : 6262646
lola: time used : 3.000000
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lola: time limit : 595 sec
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-CTLFireability-00: CTL false CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-03: CTL false CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
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PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
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ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 0 1 0 5 0 0 2
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 2/595 3/32 ResAllocation-PT-R003C015-CTLFireability-06 643173 m, 128634 m/sec, 4247944 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
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21 CTL EXCL 7/595 10/32 ResAllocation-PT-R003C015-CTLFireability-06 2291118 m, 329589 m/sec, 15778320 t fired, .

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21 CTL EXCL 12/595 16/32 ResAllocation-PT-R003C015-CTLFireability-06 3711019 m, 283980 m/sec, 26362904 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 0 1 0 5 0 0 2
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
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TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
21 CTL EXCL 22/595 28/32 ResAllocation-PT-R003C015-CTLFireability-06 6563643 m, 248448 m/sec, 47544430 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL true CTL model checker
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ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-02: CTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 0 0 0 5 0 1 2
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
7 CTL EXCL 20/873 27/32 ResAllocation-PT-R003C015-CTLFireability-02 6425882 m, 305932 m/sec, 45698137 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-01: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-04: SP ECTL 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 0 0 0 5 0 1 2
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-01: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 0 0 0 5 0 1 2
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 LTL EXCL 5/1156 12/32 ResAllocation-PT-R003C015-CTLFireability-04 1757689 m, 351537 m/sec, 10190530 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-01: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 0 0 0 5 0 1 2
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 LTL EXCL 10/1156 22/32 ResAllocation-PT-R003C015-CTLFireability-04 3334607 m, 315383 m/sec, 20561162 t fired, .

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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-01: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-04: SP ECTL 0 0 1 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 0 0 0 5 0 1 2
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
69 LTL EXCL 15/1156 31/32 ResAllocation-PT-R003C015-CTLFireability-04 4758056 m, 284689 m/sec, 29906054 t fired, .

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ResAllocation-PT-R003C015-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-01: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CONJ false findpath

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
ResAllocation-PT-R003C015-CTLFireability-02: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-04: SP ECTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-05: CTL 0 0 0 0 1 0 1 0
ResAllocation-PT-R003C015-CTLFireability-06: CONJ 0 0 0 0 5 0 1 2
ResAllocation-PT-R003C015-CTLFireability-09: AGEF 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-10: EG 0 1 0 0 1 0 0 0
ResAllocation-PT-R003C015-CTLFireability-15: CTL 0 0 0 0 1 0 1 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

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lola: result : true
lola: markings : 3
lola: fired transitions : 3
lola: time used : 0.000000
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lola: time limit : 3450 sec
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lola: result : false
lola: markings : 40
lola: fired transitions : 47
lola: time used : 0.000000
lola: memory pages used : 1
lola: Portfolio finished: no open tasks 16

FINAL RESULTS
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
ResAllocation-PT-R003C015-CTLFireability-00: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-01: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-02: CTL unknown AGGR
ResAllocation-PT-R003C015-CTLFireability-03: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-04: SP ECTL unknown AGGR
ResAllocation-PT-R003C015-CTLFireability-05: CTL unknown AGGR
ResAllocation-PT-R003C015-CTLFireability-06: CONJ unknown CONJ
ResAllocation-PT-R003C015-CTLFireability-07: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-08: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-09: AGEF false tscc_search
ResAllocation-PT-R003C015-CTLFireability-10: EG true state space / EG
ResAllocation-PT-R003C015-CTLFireability-11: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-12: CTL true CTL model checker
ResAllocation-PT-R003C015-CTLFireability-13: CTL false CTL model checker
ResAllocation-PT-R003C015-CTLFireability-14: CONJ false findpath
ResAllocation-PT-R003C015-CTLFireability-15: CTL unknown AGGR


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Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="ResAllocation-PT-R003C015"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is ResAllocation-PT-R003C015, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r175-tajo-162089412000746"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/ResAllocation-PT-R003C015.tgz
mv ResAllocation-PT-R003C015 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;