About the Execution of LoLA for RERS17pb113-PT-4
| Execution Summary | |||||
| Max Memory Used (MB) |
Time wait (ms) | CPU Usage (ms) | I/O Wait (ms) | Computed Result | Execution Status |
| 16012.747 | 301755.00 | 853592.00 | 67.40 | ??T?FF??FTF????? | normal |
Execution Chart
We display below the execution chart for this examination (boot time has been removed).
Trace from the execution
Formatting '/mnt/tpsp/fkordon/mcc2021-input.r175-tajo-162089411000150.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
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=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is RERS17pb113-PT-4, examination is ReachabilityCardinality
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r175-tajo-162089411000150
=====================================================================
--------------------
preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 13K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 115K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 17K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 79K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.4K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 3.1K Mar 28 16:28 LTLCardinality.txt
-rw-r--r-- 1 mcc users 24K Mar 28 16:28 LTLCardinality.xml
-rw-r--r-- 1 mcc users 2.8K Mar 28 16:28 LTLFireability.txt
-rw-r--r-- 1 mcc users 19K Mar 28 16:28 LTLFireability.xml
-rw-r--r-- 1 mcc users 3.4K Mar 27 10:03 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 17K Mar 27 10:03 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 3.0K Mar 25 13:11 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 13K Mar 25 13:11 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.6K Mar 22 08:13 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.6K Mar 22 08:13 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 2 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 15M May 5 16:51 model.pnml
--------------------
content from stdout:
=== Data for post analysis generated by BenchKit (invocation template)
The expected result is a vector of booleans
BOOL_VECTOR
here is the order used to build the result vector(from text file)
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-00
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-01
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-02
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-03
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-04
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-05
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-06
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-07
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-08
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-09
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-10
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-11
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-12
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-13
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-14
FORMULA_NAME RERS17pb113-PT-4-ReachabilityCardinality-15
=== Now, execution of the tool begins
BK_START 1621068645628
starting LoLA
BK_INPUT RERS17pb113-PT-4
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality
FORMULA RERS17pb113-PT-4-ReachabilityCardinality-05 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-4-ReachabilityCardinality-04 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-4-ReachabilityCardinality-08 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-4-ReachabilityCardinality-10 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-4-ReachabilityCardinality-09 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
FORMULA RERS17pb113-PT-4-ReachabilityCardinality-02 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT
BK_STOP 1621068947383
--------------------
content from stderr:
lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/ReachabilityCardinality.xml
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
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RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-04: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-05: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-08: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 0 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 0 0 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
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RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 0 0 0 0
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sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-54.sara.
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-04: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-05: AG 0 1 4 0 0 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
49 EF FNDP 7/555 0/5 RERS17pb113-PT-4-ReachabilityCardinality-05 328 t fired, 1 attempts, .
54 EF STEQ 7/667 0/5 RERS17pb113-PT-4-ReachabilityCardinality-05 sara is running.
58 EF SRCH 7/667 1/5 RERS17pb113-PT-4-ReachabilityCardinality-05 367 m, 73 m/sec, 366 t fired, .
59 EF EXCL 7/196 1/32 RERS17pb113-PT-4-ReachabilityCardinality-05 296 m, 59 m/sec, 296 t fired, .
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lola: FINISHED task # 49 (type FNDP) for RERS17pb113-PT-4-ReachabilityCardinality-05
lola: result : true
lola: fired transitions : 685
lola: tried executions : 1
lola: time used : 10.000000
lola: memory pages used : 0
lola: CANCELED task # 54 (type EQUN) for RERS17pb113-PT-4-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 58 (type SRCH) for RERS17pb113-PT-4-ReachabilityCardinality-05 (obsolete)
lola: CANCELED task # 59 (type EXCL) for RERS17pb113-PT-4-ReachabilityCardinality-05 (obsolete)
lola: LAUNCH task # 65 (type EXCL) for 0 RERS17pb113-PT-4-ReachabilityCardinality-00
lola: time limit : 222 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 67 (type FNDP) for 12 RERS17pb113-PT-4-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 70 (type EQUN) for 12 RERS17pb113-PT-4-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 73 (type SRCH) for 12 RERS17pb113-PT-4-ReachabilityCardinality-04
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 54 (type EQUN) for RERS17pb113-PT-4-ReachabilityCardinality-05
lola: result : unknown
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-70.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-4-ReachabilityCardinality-05: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-04: AG 0 2 3 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF EXCL 2/222 1/32 RERS17pb113-PT-4-ReachabilityCardinality-00 259 m, 51 m/sec, 258 t fired, .
67 EF FNDP 2/834 0/5 RERS17pb113-PT-4-ReachabilityCardinality-04 85 t fired, 1 attempts, .
70 EF STEQ 2/834 0/5 RERS17pb113-PT-4-ReachabilityCardinality-04 sara is running.
73 EF SRCH 2/834 1/5 RERS17pb113-PT-4-ReachabilityCardinality-04 58 m, 11 m/sec, 57 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-4-ReachabilityCardinality-05: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-04: AG 0 2 3 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-08: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 0 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 0 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF EXCL 7/222 1/32 RERS17pb113-PT-4-ReachabilityCardinality-00 632 m, 74 m/sec, 631 t fired, .
67 EF FNDP 7/832 0/5 RERS17pb113-PT-4-ReachabilityCardinality-04 630 t fired, 1 attempts, .
70 EF STEQ 7/832 0/5 RERS17pb113-PT-4-ReachabilityCardinality-04 sara is running.
73 EF SRCH 7/832 1/5 RERS17pb113-PT-4-ReachabilityCardinality-04 474 m, 83 m/sec, 473 t fired, .
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lola: Created skeleton in 18.000000 secs.
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-4-ReachabilityCardinality-05: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-04: AG 0 2 3 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-08: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF EXCL 12/222 1/32 RERS17pb113-PT-4-ReachabilityCardinality-00 885 m, 50 m/sec, 884 t fired, .
67 EF FNDP 12/156 0/5 RERS17pb113-PT-4-ReachabilityCardinality-04 1689 t fired, 1 attempts, .
70 EF STEQ 12/156 0/5 RERS17pb113-PT-4-ReachabilityCardinality-04 sara is running.
73 EF SRCH 12/156 1/5 RERS17pb113-PT-4-ReachabilityCardinality-04 1308 m, 166 m/sec, 1307 t fired, .
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FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-4-ReachabilityCardinality-05: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-04: AG 0 2 3 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-08: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF EXCL 17/222 1/32 RERS17pb113-PT-4-ReachabilityCardinality-00 1280 m, 79 m/sec, 1279 t fired, .
67 EF FNDP 17/154 0/5 RERS17pb113-PT-4-ReachabilityCardinality-04 3121 t fired, 1 attempts, .
70 EF STEQ 17/154 0/5 RERS17pb113-PT-4-ReachabilityCardinality-04 sara is running.
73 EF SRCH 17/154 1/5 RERS17pb113-PT-4-ReachabilityCardinality-04 2744 m, 287 m/sec, 2743 t fired, .
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lola: FINISHED task # 73 (type SRCH) for RERS17pb113-PT-4-ReachabilityCardinality-04
lola: result : true
lola: markings : 3154
lola: fired transitions : 3153
lola: time used : 19.000000
lola: memory pages used : 1
lola: CANCELED task # 67 (type FNDP) for RERS17pb113-PT-4-ReachabilityCardinality-04 (obsolete)
lola: CANCELED task # 70 (type EQUN) for RERS17pb113-PT-4-ReachabilityCardinality-04 (obsolete)
lola: LAUNCH task # 101 (type FNDP) for 24 RERS17pb113-PT-4-ReachabilityCardinality-08
lola: time limit : 32000000 sec
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lola: LAUNCH task # 102 (type EQUN) for 24 RERS17pb113-PT-4-ReachabilityCardinality-08
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lola: LAUNCH task # 104 (type SRCH) for 24 RERS17pb113-PT-4-ReachabilityCardinality-08
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 70 (type EQUN) for RERS17pb113-PT-4-ReachabilityCardinality-04
lola: result : unknown
lola: FINISHED task # 67 (type FNDP) for RERS17pb113-PT-4-ReachabilityCardinality-04
lola: result : unknown
lola: fired transitions : 3538
lola: tried executions : 2
lola: time used : 19.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
sara: try reading problem file /home/mcc/execution/ReachabilityCardinality-102.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-4-ReachabilityCardinality-04: AG false tandem / insertion
RERS17pb113-PT-4-ReachabilityCardinality-05: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-08: AG 0 2 3 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-10: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF EXCL 22/238 1/32 RERS17pb113-PT-4-ReachabilityCardinality-00 1732 m, 90 m/sec, 1731 t fired, .
101 EF FNDP 3/174 0/5 RERS17pb113-PT-4-ReachabilityCardinality-08 829 t fired, 1 attempts, .
102 EF STEQ 3/174 0/5 RERS17pb113-PT-4-ReachabilityCardinality-08 sara is running.
104 EF SRCH 3/184 1/5 RERS17pb113-PT-4-ReachabilityCardinality-08 834 m, 166 m/sec, 833 t fired, .
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lola: FINISHED task # 104 (type SRCH) for RERS17pb113-PT-4-ReachabilityCardinality-08
lola: result : true
lola: markings : 1410
lola: fired transitions : 1409
lola: time used : 5.000000
lola: memory pages used : 1
lola: CANCELED task # 101 (type FNDP) for RERS17pb113-PT-4-ReachabilityCardinality-08 (obsolete)
lola: CANCELED task # 102 (type EQUN) for RERS17pb113-PT-4-ReachabilityCardinality-08 (obsolete)
lola: LAUNCH task # 82 (type FNDP) for 30 RERS17pb113-PT-4-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 84 (type EQUN) for 30 RERS17pb113-PT-4-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 86 (type SRCH) for 30 RERS17pb113-PT-4-ReachabilityCardinality-10
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 102 (type EQUN) for RERS17pb113-PT-4-ReachabilityCardinality-08
lola: result : unknown
lola: FINISHED task # 101 (type FNDP) for RERS17pb113-PT-4-ReachabilityCardinality-08
lola: result : unknown
lola: fired transitions : 1380
lola: tried executions : 2
lola: time used : 5.000000
lola: memory pages used : 0
lola: rewrite Frontend/Parser/formula_rewrite.k:721
lola: rewrite Frontend/Parser/formula_rewrite.k:787
lola: FINISHED task # 84 (type EQUN) for RERS17pb113-PT-4-ReachabilityCardinality-10
lola: result : unknown
lola: LAUNCH task # 93 (type FNDP) for 39 RERS17pb113-PT-4-ReachabilityCardinality-13
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 82 (type FNDP) for RERS17pb113-PT-4-ReachabilityCardinality-10
lola: result : true
lola: fired transitions : 149
lola: tried executions : 1
lola: time used : 1.000000
lola: memory pages used : 0
lola: CANCELED task # 86 (type SRCH) for RERS17pb113-PT-4-ReachabilityCardinality-10 (obsolete)
lola: LAUNCH task # 95 (type FNDP) for 27 RERS17pb113-PT-4-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 96 (type EQUN) for 27 RERS17pb113-PT-4-ReachabilityCardinality-09
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 96 (type EQUN) for RERS17pb113-PT-4-ReachabilityCardinality-09
lola: result : unknown
lola: LAUNCH task # 113 (type FNDP) for 36 RERS17pb113-PT-4-ReachabilityCardinality-12
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-4-ReachabilityCardinality-04: AG false tandem / insertion
RERS17pb113-PT-4-ReachabilityCardinality-05: AG false findpath
RERS17pb113-PT-4-ReachabilityCardinality-08: AG false tandem / insertion
RERS17pb113-PT-4-ReachabilityCardinality-10: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 3 1 0 2 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF EXCL 27/278 1/32 RERS17pb113-PT-4-ReachabilityCardinality-00 2227 m, 99 m/sec, 2226 t fired, .
93 EF FNDP 2/219 0/5 RERS17pb113-PT-4-ReachabilityCardinality-13 540 t fired, 1 attempts, .
95 EF FNDP 2/205 0/5 RERS17pb113-PT-4-ReachabilityCardinality-09 542 t fired, 1 attempts, .
113 EF FNDP 1/206 0/5 RERS17pb113-PT-4-ReachabilityCardinality-12 295 t fired, 1 attempts, .
Time elapsed: 291 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
RERS17pb113-PT-4-ReachabilityCardinality-04: AG false tandem / insertion
RERS17pb113-PT-4-ReachabilityCardinality-05: AG false findpath
RERS17pb113-PT-4-ReachabilityCardinality-08: AG false tandem / insertion
RERS17pb113-PT-4-ReachabilityCardinality-10: AG false findpath
PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
RERS17pb113-PT-4-ReachabilityCardinality-00: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-01: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-02: EF 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-03: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-06: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-07: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-09: EF 0 3 1 0 2 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-11: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-12: AG 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-13: EF 0 4 1 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-14: AG 0 5 0 0 1 0 0 0
RERS17pb113-PT-4-ReachabilityCardinality-15: EF 0 5 0 0 1 0 0 0
TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS
65 EF EXCL 32/278 1/32 RERS17pb113-PT-4-ReachabilityCardinality-00 2641 m, 82 m/sec, 2640 t fired, .
93 EF FNDP 7/218 0/5 RERS17pb113-PT-4-ReachabilityCardinality-13 1757 t fired, 1 attempts, .
95 EF FNDP 7/204 0/5 RERS17pb113-PT-4-ReachabilityCardinality-09 1861 t fired, 1 attempts, .
113 EF FNDP 6/205 0/5 RERS17pb113-PT-4-ReachabilityCardinality-12 1071 t fired, 1 attempts, .
Time elapsed: 296 secs. Pages in use: 2
# running tasks: 4 of 4 Visible: 16
lola: FINISHED task # 95 (type FNDP) for RERS17pb113-PT-4-ReachabilityCardinality-09
lola: result : true
lola: fired transitions : 3023
lola: tried executions : 1
lola: time used : 12.000000
lola: memory pages used : 0
lola: LAUNCH task # 143 (type FNDP) for 6 RERS17pb113-PT-4-ReachabilityCardinality-02
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: FINISHED task # 143 (type FNDP) for RERS17pb113-PT-4-ReachabilityCardinality-02
lola: result : true
lola: fired transitions : 11
lola: tried executions : 1
lola: time used : 0.000000
lola: memory pages used : 0
lola: LAUNCH task # 51 (type FNDP) for 9 RERS17pb113-PT-4-ReachabilityCardinality-03
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 399 Killed lola --conf=$BIN_DIR/configfiles/reachabilitycardinalityconf --formula=$DIR/ReachabilityCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml
Sequence of Actions to be Executed by the VM
This is useful if one wants to reexecute the tool in the VM from the submitted image disk.
set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-4"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"
# this is specific to your benchmark or test
export BIN_DIR="$HOME/BenchKit/bin"
# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi
# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-4, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r175-tajo-162089411000150"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"
tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-4.tgz
mv RERS17pb113-PT-4 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh
echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;