MCC'2021- Execution of r175-tajo-162089411000134

About the Execution of LoLA for RERS17pb113-PT-2

Execution Summary
Max Memory Used (MB)	Time wait (ms)	CPU Usage (ms)	I/O Wait (ms)	Computed Result	Execution Status
16172.535	315567.00	810064.00	503.30	T??FFF???TF?T???	normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/mnt/tpsp/fkordon/mcc2021-input.r175-t
Waiting for the VM to be ready (probing ssh)
............................................
======================
Generated by BenchKit 2-4028
Executing tool lola
Input is RERS17pb113-PT-2, examination
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r175-tajo-162089411000
============================================

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preparation of the directory to be used:
/home/mcc/execution
total 15M
-rw-r--r-- 1 mcc users 13K May 5
-rw-r--r-- 1 mcc users 113K May 10
-rw-r--r-- 1 mcc users 18K May 5
-rw-r--r-- 1 mcc users 89K May 10
-rw-r--r-- 1 mcc users 4.2K May 6
-rw-r--r-- 1 mcc users 6.4K May 6
-rw-r--r-- 1 mcc users 3.3K Mar 28
-rw-r--r-- 1 mcc users 25K Mar 28
-rw-r--r-- 1 mcc users 2.7K Mar 28
-rw-r--r-- 1 mcc users 17K Mar 28
-rw-r--r-- 1 mcc users 3.4K Mar 27
-rw-r--r-- 1 mcc users 17K Mar 27
-rw-r--r-- 1 mcc users 3.1K Mar 25
-rw-r--r-- 1 mcc users 14K Mar 25
-rw-r--r-- 1 mcc users 1.6K Mar 22
-rw-r--r-- 1 mcc users 3.6K Mar 22
-rw-r--r-- 1 mcc users 6 May 5
-rw-r--r-- 1 mcc users 2 May 5
-rw-r--r-- 1 mcc users 6 May 5
-rw-r--r-- 1 mcc users 15M May 5

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content from stdout:

=== Data for post analysis generated

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa
FORMULA_NAME RERS17pb113-PT-2-ReachabilityCa

=== Now, execution of the tool begins

BK_START 1621068017615

starting LoLA
BK_INPUT RERS17pb113-PT-2
BK_EXAMINATION: ReachabilityCardinality
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
ReachabilityCardinality

FORMULA RERS17pb113-PT-2-ReachabilityCardinality-10

FORMULA RERS17pb113-PT-2-ReachabilityCardinality-05

FORMULA RERS17pb113-PT-2-ReachabilityCardinality-03

FORMULA RERS17pb113-PT-2-ReachabilityCardinality-09

FORMULA RERS17pb113-PT-2-ReachabilityCardinality-12

FORMULA RERS17pb113-PT-2-ReachabilityCardinality-00

FORMULA RERS17pb113-PT-2-ReachabilityCardinality-04

BK_STOP 1621068333182

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content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution
lola: reading pnml
lola: PNML file contains place/transition
lola: finished parsing
lola: closed net file /home/mcc/execution/
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execu
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lola: rewrite Frontend/Parser/formula_rewr
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lola: rewrite Frontend/Parser/formula_rewr
lola: rewrite Frontend/Parser/formula_rewr
lola: rewrite Frontend/Parser/formula_rewr
lola: rewrite Frontend/Parser/formula_rewr
lola: rewrite Frontend/Parser/formula_rewr
lola: rewrite Frontend/Parser/formula_rewr
lola: rewrite Frontend/Parser/formula_rewr
lola: rewrite Frontend/Parser/formula_rewr
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lola: rewrite Frontend/Parser/formula_rewr
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/home/mcc/BenchKit/BenchKit_head.sh: line 62:
ajo-162089411000134.qcow2', fmt=qcow2 size=4294967296 backing_file='/mnt/tpsp/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off ............................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... =============================================== is ReachabilityCardinality 134 ========================= 16:58 CTLCardinality.txt 09:43 CTLCardinality.xml 16:58 CTLFireability.txt 09:43 CTLFireability.xml 14:48 GenericPropertiesDefinition.xml 14:48 GenericPropertiesVerdict.xml 16:28 LTLCardinality.txt 16:28 LTLCardinality.xml 16:28 LTLFireability.txt 16:28 LTLFireability.xml 10:02 ReachabilityCardinality.txt 10:02 ReachabilityCardinality.xml 13:10 ReachabilityFireability.txt 13:10 ReachabilityFireability.xml 08:13 UpperBounds.txt 08:13 UpperBounds.xml 16:51 equiv_col 16:51 instance 16:51 iscolored 16:51 model.pnml by BenchKit (invocation template) result vector(from text file) rdinality-00 rdinality-01 rdinality-02 rdinality-03 rdinality-04 rdinality-05 rdinality-06 rdinality-07 rdinality-08 rdinality-09 rdinality-10 rdinality-11 rdinality-12 rdinality-13 rdinality-14 rdinality-15 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT /model.pnml net model.pnml tion/ReachabilityCardinality.xml VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 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0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 0 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 0 0 0 0 EF 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 AG 0 0 0 0 1 0 0 0 EF 0 0 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 for 30 RERS17pb113-PT-2-ReachabilityCardinality-10 for 30 RERS17pb113-PT-2-ReachabilityCardinality-10 for 30 RERS17pb113-PT-2-ReachabilityCardinality-10 for 30 RERS17pb113-PT-2-ReachabilityCardinality-10 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:711 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:711 ite.k:711 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:721 ite.k:787 ite.k:711 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:711 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:711 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:711 ite.k:721 ite.k:787 ite.k:711 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:721 ite.k:787 ite.k:711 ite.k:721 ite.k:787 ite.k:711 ite.k:711 ite.k:721 ite.k:787 VALUE PRODUCED BY IDL ACT RUN SUS FIN C/T C/M OBS EF 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 1 4 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 RERS17pb113-PT-2-ReachabilityCardinality-10 -- 0/5 RERS17pb113-PT-2-ReachabilityCardinality-10 sara not yet started (preprocessing). 1/5 RERS17pb113-PT-2-ReachabilityCardinality-10 -- 1/32 RERS17pb113-PT-2-ReachabilityCardinality-10 -- cution/ReachabilityCardinality-57.sara. for RERS17pb113-PT-2-ReachabilityCardinality-10 868 867 5.000000 1 for RERS17pb113-PT-2-ReachabilityCardinality-10 (obsolete) for RERS17pb113-PT-2-ReachabilityCardinality-10 (obsolete) for RERS17pb113-PT-2-ReachabilityCardinality-10 (obsolete) for 39 RERS17pb113-PT-2-ReachabilityCardinality-13 for 15 RERS17pb113-PT-2-ReachabilityCardinality-05 for 15 RERS17pb113-PT-2-ReachabilityCardinality-05 for 15 RERS17pb113-PT-2-ReachabilityCardinality-05 ite.k:721 ite.k:787 for RERS17pb113-PT-2-ReachabilityCardinality-10 for RERS17pb113-PT-2-ReachabilityCardinality-10 852 2 5.000000 0 VALUE PRODUCED BY AG false tandem / insertion IDL ACT RUN SUS FIN C/T C/M OBS EF 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 2 3 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 RERS17pb113-PT-2-ReachabilityCardinality-05 49 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-05 sara not yet started (preprocessing). 1/5 RERS17pb113-PT-2-ReachabilityCardinality-05 57 m, 11 m/sec, 56 t fired, . 1/32 RERS17pb113-PT-2-ReachabilityCardinality-13 127 m, 25 m/sec, 126 t fired, . for RERS17pb113-PT-2-ReachabilityCardinality-05 101 100 1.000000 1 for RERS17pb113-PT-2-ReachabilityCardinality-05 (obsolete) for RERS17pb113-PT-2-ReachabilityCardinality-05 (obsolete) for 9 RERS17pb113-PT-2-ReachabilityCardinality-03 for 9 RERS17pb113-PT-2-ReachabilityCardinality-03 for 9 RERS17pb113-PT-2-ReachabilityCardinality-03 ite.k:721 ite.k:787 for RERS17pb113-PT-2-ReachabilityCardinality-05 91 2 1.000000 0 cution/ReachabilityCardinality-96.sara. for RERS17pb113-PT-2-ReachabilityCardinality-03 for 36 RERS17pb113-PT-2-ReachabilityCardinality-12 for RERS17pb113-PT-2-ReachabilityCardinality-03 296 1 2.000000 0 for RERS17pb113-PT-2-ReachabilityCardinality-03 (obsolete) for 27 RERS17pb113-PT-2-ReachabilityCardinality-09 for 27 RERS17pb113-PT-2-ReachabilityCardinality-09 ite.k:711 for RERS17pb113-PT-2-ReachabilityCardinality-09 for 42 RERS17pb113-PT-2-ReachabilityCardinality-14 for RERS17pb113-PT-2-ReachabilityCardinality-09 139 1 1.000000 0 for 3 RERS17pb113-PT-2-ReachabilityCardinality-01 VALUE PRODUCED BY AG false findpath AG false tandem / insertion EF true findpath AG false tandem / insertion IDL ACT RUN SUS FIN C/T C/M OBS EF 0 5 0 0 1 0 0 0 EF 0 4 1 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 EF 0 4 1 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 RERS17pb113-PT-2-ReachabilityCardinality-14 251 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-01 294 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-12 753 t fired, 1 attempts, . 1/32 RERS17pb113-PT-2-ReachabilityCardinality-13 654 m, 105 m/sec, 653 t fired, . VALUE PRODUCED BY AG false findpath AG false tandem / insertion EF true findpath AG false tandem / insertion IDL ACT RUN SUS FIN C/T C/M OBS EF 0 5 0 0 1 0 0 0 EF 0 4 1 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 EF 0 4 1 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 RERS17pb113-PT-2-ReachabilityCardinality-14 1379 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-01 1303 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-12 1796 t fired, 1 attempts, . 1/32 RERS17pb113-PT-2-ReachabilityCardinality-13 2063 m, 281 m/sec, 2062 t fired, . VALUE PRODUCED BY AG false findpath AG false tandem / insertion EF true findpath AG false tandem / insertion IDL ACT RUN SUS FIN C/T C/M OBS EF 0 5 0 0 1 0 0 0 EF 0 4 1 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 EF 0 4 1 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 RERS17pb113-PT-2-ReachabilityCardinality-14 2523 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-01 2379 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-12 2849 t fired, 1 attempts, . 1/32 RERS17pb113-PT-2-ReachabilityCardinality-13 3146 m, 216 m/sec, 3145 t fired, . for RERS17pb113-PT-2-ReachabilityCardinality-12 3548 1 17.000000 0 for 0 RERS17pb113-PT-2-ReachabilityCardinality-00 VALUE PRODUCED BY AG false findpath AG false tandem / insertion EF true findpath AG false tandem / insertion EF true findpath IDL ACT RUN SUS FIN C/T C/M OBS EF 0 4 1 0 1 0 0 0 EF 0 4 1 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 5 0 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 AG 0 4 1 0 1 0 0 0 EF 0 5 0 0 1 0 0 0 MEM PG/PGLIMIT FORMULA STATUS 0/5 RERS17pb113-PT-2-ReachabilityCardinality-14 3584 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-00 398 t fired, 1 attempts, . 0/5 RERS17pb113-PT-2-ReachabilityCardinality-01 3548 t fired, 1 attempts, . 1/32 RERS17pb113-PT-2-ReachabilityCardinality-13 3699 m, 110 m/sec, 3698 t fired, . for RERS17pb113-PT-2-ReachabilityCardinality-00 754 1 3.000000 0 for 12 RERS17pb113-PT-2-ReachabilityCardinality-04 for RERS17pb113-PT-2-ReachabilityCardinality-05 for RERS17pb113-PT-2-ReachabilityCardinality-04 54 1 3.000000 0 for 33 RERS17pb113-PT-2-ReachabilityCardinality-11 411 Killed lola --conf=$BIN_DIR/configfiles/reachabilitycardinalityconf --formula=$DIR/ReachabilityCardinality.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="RERS17pb113-PT-2"
export BK_EXAMINATION="ReachabilityCardinality"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is RERS17pb113-PT-2, examination is ReachabilityCardinality"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r175-tajo-162089411000134"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/RERS17pb113-PT-2.tgz
mv RERS17pb113-PT-2 execution
cd execution
if [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "UpperBounds" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] || [ "ReachabilityCardinality" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "ReachabilityCardinality" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "ReachabilityCardinality" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "ReachabilityCardinality.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property ReachabilityCardinality.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "ReachabilityCardinality.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' ReachabilityCardinality.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "ReachabilityCardinality" = "ReachabilityDeadlock" ] || [ "ReachabilityCardinality" = "QuasiLiveness" ] || [ "ReachabilityCardinality" = "StableMarking" ] || [ "ReachabilityCardinality" = "Liveness" ] || [ "ReachabilityCardinality" = "OneSafe" ] ; then
echo "FORMULA_NAME ReachabilityCardinality"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;