fond
Model Checking Contest 2021
11th edition, Paris, France, June 23, 2021
Execution of r137-tall-162089122600722
Last Updated
Jun 28, 2021

About the Execution of LoLA for PhaseVariation-PT-D30CS100

Execution Summary
Max Memory
Used (MB)
Time wait (ms) CPU Usage (ms) I/O Wait (ms) Computed Result Execution
Status
15811.312 698047.00 1883006.00 804.70 ??????F????????T normal

Execution Chart

We display below the execution chart for this examination (boot time has been removed).

Trace from the execution

Formatting '/data/fkordon/mcc2021-input.r137-tall-162089122600722.qcow2', fmt=qcow2 size=4294967296 backing_file='/data/fkordon/mcc2021-input.qcow2' encryption=off cluster_size=65536 lazy_refcounts=off
Waiting for the VM to be ready (probing ssh)
.........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................
=====================================================================
Generated by BenchKit 2-4028
Executing tool lola
Input is PhaseVariation-PT-D30CS100, examination is CTLFireability
Time confinement is 3600 seconds
Memory confinement is 16384 MBytes
Number of cores is 4
Run identifier is r137-tall-162089122600722
=====================================================================

--------------------
preparation of the directory to be used:
/home/mcc/execution
total 30M
-rw-r--r-- 1 mcc users 15K May 5 16:58 CTLCardinality.txt
-rw-r--r-- 1 mcc users 84K May 10 09:43 CTLCardinality.xml
-rw-r--r-- 1 mcc users 19K May 5 16:58 CTLFireability.txt
-rw-r--r-- 1 mcc users 74K May 10 09:43 CTLFireability.xml
-rw-r--r-- 1 mcc users 4.2K May 6 14:48 GenericPropertiesDefinition.xml
-rw-r--r-- 1 mcc users 6.1K May 6 14:48 GenericPropertiesVerdict.xml
-rw-r--r-- 1 mcc users 4.6K Mar 28 16:25 LTLCardinality.txt
-rw-r--r-- 1 mcc users 26K Mar 28 16:25 LTLCardinality.xml
-rw-r--r-- 1 mcc users 3.4K Mar 28 16:25 LTLFireability.txt
-rw-r--r-- 1 mcc users 18K Mar 28 16:25 LTLFireability.xml
-rw-r--r-- 1 mcc users 4.3K Mar 27 07:11 ReachabilityCardinality.txt
-rw-r--r-- 1 mcc users 18K Mar 27 07:11 ReachabilityCardinality.xml
-rw-r--r-- 1 mcc users 4.4K Mar 25 08:38 ReachabilityFireability.txt
-rw-r--r-- 1 mcc users 17K Mar 25 08:38 ReachabilityFireability.xml
-rw-r--r-- 1 mcc users 1.9K Mar 22 09:16 UpperBounds.txt
-rw-r--r-- 1 mcc users 3.9K Mar 22 09:16 UpperBounds.xml
-rw-r--r-- 1 mcc users 6 May 5 16:51 equiv_col
-rw-r--r-- 1 mcc users 9 May 5 16:51 instance
-rw-r--r-- 1 mcc users 6 May 5 16:51 iscolored
-rw-r--r-- 1 mcc users 30M May 5 16:51 model.pnml

--------------------
content from stdout:

=== Data for post analysis generated by BenchKit (invocation template)

The expected result is a vector of booleans
BOOL_VECTOR

here is the order used to build the result vector(from text file)
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-00
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-01
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-02
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-03
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-04
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-05
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-06
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-07
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-08
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-09
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-10
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-11
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-12
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-13
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-14
FORMULA_NAME PhaseVariation-PT-D30CS100-CTLFireability-15

=== Now, execution of the tool begins

BK_START 1620985144679

starting LoLA
BK_INPUT PhaseVariation-PT-D30CS100
BK_EXAMINATION: CTLFireability
bin directory: /home/mcc/BenchKit/bin
current directory: /home/mcc/execution
CTLFireability

FORMULA PhaseVariation-PT-D30CS100-CTLFireability-06 FALSE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

FORMULA PhaseVariation-PT-D30CS100-CTLFireability-15 TRUE TECHNIQUES COLLATERAL_PROCESSING EXPLICIT TOPOLOGICAL STATE_COMPRESSION STUBBORN_SETS USE_NUPN UNFOLDING_TO_PT

BK_STOP 1620985842726

--------------------
content from stderr:

lola: MEM LIMIT 32
lola: MEM LIMIT 5
lola: NET
lola: input: PNML file (--pnmlnet)
lola: reading net from /home/mcc/execution/model.pnml
lola: reading pnml
lola: PNML file contains place/transition net
lola: finished parsing
lola: closed net file /home/mcc/execution/model.pnml
lola: Reading formula.
lola: Using XML format (--xmlformula)
lola: reading XML formula
lola: reading formula from /home/mcc/execution/CTLFireability.xml
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: RELEASE
lola: RELEASE
lola: rewrite Frontend/Parser/formula_rewrite.k:253
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:439
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:544
lola: rewrite Frontend/Parser/formula_rewrite.k:388
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:317
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:314
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:334
lola: rewrite Frontend/Parser/formula_rewrite.k:299
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:394
lola: rewrite Frontend/Parser/formula_rewrite.k:325
lola: rewrite Frontend/Parser/formula_rewrite.k:337
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:547
lola: rewrite Frontend/Parser/formula_rewrite.k:391
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:328
lola: rewrite Frontend/Parser/formula_rewrite.k:322
lola: rewrite Frontend/Parser/formula_rewrite.k:331
lola: rewrite Frontend/Parser/formula_rewrite.k:296
lola: rewrite Frontend/Parser/formula_rewrite.k:250
lola: RELEASE
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 205 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 210 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 215 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 2.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 1.000000 secs.
lola: Created skeleton in 2.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 0 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 220 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
lola: Rule S: 52 transitions removed,2 places removed
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 225 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 230 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 235 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 240 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 245 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 250 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 255 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 260 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 265 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 270 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 0 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 275 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: Created skeleton in 1.000000 secs.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 280 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 285 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 290 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 295 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 300 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 305 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 310 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 315 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 320 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 325 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 330 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 335 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 340 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 345 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 350 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 355 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 360 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 365 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 370 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 375 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 380 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 385 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 390 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 395 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 400 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 405 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 410 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 415 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 420 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 425 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 430 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 435 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 440 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 445 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 450 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 455 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 460 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 465 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 470 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 475 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 480 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 485 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 490 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 495 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 500 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 505 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 510 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 515 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 520 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 525 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 530 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 535 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:814
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL 1 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 540 secs. Pages in use: 0
# running tasks: 0 of 4 Visible: 16
lola: LAUNCH task # 23 (type EXCL) for 22 PhaseVariation-PT-D30CS100-CTLFireability-06
lola: time limit : 179 sec
lola: memory limit: 32 pages
lola: FINISHED task # 23 (type EXCL) for PhaseVariation-PT-D30CS100-CTLFireability-06
lola: result : false
lola: markings : 10406
lola: fired transitions : 10413
lola: time used : 2.000000
lola: memory pages used : 1
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 545 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 550 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 555 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 560 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 565 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 570 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 575 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 580 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 585 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 590 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-15: EF 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 595 secs. Pages in use: 1
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: LAUNCH task # 54 (type EXCL) for 49 PhaseVariation-PT-D30CS100-CTLFireability-15
lola: time limit : 187 sec
lola: memory limit: 32 pages
lola: LAUNCH task # 52 (type FNDP) for 49 PhaseVariation-PT-D30CS100-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 53 (type EQUN) for 49 PhaseVariation-PT-D30CS100-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: LAUNCH task # 55 (type SRCH) for 49 PhaseVariation-PT-D30CS100-CTLFireability-15
lola: time limit : 32000000 sec
lola: memory limit: 5 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:711
lola: FINISHED task # 55 (type SRCH) for PhaseVariation-PT-D30CS100-CTLFireability-15
lola: result : unknown
lola: time used : 2.000000
lola: memory pages used : 1
lola: FINISHED task # 54 (type EXCL) for PhaseVariation-PT-D30CS100-CTLFireability-15
lola: result : true
lola: markings : 6
lola: fired transitions : 5
lola: time used : 2.000000
lola: memory pages used : 1
lola: CANCELED task # 52 (type FNDP) for PhaseVariation-PT-D30CS100-CTLFireability-15 (obsolete)
lola: CANCELED task # 53 (type EQUN) for PhaseVariation-PT-D30CS100-CTLFireability-15 (obsolete)
lola: FINISHED task # 52 (type FNDP) for PhaseVariation-PT-D30CS100-CTLFireability-15
lola: result : unknown
lola: fired transitions : 3
lola: tried executions : 2
lola: time used : 2.000000
lola: memory pages used : 0
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 600 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
sara: try reading problem file /home/mcc/execution/CTLFireability-53.sara.
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 605 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 610 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 615 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 620 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 625 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 630 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 635 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 640 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 645 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 650 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 655 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 660 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 665 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 670 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 675 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 680 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 685 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 690 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:813
FINISHED FORMULA: CATEGORY VALUE PRODUCED BY
PhaseVariation-PT-D30CS100-CTLFireability-06: CTL false CTL model checker
PhaseVariation-PT-D30CS100-CTLFireability-15: EF true state space

PENDING FORMULAS: CATEGORY IDL ACT RUN SUS FIN C/T C/M OBS
PhaseVariation-PT-D30CS100-CTLFireability-00: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-01: EF 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-02: DISJ 0 0 0 0 2 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-03: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-04: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-05: F 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-07: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-08: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-09: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-10: EG 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-11: CTL 1 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-12: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-13: CTL 0 0 0 0 1 0 0 0
PhaseVariation-PT-D30CS100-CTLFireability-14: CTL 0 0 0 0 1 0 0 0

TASK CATEGORY TYPE TIME/TLIMIT MEM PG/PGLIMIT FORMULA STATUS

Time elapsed: 695 secs. Pages in use: 2
# running tasks: 0 of 4 Visible: 16
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:813
lola: rewrite Frontend/Parser/formula_rewrite.k:809
lola: LAUNCH task # 38 (type EXCL) for 37 PhaseVariation-PT-D30CS100-CTLFireability-11
lola: time limit : 193 sec
lola: memory limit: 32 pages
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:812
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:815
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:806
lola: rewrite Frontend/Parser/formula_rewrite.k:811
lola: rewrite Frontend/Parser/formula_rewrite.k:807
lola: rewrite Frontend/Parser/formula_rewrite.k:814
lola: rewrite Frontend/Parser/formula_rewrite.k:808
lola: rewrite Frontend/Parser/formula_rewrite.k:806
/home/mcc/BenchKit/BenchKit_head.sh: line 62: 411 Killed lola --conf=$BIN_DIR/configfiles/ctlfireabilityconf --formula=$DIR/CTLFireability.xml --verdictfile=$DIR/GenericPropertiesVerdict.xml $DIR/model.pnml

Sequence of Actions to be Executed by the VM

This is useful if one wants to reexecute the tool in the VM from the submitted image disk.

set -x
# this is for BenchKit: configuration of major elements for the test
export BK_INPUT="PhaseVariation-PT-D30CS100"
export BK_EXAMINATION="CTLFireability"
export BK_TOOL="lola"
export BK_RESULT_DIR="/tmp/BK_RESULTS/OUTPUTS"
export BK_TIME_CONFINEMENT="3600"
export BK_MEMORY_CONFINEMENT="16384"
export BK_BIN_PATH="/home/mcc/BenchKit/bin/"

# this is specific to your benchmark or test

export BIN_DIR="$HOME/BenchKit/bin"

# remove the execution directoty if it exists (to avoid increse of .vmdk images)
if [ -d execution ] ; then
rm -rf execution
fi

# this is for BenchKit: explicit launching of the test
echo "====================================================================="
echo " Generated by BenchKit 2-4028"
echo " Executing tool lola"
echo " Input is PhaseVariation-PT-D30CS100, examination is CTLFireability"
echo " Time confinement is $BK_TIME_CONFINEMENT seconds"
echo " Memory confinement is 16384 MBytes"
echo " Number of cores is 4"
echo " Run identifier is r137-tall-162089122600722"
echo "====================================================================="
echo
echo "--------------------"
echo "preparation of the directory to be used:"

tar xzf /home/mcc/BenchKit/INPUTS/PhaseVariation-PT-D30CS100.tgz
mv PhaseVariation-PT-D30CS100 execution
cd execution
if [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "UpperBounds" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] || [ "CTLFireability" = "StateSpace" ]; then
rm -f GenericPropertiesVerdict.xml
fi
pwd
ls -lh

echo
echo "--------------------"
echo "content from stdout:"
echo
echo "=== Data for post analysis generated by BenchKit (invocation template)"
echo
if [ "CTLFireability" = "UpperBounds" ] ; then
echo "The expected result is a vector of positive values"
echo NUM_VECTOR
elif [ "CTLFireability" != "StateSpace" ] ; then
echo "The expected result is a vector of booleans"
echo BOOL_VECTOR
else
echo "no data necessary for post analysis"
fi
echo
if [ -f "CTLFireability.txt" ] ; then
echo "here is the order used to build the result vector(from text file)"
for x in $(grep Property CTLFireability.txt | cut -d ' ' -f 2 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ -f "CTLFireability.xml" ] ; then # for cunf (txt files deleted;-)
echo echo "here is the order used to build the result vector(from xml file)"
for x in $(grep '' CTLFireability.xml | cut -d '>' -f 2 | cut -d '<' -f 1 | sort -u) ; do
echo "FORMULA_NAME $x"
done
elif [ "CTLFireability" = "ReachabilityDeadlock" ] || [ "CTLFireability" = "QuasiLiveness" ] || [ "CTLFireability" = "StableMarking" ] || [ "CTLFireability" = "Liveness" ] || [ "CTLFireability" = "OneSafe" ] ; then
echo "FORMULA_NAME CTLFireability"
fi
echo
echo "=== Now, execution of the tool begins"
echo
echo -n "BK_START "
date -u +%s%3N
echo
timeout -s 9 $BK_TIME_CONFINEMENT bash -c "/home/mcc/BenchKit/BenchKit_head.sh 2> STDERR ; echo ; echo -n \"BK_STOP \" ; date -u +%s%3N"
if [ $? -eq 137 ] ; then
echo
echo "BK_TIME_CONFINEMENT_REACHED"
fi
echo
echo "--------------------"
echo "content from stderr:"
echo
cat STDERR ;